1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include "amdgpu_display.h"
33 #include "soc15_common.h"
34 #include "gc/gc_11_0_0_offset.h"
35 #include "gc/gc_11_0_0_sh_mask.h"
36 #include <asm/div64.h>
37
38 #include <linux/pci.h>
39 #include <linux/pm_runtime.h>
40 #include <drm/drm_crtc_helper.h>
41 #include <drm/drm_damage_helper.h>
42 #include <drm/drm_drv.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_fb_helper.h>
45 #include <drm/drm_gem_framebuffer_helper.h>
46 #include <drm/drm_fourcc.h>
47 #include <drm/drm_modeset_helper.h>
48 #include <drm/drm_vblank.h>
49
50 /**
51 * amdgpu_display_hotplug_work_func - work handler for display hotplug event
52 *
53 * @work: work struct pointer
54 *
55 * This is the hotplug event work handler (all ASICs).
56 * The work gets scheduled from the IRQ handler if there
57 * was a hotplug interrupt. It walks through the connector table
58 * and calls hotplug handler for each connector. After this, it sends
59 * a DRM hotplug event to alert userspace.
60 *
61 * This design approach is required in order to defer hotplug event handling
62 * from the IRQ handler to a work handler because hotplug handler has to use
63 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
64 * sleep).
65 */
amdgpu_display_hotplug_work_func(struct work_struct * work)66 void amdgpu_display_hotplug_work_func(struct work_struct *work)
67 {
68 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
69 hotplug_work.work);
70 struct drm_device *dev = adev_to_drm(adev);
71 struct drm_mode_config *mode_config = &dev->mode_config;
72 struct drm_connector *connector;
73 struct drm_connector_list_iter iter;
74
75 mutex_lock(&mode_config->mutex);
76 drm_connector_list_iter_begin(dev, &iter);
77 drm_for_each_connector_iter(connector, &iter)
78 amdgpu_connector_hotplug(connector);
79 drm_connector_list_iter_end(&iter);
80 mutex_unlock(&mode_config->mutex);
81 /* Just fire off a uevent and let userspace tell us what to do */
82 drm_helper_hpd_irq_event(dev);
83 }
84
85 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
86 struct amdgpu_framebuffer *rfb,
87 const struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_gem_object *obj);
89
amdgpu_display_flip_callback(struct dma_fence * f,struct dma_fence_cb * cb)90 static void amdgpu_display_flip_callback(struct dma_fence *f,
91 struct dma_fence_cb *cb)
92 {
93 struct amdgpu_flip_work *work =
94 container_of(cb, struct amdgpu_flip_work, cb);
95
96 dma_fence_put(f);
97 schedule_work(&work->flip_work.work);
98 }
99
amdgpu_display_flip_handle_fence(struct amdgpu_flip_work * work,struct dma_fence ** f)100 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
101 struct dma_fence **f)
102 {
103 struct dma_fence *fence = *f;
104
105 if (fence == NULL)
106 return false;
107
108 *f = NULL;
109
110 if (!dma_fence_add_callback(fence, &work->cb,
111 amdgpu_display_flip_callback))
112 return true;
113
114 dma_fence_put(fence);
115 return false;
116 }
117
amdgpu_display_flip_work_func(struct work_struct * __work)118 static void amdgpu_display_flip_work_func(struct work_struct *__work)
119 {
120 struct delayed_work *delayed_work =
121 container_of(__work, struct delayed_work, work);
122 struct amdgpu_flip_work *work =
123 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
124 struct amdgpu_device *adev = work->adev;
125 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
126
127 struct drm_crtc *crtc = &amdgpu_crtc->base;
128 unsigned long flags;
129 unsigned int i;
130 int vpos, hpos;
131
132 for (i = 0; i < work->shared_count; ++i)
133 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
134 return;
135
136 /* Wait until we're out of the vertical blank period before the one
137 * targeted by the flip
138 */
139 if (amdgpu_crtc->enabled &&
140 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
141 &vpos, &hpos, NULL, NULL,
142 &crtc->hwmode)
143 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
144 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
145 (int)(work->target_vblank -
146 amdgpu_get_vblank_counter_kms(crtc)) > 0) {
147 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
148 return;
149 }
150
151 /* We borrow the event spin lock for protecting flip_status */
152 spin_lock_irqsave(&crtc->dev->event_lock, flags);
153
154 /* Do the flip (mmio) */
155 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
156
157 /* Set the flip status */
158 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
159 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
160
161
162 drm_dbg_vbl(adev_to_drm(adev),
163 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
164 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
165
166 }
167
168 /*
169 * Handle unpin events outside the interrupt handler proper.
170 */
amdgpu_display_unpin_work_func(struct work_struct * __work)171 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
172 {
173 struct amdgpu_flip_work *work =
174 container_of(__work, struct amdgpu_flip_work, unpin_work);
175 int r;
176
177 /* unpin of the old buffer */
178 r = amdgpu_bo_reserve(work->old_abo, true);
179 if (likely(r == 0)) {
180 amdgpu_bo_unpin(work->old_abo);
181 amdgpu_bo_unreserve(work->old_abo);
182 } else
183 DRM_ERROR("failed to reserve buffer after flip\n");
184
185 amdgpu_bo_unref(&work->old_abo);
186 kfree(work->shared);
187 kfree(work);
188 }
189
amdgpu_display_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)190 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
191 struct drm_framebuffer *fb,
192 struct drm_pending_vblank_event *event,
193 uint32_t page_flip_flags, uint32_t target,
194 struct drm_modeset_acquire_ctx *ctx)
195 {
196 struct drm_device *dev = crtc->dev;
197 struct amdgpu_device *adev = drm_to_adev(dev);
198 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
199 struct drm_gem_object *obj;
200 struct amdgpu_flip_work *work;
201 struct amdgpu_bo *new_abo;
202 unsigned long flags;
203 u64 tiling_flags;
204 int i, r;
205
206 work = kzalloc(sizeof(*work), GFP_KERNEL);
207 if (work == NULL)
208 return -ENOMEM;
209
210 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
211 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
212
213 work->event = event;
214 work->adev = adev;
215 work->crtc_id = amdgpu_crtc->crtc_id;
216 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
217
218 /* schedule unpin of the old buffer */
219 obj = crtc->primary->fb->obj[0];
220
221 /* take a reference to the old object */
222 work->old_abo = gem_to_amdgpu_bo(obj);
223 amdgpu_bo_ref(work->old_abo);
224
225 obj = fb->obj[0];
226 new_abo = gem_to_amdgpu_bo(obj);
227
228 /* pin the new buffer */
229 r = amdgpu_bo_reserve(new_abo, false);
230 if (unlikely(r != 0)) {
231 DRM_ERROR("failed to reserve new abo buffer before flip\n");
232 goto cleanup;
233 }
234
235 if (!adev->enable_virtual_display) {
236 r = amdgpu_bo_pin(new_abo,
237 amdgpu_display_supported_domains(adev, new_abo->flags));
238 if (unlikely(r != 0)) {
239 DRM_ERROR("failed to pin new abo buffer before flip\n");
240 goto unreserve;
241 }
242 }
243
244 r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
245 if (unlikely(r != 0)) {
246 DRM_ERROR("%p bind failed\n", new_abo);
247 goto unpin;
248 }
249
250 r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
251 &work->shared_count,
252 &work->shared);
253 if (unlikely(r != 0)) {
254 DRM_ERROR("failed to get fences for buffer\n");
255 goto unpin;
256 }
257
258 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
259 amdgpu_bo_unreserve(new_abo);
260
261 if (!adev->enable_virtual_display)
262 work->base = amdgpu_bo_gpu_offset(new_abo);
263 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
264 amdgpu_get_vblank_counter_kms(crtc);
265
266 /* we borrow the event spin lock for protecting flip_wrok */
267 spin_lock_irqsave(&crtc->dev->event_lock, flags);
268 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
269 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
270 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
271 r = -EBUSY;
272 goto pflip_cleanup;
273 }
274
275 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
276 amdgpu_crtc->pflip_works = work;
277
278
279 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
280 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
281 /* update crtc fb */
282 crtc->primary->fb = fb;
283 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
284 amdgpu_display_flip_work_func(&work->flip_work.work);
285 return 0;
286
287 pflip_cleanup:
288 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
289 DRM_ERROR("failed to reserve new abo in error path\n");
290 goto cleanup;
291 }
292 unpin:
293 if (!adev->enable_virtual_display)
294 amdgpu_bo_unpin(new_abo);
295
296 unreserve:
297 amdgpu_bo_unreserve(new_abo);
298
299 cleanup:
300 amdgpu_bo_unref(&work->old_abo);
301 for (i = 0; i < work->shared_count; ++i)
302 dma_fence_put(work->shared[i]);
303 kfree(work->shared);
304 kfree(work);
305
306 return r;
307 }
308
amdgpu_display_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)309 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
310 struct drm_modeset_acquire_ctx *ctx)
311 {
312 struct drm_device *dev;
313 struct amdgpu_device *adev;
314 struct drm_crtc *crtc;
315 bool active = false;
316 int ret;
317
318 if (!set || !set->crtc)
319 return -EINVAL;
320
321 dev = set->crtc->dev;
322
323 ret = pm_runtime_get_sync(dev->dev);
324 if (ret < 0)
325 goto out;
326
327 ret = drm_crtc_helper_set_config(set, ctx);
328
329 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
330 if (crtc->enabled)
331 active = true;
332
333 pm_runtime_mark_last_busy(dev->dev);
334
335 adev = drm_to_adev(dev);
336 /* if we have active crtcs and we don't have a power ref,
337 * take the current one
338 */
339 if (active && !adev->have_disp_power_ref) {
340 adev->have_disp_power_ref = true;
341 return ret;
342 }
343 /* if we have no active crtcs, then drop the power ref
344 * we got before
345 */
346 if (!active && adev->have_disp_power_ref) {
347 pm_runtime_put_autosuspend(dev->dev);
348 adev->have_disp_power_ref = false;
349 }
350
351 out:
352 /* drop the power reference we got coming in here */
353 pm_runtime_put_autosuspend(dev->dev);
354 return ret;
355 }
356
357 static const char *encoder_names[41] = {
358 "NONE",
359 "INTERNAL_LVDS",
360 "INTERNAL_TMDS1",
361 "INTERNAL_TMDS2",
362 "INTERNAL_DAC1",
363 "INTERNAL_DAC2",
364 "INTERNAL_SDVOA",
365 "INTERNAL_SDVOB",
366 "SI170B",
367 "CH7303",
368 "CH7301",
369 "INTERNAL_DVO1",
370 "EXTERNAL_SDVOA",
371 "EXTERNAL_SDVOB",
372 "TITFP513",
373 "INTERNAL_LVTM1",
374 "VT1623",
375 "HDMI_SI1930",
376 "HDMI_INTERNAL",
377 "INTERNAL_KLDSCP_TMDS1",
378 "INTERNAL_KLDSCP_DVO1",
379 "INTERNAL_KLDSCP_DAC1",
380 "INTERNAL_KLDSCP_DAC2",
381 "SI178",
382 "MVPU_FPGA",
383 "INTERNAL_DDI",
384 "VT1625",
385 "HDMI_SI1932",
386 "DP_AN9801",
387 "DP_DP501",
388 "INTERNAL_UNIPHY",
389 "INTERNAL_KLDSCP_LVTMA",
390 "INTERNAL_UNIPHY1",
391 "INTERNAL_UNIPHY2",
392 "NUTMEG",
393 "TRAVIS",
394 "INTERNAL_VCE",
395 "INTERNAL_UNIPHY3",
396 "HDMI_ANX9805",
397 "INTERNAL_AMCLK",
398 "VIRTUAL",
399 };
400
401 static const char *hpd_names[6] = {
402 "HPD1",
403 "HPD2",
404 "HPD3",
405 "HPD4",
406 "HPD5",
407 "HPD6",
408 };
409
amdgpu_display_print_display_setup(struct drm_device * dev)410 void amdgpu_display_print_display_setup(struct drm_device *dev)
411 {
412 struct drm_connector *connector;
413 struct amdgpu_connector *amdgpu_connector;
414 struct drm_encoder *encoder;
415 struct amdgpu_encoder *amdgpu_encoder;
416 struct drm_connector_list_iter iter;
417 uint32_t devices;
418 int i = 0;
419
420 drm_connector_list_iter_begin(dev, &iter);
421 DRM_INFO("AMDGPU Display Connectors\n");
422 drm_for_each_connector_iter(connector, &iter) {
423 amdgpu_connector = to_amdgpu_connector(connector);
424 DRM_INFO("Connector %d:\n", i);
425 DRM_INFO(" %s\n", connector->name);
426 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
427 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
428 if (amdgpu_connector->ddc_bus) {
429 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
430 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
431 amdgpu_connector->ddc_bus->rec.mask_data_reg,
432 amdgpu_connector->ddc_bus->rec.a_clk_reg,
433 amdgpu_connector->ddc_bus->rec.a_data_reg,
434 amdgpu_connector->ddc_bus->rec.en_clk_reg,
435 amdgpu_connector->ddc_bus->rec.en_data_reg,
436 amdgpu_connector->ddc_bus->rec.y_clk_reg,
437 amdgpu_connector->ddc_bus->rec.y_data_reg);
438 if (amdgpu_connector->router.ddc_valid)
439 DRM_INFO(" DDC Router 0x%x/0x%x\n",
440 amdgpu_connector->router.ddc_mux_control_pin,
441 amdgpu_connector->router.ddc_mux_state);
442 if (amdgpu_connector->router.cd_valid)
443 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
444 amdgpu_connector->router.cd_mux_control_pin,
445 amdgpu_connector->router.cd_mux_state);
446 } else {
447 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
448 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
449 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
450 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
451 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
452 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
453 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
454 }
455 DRM_INFO(" Encoders:\n");
456 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
457 amdgpu_encoder = to_amdgpu_encoder(encoder);
458 devices = amdgpu_encoder->devices & amdgpu_connector->devices;
459 if (devices) {
460 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
461 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
462 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
463 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
464 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
465 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
466 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
467 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
468 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
469 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
470 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
471 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
472 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
473 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
474 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
475 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
476 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
477 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
478 if (devices & ATOM_DEVICE_TV1_SUPPORT)
479 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
480 if (devices & ATOM_DEVICE_CV_SUPPORT)
481 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
482 }
483 }
484 i++;
485 }
486 drm_connector_list_iter_end(&iter);
487 }
488
amdgpu_display_ddc_probe(struct amdgpu_connector * amdgpu_connector,bool use_aux)489 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
490 bool use_aux)
491 {
492 u8 out = 0x0;
493 u8 buf[8];
494 int ret;
495 struct i2c_msg msgs[] = {
496 {
497 .addr = DDC_ADDR,
498 .flags = 0,
499 .len = 1,
500 .buf = &out,
501 },
502 {
503 .addr = DDC_ADDR,
504 .flags = I2C_M_RD,
505 .len = 8,
506 .buf = buf,
507 }
508 };
509
510 /* on hw with routers, select right port */
511 if (amdgpu_connector->router.ddc_valid)
512 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
513
514 if (use_aux)
515 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
516 else
517 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
518
519 if (ret != 2)
520 /* Couldn't find an accessible DDC on this connector */
521 return false;
522 /* Probe also for valid EDID header
523 * EDID header starts with:
524 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
525 * Only the first 6 bytes must be valid as
526 * drm_edid_block_valid() can fix the last 2 bytes
527 */
528 if (drm_edid_header_is_valid(buf) < 6) {
529 /* Couldn't find an accessible EDID on this
530 * connector
531 */
532 return false;
533 }
534 return true;
535 }
536
amdgpu_dirtyfb(struct drm_framebuffer * fb,struct drm_file * file,unsigned int flags,unsigned int color,struct drm_clip_rect * clips,unsigned int num_clips)537 static int amdgpu_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file,
538 unsigned int flags, unsigned int color,
539 struct drm_clip_rect *clips, unsigned int num_clips)
540 {
541
542 if (file)
543 return -ENOSYS;
544
545 return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips,
546 num_clips);
547 }
548
549 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
550 .destroy = drm_gem_fb_destroy,
551 .create_handle = drm_gem_fb_create_handle,
552 };
553
554 static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
555 .destroy = drm_gem_fb_destroy,
556 .create_handle = drm_gem_fb_create_handle,
557 .dirty = amdgpu_dirtyfb
558 };
559
amdgpu_display_supported_domains(struct amdgpu_device * adev,uint64_t bo_flags)560 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
561 uint64_t bo_flags)
562 {
563 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
564
565 #if defined(CONFIG_DRM_AMD_DC)
566 /*
567 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
568 * is not supported for this board. But this mapping is required
569 * to avoid hang caused by placement of scanout BO in GTT on certain
570 * APUs. So force the BO placement to VRAM in case this architecture
571 * will not allow USWC mappings.
572 * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
573 */
574 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
575 amdgpu_bo_support_uswc(bo_flags) &&
576 adev->dc_enabled &&
577 adev->mode_info.gpu_vm_support)
578 domain |= AMDGPU_GEM_DOMAIN_GTT;
579 #endif
580
581 return domain;
582 }
583
584 static const struct drm_format_info dcc_formats[] = {
585 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
586 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
587 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
588 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
589 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
590 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
591 .has_alpha = true, },
592 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
593 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
594 .has_alpha = true, },
595 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
596 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
597 .has_alpha = true, },
598 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
599 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
600 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
601 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
602 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
603 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
604 .has_alpha = true, },
605 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
606 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
607 .has_alpha = true, },
608 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
609 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
610 };
611
612 static const struct drm_format_info dcc_retile_formats[] = {
613 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
614 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
615 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
616 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
617 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
618 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
619 .has_alpha = true, },
620 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
621 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
622 .has_alpha = true, },
623 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
624 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
625 .has_alpha = true, },
626 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
627 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
628 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
629 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
630 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
631 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
632 .has_alpha = true, },
633 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
634 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
635 .has_alpha = true, },
636 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
637 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
638 };
639
640 static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],int num_formats,u32 format)641 lookup_format_info(const struct drm_format_info formats[],
642 int num_formats, u32 format)
643 {
644 int i;
645
646 for (i = 0; i < num_formats; i++) {
647 if (formats[i].format == format)
648 return &formats[i];
649 }
650
651 return NULL;
652 }
653
654 const struct drm_format_info *
amdgpu_lookup_format_info(u32 format,uint64_t modifier)655 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
656 {
657 if (!IS_AMD_FMT_MOD(modifier))
658 return NULL;
659
660 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
661 return lookup_format_info(dcc_retile_formats,
662 ARRAY_SIZE(dcc_retile_formats),
663 format);
664
665 if (AMD_FMT_MOD_GET(DCC, modifier))
666 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
667 format);
668
669 /* returning NULL will cause the default format structs to be used. */
670 return NULL;
671 }
672
673
674 /*
675 * Tries to extract the renderable DCC offset from the opaque metadata attached
676 * to the buffer.
677 */
678 static int
extract_render_dcc_offset(struct amdgpu_device * adev,struct drm_gem_object * obj,uint64_t * offset)679 extract_render_dcc_offset(struct amdgpu_device *adev,
680 struct drm_gem_object *obj,
681 uint64_t *offset)
682 {
683 struct amdgpu_bo *rbo;
684 int r = 0;
685 uint32_t metadata[10]; /* Something that fits a descriptor + header. */
686 uint32_t size;
687
688 rbo = gem_to_amdgpu_bo(obj);
689 r = amdgpu_bo_reserve(rbo, false);
690
691 if (unlikely(r)) {
692 /* Don't show error message when returning -ERESTARTSYS */
693 if (r != -ERESTARTSYS)
694 DRM_ERROR("Unable to reserve buffer: %d\n", r);
695 return r;
696 }
697
698 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
699 amdgpu_bo_unreserve(rbo);
700
701 if (r)
702 return r;
703
704 /*
705 * The first word is the metadata version, and we need space for at least
706 * the version + pci vendor+device id + 8 words for a descriptor.
707 */
708 if (size < 40 || metadata[0] != 1)
709 return -EINVAL;
710
711 if (adev->family >= AMDGPU_FAMILY_NV) {
712 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
713 *offset = ((u64)metadata[9] << 16u) |
714 ((metadata[8] & 0xFF000000u) >> 16);
715 } else {
716 /* resource word 5/7 META_DATA_ADDRESS */
717 *offset = ((u64)metadata[9] << 8u) |
718 ((u64)(metadata[7] & 0x1FE0000u) << 23);
719 }
720
721 return 0;
722 }
723
convert_tiling_flags_to_modifier(struct amdgpu_framebuffer * afb)724 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
725 {
726 struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
727 uint64_t modifier = 0;
728 int num_pipes = 0;
729 int num_pkrs = 0;
730
731 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
732 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
733
734 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
735 modifier = DRM_FORMAT_MOD_LINEAR;
736 } else {
737 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
738 bool has_xor = swizzle >= 16;
739 int block_size_bits;
740 int version;
741 int pipe_xor_bits = 0;
742 int bank_xor_bits = 0;
743 int packers = 0;
744 int rb = 0;
745 int pipes = ilog2(num_pipes);
746 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
747
748 switch (swizzle >> 2) {
749 case 0: /* 256B */
750 block_size_bits = 8;
751 break;
752 case 1: /* 4KiB */
753 case 5: /* 4KiB _X */
754 block_size_bits = 12;
755 break;
756 case 2: /* 64KiB */
757 case 4: /* 64 KiB _T */
758 case 6: /* 64 KiB _X */
759 block_size_bits = 16;
760 break;
761 case 7: /* 256 KiB */
762 block_size_bits = 18;
763 break;
764 default:
765 /* RESERVED or VAR */
766 return -EINVAL;
767 }
768
769 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
770 version = AMD_FMT_MOD_TILE_VER_GFX11;
771 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
772 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
773 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
774 version = AMD_FMT_MOD_TILE_VER_GFX10;
775 else
776 version = AMD_FMT_MOD_TILE_VER_GFX9;
777
778 switch (swizzle & 3) {
779 case 0: /* Z microtiling */
780 return -EINVAL;
781 case 1: /* S microtiling */
782 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
783 if (!has_xor)
784 version = AMD_FMT_MOD_TILE_VER_GFX9;
785 }
786 break;
787 case 2:
788 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
789 if (!has_xor && afb->base.format->cpp[0] != 4)
790 version = AMD_FMT_MOD_TILE_VER_GFX9;
791 }
792 break;
793 case 3:
794 break;
795 }
796
797 if (has_xor) {
798 if (num_pipes == num_pkrs && num_pkrs == 0) {
799 DRM_ERROR("invalid number of pipes and packers\n");
800 return -EINVAL;
801 }
802
803 switch (version) {
804 case AMD_FMT_MOD_TILE_VER_GFX11:
805 pipe_xor_bits = min(block_size_bits - 8, pipes);
806 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
807 break;
808 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
809 pipe_xor_bits = min(block_size_bits - 8, pipes);
810 packers = min(block_size_bits - 8 - pipe_xor_bits,
811 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
812 break;
813 case AMD_FMT_MOD_TILE_VER_GFX10:
814 pipe_xor_bits = min(block_size_bits - 8, pipes);
815 break;
816 case AMD_FMT_MOD_TILE_VER_GFX9:
817 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
818 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
819 pipe_xor_bits = min(block_size_bits - 8, pipes +
820 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
821 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
822 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
823 break;
824 }
825 }
826
827 modifier = AMD_FMT_MOD |
828 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
829 AMD_FMT_MOD_SET(TILE_VERSION, version) |
830 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
831 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
832 AMD_FMT_MOD_SET(PACKERS, packers);
833
834 if (dcc_offset != 0) {
835 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
836 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
837 const struct drm_format_info *format_info;
838 u64 render_dcc_offset;
839
840 /* Enable constant encode on RAVEN2 and later. */
841 bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
842 (adev->asic_type == CHIP_RAVEN &&
843 adev->external_rev_id >= 0x81)) &&
844 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
845
846 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
847 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
848 AMD_FMT_MOD_DCC_BLOCK_256B;
849
850 modifier |= AMD_FMT_MOD_SET(DCC, 1) |
851 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
852 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
853 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
854 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
855
856 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
857 afb->base.pitches[1] =
858 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
859
860 /*
861 * If the userspace driver uses retiling the tiling flags do not contain
862 * info on the renderable DCC buffer. Luckily the opaque metadata contains
863 * the info so we can try to extract it. The kernel does not use this info
864 * but we should convert it to a modifier plane for getfb2, so the
865 * userspace driver that gets it doesn't have to juggle around another DCC
866 * plane internally.
867 */
868 if (extract_render_dcc_offset(adev, afb->base.obj[0],
869 &render_dcc_offset) == 0 &&
870 render_dcc_offset != 0 &&
871 render_dcc_offset != afb->base.offsets[1] &&
872 render_dcc_offset < UINT_MAX) {
873 uint32_t dcc_block_bits; /* of base surface data */
874
875 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
876 afb->base.offsets[2] = render_dcc_offset;
877
878 if (adev->family >= AMDGPU_FAMILY_NV) {
879 int extra_pipe = 0;
880
881 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) &&
882 pipes == packers && pipes > 1)
883 extra_pipe = 1;
884
885 dcc_block_bits = max(20, 16 + pipes + extra_pipe);
886 } else {
887 modifier |= AMD_FMT_MOD_SET(RB, rb) |
888 AMD_FMT_MOD_SET(PIPE, pipes);
889 dcc_block_bits = max(20, 18 + rb);
890 }
891
892 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
893 afb->base.pitches[2] = ALIGN(afb->base.width,
894 1u << ((dcc_block_bits + 1) / 2));
895 }
896 format_info = amdgpu_lookup_format_info(afb->base.format->format,
897 modifier);
898 if (!format_info)
899 return -EINVAL;
900
901 afb->base.format = format_info;
902 }
903 }
904
905 afb->base.modifier = modifier;
906 afb->base.flags |= DRM_MODE_FB_MODIFIERS;
907 return 0;
908 }
909
910 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
check_tiling_flags_gfx6(struct amdgpu_framebuffer * afb)911 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
912 {
913 u64 micro_tile_mode;
914
915 /* Zero swizzle mode means linear */
916 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
917 return 0;
918
919 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
920 switch (micro_tile_mode) {
921 case 0: /* DISPLAY */
922 case 3: /* RENDER */
923 return 0;
924 default:
925 drm_dbg_kms(afb->base.dev,
926 "Micro tile mode %llu not supported for scanout\n",
927 micro_tile_mode);
928 return -EINVAL;
929 }
930 }
931
get_block_dimensions(unsigned int block_log2,unsigned int cpp,unsigned int * width,unsigned int * height)932 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
933 unsigned int *width, unsigned int *height)
934 {
935 unsigned int cpp_log2 = ilog2(cpp);
936 unsigned int pixel_log2 = block_log2 - cpp_log2;
937 unsigned int width_log2 = (pixel_log2 + 1) / 2;
938 unsigned int height_log2 = pixel_log2 - width_log2;
939
940 *width = 1 << width_log2;
941 *height = 1 << height_log2;
942 }
943
get_dcc_block_size(uint64_t modifier,bool rb_aligned,bool pipe_aligned)944 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
945 bool pipe_aligned)
946 {
947 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
948
949 switch (ver) {
950 case AMD_FMT_MOD_TILE_VER_GFX9: {
951 /*
952 * TODO: for pipe aligned we may need to check the alignment of the
953 * total size of the surface, which may need to be bigger than the
954 * natural alignment due to some HW workarounds
955 */
956 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
957 }
958 case AMD_FMT_MOD_TILE_VER_GFX10:
959 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
960 case AMD_FMT_MOD_TILE_VER_GFX11: {
961 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
962
963 if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
964 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
965 ++pipes_log2;
966
967 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
968 }
969 default:
970 return 0;
971 }
972 }
973
amdgpu_display_verify_plane(struct amdgpu_framebuffer * rfb,int plane,const struct drm_format_info * format,unsigned int block_width,unsigned int block_height,unsigned int block_size_log2)974 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
975 const struct drm_format_info *format,
976 unsigned int block_width, unsigned int block_height,
977 unsigned int block_size_log2)
978 {
979 unsigned int width = rfb->base.width /
980 ((plane && plane < format->num_planes) ? format->hsub : 1);
981 unsigned int height = rfb->base.height /
982 ((plane && plane < format->num_planes) ? format->vsub : 1);
983 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
984 unsigned int block_pitch = block_width * cpp;
985 unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
986 unsigned int block_size = 1 << block_size_log2;
987 uint64_t size;
988
989 if (rfb->base.pitches[plane] % block_pitch) {
990 drm_dbg_kms(rfb->base.dev,
991 "pitch %d for plane %d is not a multiple of block pitch %d\n",
992 rfb->base.pitches[plane], plane, block_pitch);
993 return -EINVAL;
994 }
995 if (rfb->base.pitches[plane] < min_pitch) {
996 drm_dbg_kms(rfb->base.dev,
997 "pitch %d for plane %d is less than minimum pitch %d\n",
998 rfb->base.pitches[plane], plane, min_pitch);
999 return -EINVAL;
1000 }
1001
1002 /* Force at least natural alignment. */
1003 if (rfb->base.offsets[plane] % block_size) {
1004 drm_dbg_kms(rfb->base.dev,
1005 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
1006 rfb->base.offsets[plane], plane, block_size);
1007 return -EINVAL;
1008 }
1009
1010 size = rfb->base.offsets[plane] +
1011 (uint64_t)rfb->base.pitches[plane] / block_pitch *
1012 block_size * DIV_ROUND_UP(height, block_height);
1013
1014 if (rfb->base.obj[0]->size < size) {
1015 drm_dbg_kms(rfb->base.dev,
1016 "BO size 0x%zx is less than 0x%llx required for plane %d\n",
1017 rfb->base.obj[0]->size, size, plane);
1018 return -EINVAL;
1019 }
1020
1021 return 0;
1022 }
1023
1024
amdgpu_display_verify_sizes(struct amdgpu_framebuffer * rfb)1025 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
1026 {
1027 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
1028 uint64_t modifier = rfb->base.modifier;
1029 int ret;
1030 unsigned int i, block_width, block_height, block_size_log2;
1031
1032 if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
1033 return 0;
1034
1035 for (i = 0; i < format_info->num_planes; ++i) {
1036 if (modifier == DRM_FORMAT_MOD_LINEAR) {
1037 block_width = 256 / format_info->cpp[i];
1038 block_height = 1;
1039 block_size_log2 = 8;
1040 } else {
1041 int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1042
1043 switch ((swizzle & ~3) + 1) {
1044 case DC_SW_256B_S:
1045 block_size_log2 = 8;
1046 break;
1047 case DC_SW_4KB_S:
1048 case DC_SW_4KB_S_X:
1049 block_size_log2 = 12;
1050 break;
1051 case DC_SW_64KB_S:
1052 case DC_SW_64KB_S_T:
1053 case DC_SW_64KB_S_X:
1054 block_size_log2 = 16;
1055 break;
1056 case DC_SW_VAR_S_X:
1057 block_size_log2 = 18;
1058 break;
1059 default:
1060 drm_dbg_kms(rfb->base.dev,
1061 "Swizzle mode with unknown block size: %d\n", swizzle);
1062 return -EINVAL;
1063 }
1064
1065 get_block_dimensions(block_size_log2, format_info->cpp[i],
1066 &block_width, &block_height);
1067 }
1068
1069 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1070 block_width, block_height, block_size_log2);
1071 if (ret)
1072 return ret;
1073 }
1074
1075 if (AMD_FMT_MOD_GET(DCC, modifier)) {
1076 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1077 block_size_log2 = get_dcc_block_size(modifier, false, false);
1078 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1079 &block_width, &block_height);
1080 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1081 block_width, block_height,
1082 block_size_log2);
1083 if (ret)
1084 return ret;
1085
1086 ++i;
1087 block_size_log2 = get_dcc_block_size(modifier, true, true);
1088 } else {
1089 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1090
1091 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1092 }
1093 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1094 &block_width, &block_height);
1095 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1096 block_width, block_height, block_size_log2);
1097 if (ret)
1098 return ret;
1099 }
1100
1101 return 0;
1102 }
1103
amdgpu_display_get_fb_info(const struct amdgpu_framebuffer * amdgpu_fb,uint64_t * tiling_flags,bool * tmz_surface)1104 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1105 uint64_t *tiling_flags, bool *tmz_surface)
1106 {
1107 struct amdgpu_bo *rbo;
1108 int r;
1109
1110 if (!amdgpu_fb) {
1111 *tiling_flags = 0;
1112 *tmz_surface = false;
1113 return 0;
1114 }
1115
1116 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1117 r = amdgpu_bo_reserve(rbo, false);
1118
1119 if (unlikely(r)) {
1120 /* Don't show error message when returning -ERESTARTSYS */
1121 if (r != -ERESTARTSYS)
1122 DRM_ERROR("Unable to reserve buffer: %d\n", r);
1123 return r;
1124 }
1125
1126 if (tiling_flags)
1127 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1128
1129 if (tmz_surface)
1130 *tmz_surface = amdgpu_bo_encrypted(rbo);
1131
1132 amdgpu_bo_unreserve(rbo);
1133
1134 return r;
1135 }
1136
amdgpu_display_gem_fb_verify_and_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1137 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
1138 struct amdgpu_framebuffer *rfb,
1139 struct drm_file *file_priv,
1140 const struct drm_mode_fb_cmd2 *mode_cmd,
1141 struct drm_gem_object *obj)
1142 {
1143 int ret;
1144
1145 rfb->base.obj[0] = obj;
1146 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1147 /* Verify that the modifier is supported. */
1148 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1149 mode_cmd->modifier[0])) {
1150 drm_dbg_kms(dev,
1151 "unsupported pixel format %p4cc / modifier 0x%llx\n",
1152 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1153
1154 ret = -EINVAL;
1155 goto err;
1156 }
1157
1158 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1159 if (ret)
1160 goto err;
1161
1162 if (drm_drv_uses_atomic_modeset(dev))
1163 ret = drm_framebuffer_init(dev, &rfb->base,
1164 &amdgpu_fb_funcs_atomic);
1165 else
1166 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1167
1168 if (ret)
1169 goto err;
1170
1171 return 0;
1172 err:
1173 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1174 rfb->base.obj[0] = NULL;
1175 return ret;
1176 }
1177
amdgpu_display_framebuffer_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1178 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
1179 struct amdgpu_framebuffer *rfb,
1180 const struct drm_mode_fb_cmd2 *mode_cmd,
1181 struct drm_gem_object *obj)
1182 {
1183 struct amdgpu_device *adev = drm_to_adev(dev);
1184 int ret, i;
1185
1186 /*
1187 * This needs to happen before modifier conversion as that might change
1188 * the number of planes.
1189 */
1190 for (i = 1; i < rfb->base.format->num_planes; ++i) {
1191 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1192 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1193 i, mode_cmd->handles[0], mode_cmd->handles[i]);
1194 ret = -EINVAL;
1195 return ret;
1196 }
1197 }
1198
1199 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1200 if (ret)
1201 return ret;
1202
1203 if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
1204 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1205 "GFX9+ requires FB check based on format modifier\n");
1206 ret = check_tiling_flags_gfx6(rfb);
1207 if (ret)
1208 return ret;
1209 }
1210
1211 if (!dev->mode_config.fb_modifiers_not_supported &&
1212 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1213 ret = convert_tiling_flags_to_modifier(rfb);
1214 if (ret) {
1215 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1216 rfb->tiling_flags);
1217 return ret;
1218 }
1219 }
1220
1221 ret = amdgpu_display_verify_sizes(rfb);
1222 if (ret)
1223 return ret;
1224
1225 for (i = 0; i < rfb->base.format->num_planes; ++i) {
1226 drm_gem_object_get(rfb->base.obj[0]);
1227 rfb->base.obj[i] = rfb->base.obj[0];
1228 }
1229
1230 return 0;
1231 }
1232
1233 struct drm_framebuffer *
amdgpu_display_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)1234 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1235 struct drm_file *file_priv,
1236 const struct drm_mode_fb_cmd2 *mode_cmd)
1237 {
1238 struct amdgpu_framebuffer *amdgpu_fb;
1239 struct drm_gem_object *obj;
1240 struct amdgpu_bo *bo;
1241 uint32_t domains;
1242 int ret;
1243
1244 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1245 if (obj == NULL) {
1246 drm_dbg_kms(dev,
1247 "No GEM object associated to handle 0x%08X, can't create framebuffer\n",
1248 mode_cmd->handles[0]);
1249
1250 return ERR_PTR(-ENOENT);
1251 }
1252
1253 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1254 bo = gem_to_amdgpu_bo(obj);
1255 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1256 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1257 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1258 drm_gem_object_put(obj);
1259 return ERR_PTR(-EINVAL);
1260 }
1261
1262 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1263 if (amdgpu_fb == NULL) {
1264 drm_gem_object_put(obj);
1265 return ERR_PTR(-ENOMEM);
1266 }
1267
1268 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1269 mode_cmd, obj);
1270 if (ret) {
1271 kfree(amdgpu_fb);
1272 drm_gem_object_put(obj);
1273 return ERR_PTR(ret);
1274 }
1275
1276 drm_gem_object_put(obj);
1277 return &amdgpu_fb->base;
1278 }
1279
1280 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1281 .fb_create = amdgpu_display_user_framebuffer_create,
1282 };
1283
1284 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = {
1285 { UNDERSCAN_OFF, "off" },
1286 { UNDERSCAN_ON, "on" },
1287 { UNDERSCAN_AUTO, "auto" },
1288 };
1289
1290 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = {
1291 { AMDGPU_AUDIO_DISABLE, "off" },
1292 { AMDGPU_AUDIO_ENABLE, "on" },
1293 { AMDGPU_AUDIO_AUTO, "auto" },
1294 };
1295
1296 /* XXX support different dither options? spatial, temporal, both, etc. */
1297 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = {
1298 { AMDGPU_FMT_DITHER_DISABLE, "off" },
1299 { AMDGPU_FMT_DITHER_ENABLE, "on" },
1300 };
1301
amdgpu_display_modeset_create_props(struct amdgpu_device * adev)1302 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1303 {
1304 int sz;
1305
1306 adev->mode_info.coherent_mode_property =
1307 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1308 if (!adev->mode_info.coherent_mode_property)
1309 return -ENOMEM;
1310
1311 adev->mode_info.load_detect_property =
1312 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1313 if (!adev->mode_info.load_detect_property)
1314 return -ENOMEM;
1315
1316 drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1317
1318 sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1319 adev->mode_info.underscan_property =
1320 drm_property_create_enum(adev_to_drm(adev), 0,
1321 "underscan",
1322 amdgpu_underscan_enum_list, sz);
1323
1324 adev->mode_info.underscan_hborder_property =
1325 drm_property_create_range(adev_to_drm(adev), 0,
1326 "underscan hborder", 0, 128);
1327 if (!adev->mode_info.underscan_hborder_property)
1328 return -ENOMEM;
1329
1330 adev->mode_info.underscan_vborder_property =
1331 drm_property_create_range(adev_to_drm(adev), 0,
1332 "underscan vborder", 0, 128);
1333 if (!adev->mode_info.underscan_vborder_property)
1334 return -ENOMEM;
1335
1336 sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1337 adev->mode_info.audio_property =
1338 drm_property_create_enum(adev_to_drm(adev), 0,
1339 "audio",
1340 amdgpu_audio_enum_list, sz);
1341
1342 sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1343 adev->mode_info.dither_property =
1344 drm_property_create_enum(adev_to_drm(adev), 0,
1345 "dither",
1346 amdgpu_dither_enum_list, sz);
1347
1348 if (adev->dc_enabled) {
1349 adev->mode_info.abm_level_property =
1350 drm_property_create_range(adev_to_drm(adev), 0,
1351 "abm level", 0, 4);
1352 if (!adev->mode_info.abm_level_property)
1353 return -ENOMEM;
1354 }
1355
1356 return 0;
1357 }
1358
amdgpu_display_update_priority(struct amdgpu_device * adev)1359 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1360 {
1361 /* adjustment options for the display watermarks */
1362 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1363 adev->mode_info.disp_priority = 0;
1364 else
1365 adev->mode_info.disp_priority = amdgpu_disp_priority;
1366
1367 }
1368
amdgpu_display_is_hdtv_mode(const struct drm_display_mode * mode)1369 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1370 {
1371 /* try and guess if this is a tv or a monitor */
1372 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1373 (mode->vdisplay == 576) || /* 576p */
1374 (mode->vdisplay == 720) || /* 720p */
1375 (mode->vdisplay == 1080)) /* 1080p */
1376 return true;
1377 else
1378 return false;
1379 }
1380
amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1381 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1382 const struct drm_display_mode *mode,
1383 struct drm_display_mode *adjusted_mode)
1384 {
1385 struct drm_device *dev = crtc->dev;
1386 struct drm_encoder *encoder;
1387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1388 struct amdgpu_encoder *amdgpu_encoder;
1389 struct drm_connector *connector;
1390 u32 src_v = 1, dst_v = 1;
1391 u32 src_h = 1, dst_h = 1;
1392
1393 amdgpu_crtc->h_border = 0;
1394 amdgpu_crtc->v_border = 0;
1395
1396 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1397 if (encoder->crtc != crtc)
1398 continue;
1399 amdgpu_encoder = to_amdgpu_encoder(encoder);
1400 connector = amdgpu_get_connector_for_encoder(encoder);
1401
1402 /* set scaling */
1403 if (amdgpu_encoder->rmx_type == RMX_OFF)
1404 amdgpu_crtc->rmx_type = RMX_OFF;
1405 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1406 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1407 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1408 else
1409 amdgpu_crtc->rmx_type = RMX_OFF;
1410 /* copy native mode */
1411 memcpy(&amdgpu_crtc->native_mode,
1412 &amdgpu_encoder->native_mode,
1413 sizeof(struct drm_display_mode));
1414 src_v = crtc->mode.vdisplay;
1415 dst_v = amdgpu_crtc->native_mode.vdisplay;
1416 src_h = crtc->mode.hdisplay;
1417 dst_h = amdgpu_crtc->native_mode.hdisplay;
1418
1419 /* fix up for overscan on hdmi */
1420 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1421 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1422 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1423 connector->display_info.is_hdmi &&
1424 amdgpu_display_is_hdtv_mode(mode)))) {
1425 if (amdgpu_encoder->underscan_hborder != 0)
1426 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1427 else
1428 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1429 if (amdgpu_encoder->underscan_vborder != 0)
1430 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1431 else
1432 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1433 amdgpu_crtc->rmx_type = RMX_FULL;
1434 src_v = crtc->mode.vdisplay;
1435 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1436 src_h = crtc->mode.hdisplay;
1437 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1438 }
1439 }
1440 if (amdgpu_crtc->rmx_type != RMX_OFF) {
1441 fixed20_12 a, b;
1442
1443 a.full = dfixed_const(src_v);
1444 b.full = dfixed_const(dst_v);
1445 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1446 a.full = dfixed_const(src_h);
1447 b.full = dfixed_const(dst_h);
1448 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1449 } else {
1450 amdgpu_crtc->vsc.full = dfixed_const(1);
1451 amdgpu_crtc->hsc.full = dfixed_const(1);
1452 }
1453 return true;
1454 }
1455
1456 /*
1457 * Retrieve current video scanout position of crtc on a given gpu, and
1458 * an optional accurate timestamp of when query happened.
1459 *
1460 * \param dev Device to query.
1461 * \param pipe Crtc to query.
1462 * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1463 * For driver internal use only also supports these flags:
1464 *
1465 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1466 * of a fudged earlier start of vblank.
1467 *
1468 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1469 * fudged earlier start of vblank in *vpos and the distance
1470 * to true start of vblank in *hpos.
1471 *
1472 * \param *vpos Location where vertical scanout position should be stored.
1473 * \param *hpos Location where horizontal scanout position should go.
1474 * \param *stime Target location for timestamp taken immediately before
1475 * scanout position query. Can be NULL to skip timestamp.
1476 * \param *etime Target location for timestamp taken immediately after
1477 * scanout position query. Can be NULL to skip timestamp.
1478 *
1479 * Returns vpos as a positive number while in active scanout area.
1480 * Returns vpos as a negative number inside vblank, counting the number
1481 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1482 * until start of active scanout / end of vblank."
1483 *
1484 * \return Flags, or'ed together as follows:
1485 *
1486 * DRM_SCANOUTPOS_VALID = Query successful.
1487 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1488 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1489 * this flag means that returned position may be offset by a constant but
1490 * unknown small number of scanlines wrt. real scanout position.
1491 *
1492 */
amdgpu_display_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1493 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1494 unsigned int pipe, unsigned int flags, int *vpos,
1495 int *hpos, ktime_t *stime, ktime_t *etime,
1496 const struct drm_display_mode *mode)
1497 {
1498 u32 vbl = 0, position = 0;
1499 int vbl_start, vbl_end, vtotal, ret = 0;
1500 bool in_vbl = true;
1501
1502 struct amdgpu_device *adev = drm_to_adev(dev);
1503
1504 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1505
1506 /* Get optional system timestamp before query. */
1507 if (stime)
1508 *stime = ktime_get();
1509
1510 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1511 ret |= DRM_SCANOUTPOS_VALID;
1512
1513 /* Get optional system timestamp after query. */
1514 if (etime)
1515 *etime = ktime_get();
1516
1517 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1518
1519 /* Decode into vertical and horizontal scanout position. */
1520 *vpos = position & 0x1fff;
1521 *hpos = (position >> 16) & 0x1fff;
1522
1523 /* Valid vblank area boundaries from gpu retrieved? */
1524 if (vbl > 0) {
1525 /* Yes: Decode. */
1526 ret |= DRM_SCANOUTPOS_ACCURATE;
1527 vbl_start = vbl & 0x1fff;
1528 vbl_end = (vbl >> 16) & 0x1fff;
1529 } else {
1530 /* No: Fake something reasonable which gives at least ok results. */
1531 vbl_start = mode->crtc_vdisplay;
1532 vbl_end = 0;
1533 }
1534
1535 /* Called from driver internal vblank counter query code? */
1536 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1537 /* Caller wants distance from real vbl_start in *hpos */
1538 *hpos = *vpos - vbl_start;
1539 }
1540
1541 /* Fudge vblank to start a few scanlines earlier to handle the
1542 * problem that vblank irqs fire a few scanlines before start
1543 * of vblank. Some driver internal callers need the true vblank
1544 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1545 *
1546 * The cause of the "early" vblank irq is that the irq is triggered
1547 * by the line buffer logic when the line buffer read position enters
1548 * the vblank, whereas our crtc scanout position naturally lags the
1549 * line buffer read position.
1550 */
1551 if (!(flags & USE_REAL_VBLANKSTART))
1552 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1553
1554 /* Test scanout position against vblank region. */
1555 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1556 in_vbl = false;
1557
1558 /* In vblank? */
1559 if (in_vbl)
1560 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1561
1562 /* Called from driver internal vblank counter query code? */
1563 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1564 /* Caller wants distance from fudged earlier vbl_start */
1565 *vpos -= vbl_start;
1566 return ret;
1567 }
1568
1569 /* Check if inside vblank area and apply corrective offsets:
1570 * vpos will then be >=0 in video scanout area, but negative
1571 * within vblank area, counting down the number of lines until
1572 * start of scanout.
1573 */
1574
1575 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1576 if (in_vbl && (*vpos >= vbl_start)) {
1577 vtotal = mode->crtc_vtotal;
1578
1579 /* With variable refresh rate displays the vpos can exceed
1580 * the vtotal value. Clamp to 0 to return -vbl_end instead
1581 * of guessing the remaining number of lines until scanout.
1582 */
1583 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1584 }
1585
1586 /* Correct for shifted end of vbl at vbl_end. */
1587 *vpos = *vpos - vbl_end;
1588
1589 return ret;
1590 }
1591
amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device * adev,int crtc)1592 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1593 {
1594 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1595 return AMDGPU_CRTC_IRQ_NONE;
1596
1597 switch (crtc) {
1598 case 0:
1599 return AMDGPU_CRTC_IRQ_VBLANK1;
1600 case 1:
1601 return AMDGPU_CRTC_IRQ_VBLANK2;
1602 case 2:
1603 return AMDGPU_CRTC_IRQ_VBLANK3;
1604 case 3:
1605 return AMDGPU_CRTC_IRQ_VBLANK4;
1606 case 4:
1607 return AMDGPU_CRTC_IRQ_VBLANK5;
1608 case 5:
1609 return AMDGPU_CRTC_IRQ_VBLANK6;
1610 default:
1611 return AMDGPU_CRTC_IRQ_NONE;
1612 }
1613 }
1614
amdgpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1615 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1616 bool in_vblank_irq, int *vpos,
1617 int *hpos, ktime_t *stime, ktime_t *etime,
1618 const struct drm_display_mode *mode)
1619 {
1620 struct drm_device *dev = crtc->dev;
1621 unsigned int pipe = crtc->index;
1622
1623 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1624 stime, etime, mode);
1625 }
1626
1627 static bool
amdgpu_display_robj_is_fb(struct amdgpu_device * adev,struct amdgpu_bo * robj)1628 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
1629 {
1630 struct drm_device *dev = adev_to_drm(adev);
1631 struct drm_fb_helper *fb_helper = dev->fb_helper;
1632
1633 if (!fb_helper || !fb_helper->buffer)
1634 return false;
1635
1636 if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
1637 return false;
1638
1639 return true;
1640 }
1641
amdgpu_display_suspend_helper(struct amdgpu_device * adev)1642 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1643 {
1644 struct drm_device *dev = adev_to_drm(adev);
1645 struct drm_crtc *crtc;
1646 struct drm_connector *connector;
1647 struct drm_connector_list_iter iter;
1648 int r;
1649
1650 drm_kms_helper_poll_disable(dev);
1651
1652 /* turn off display hw */
1653 drm_modeset_lock_all(dev);
1654 drm_connector_list_iter_begin(dev, &iter);
1655 drm_for_each_connector_iter(connector, &iter)
1656 drm_helper_connector_dpms(connector,
1657 DRM_MODE_DPMS_OFF);
1658 drm_connector_list_iter_end(&iter);
1659 drm_modeset_unlock_all(dev);
1660 /* unpin the front buffers and cursors */
1661 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1662 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1663 struct drm_framebuffer *fb = crtc->primary->fb;
1664 struct amdgpu_bo *robj;
1665
1666 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1667 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1668
1669 r = amdgpu_bo_reserve(aobj, true);
1670 if (r == 0) {
1671 amdgpu_bo_unpin(aobj);
1672 amdgpu_bo_unreserve(aobj);
1673 }
1674 }
1675
1676 if (!fb || !fb->obj[0])
1677 continue;
1678
1679 robj = gem_to_amdgpu_bo(fb->obj[0]);
1680 if (!amdgpu_display_robj_is_fb(adev, robj)) {
1681 r = amdgpu_bo_reserve(robj, true);
1682 if (r == 0) {
1683 amdgpu_bo_unpin(robj);
1684 amdgpu_bo_unreserve(robj);
1685 }
1686 }
1687 }
1688 return 0;
1689 }
1690
amdgpu_display_resume_helper(struct amdgpu_device * adev)1691 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1692 {
1693 struct drm_device *dev = adev_to_drm(adev);
1694 struct drm_connector *connector;
1695 struct drm_connector_list_iter iter;
1696 struct drm_crtc *crtc;
1697 int r;
1698
1699 /* pin cursors */
1700 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1702
1703 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1704 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1705
1706 r = amdgpu_bo_reserve(aobj, true);
1707 if (r == 0) {
1708 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1709 if (r != 0)
1710 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1711 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1712 amdgpu_bo_unreserve(aobj);
1713 }
1714 }
1715 }
1716
1717 drm_helper_resume_force_mode(dev);
1718
1719 /* turn on display hw */
1720 drm_modeset_lock_all(dev);
1721
1722 drm_connector_list_iter_begin(dev, &iter);
1723 drm_for_each_connector_iter(connector, &iter)
1724 drm_helper_connector_dpms(connector,
1725 DRM_MODE_DPMS_ON);
1726 drm_connector_list_iter_end(&iter);
1727
1728 drm_modeset_unlock_all(dev);
1729
1730 drm_kms_helper_poll_enable(dev);
1731
1732 return 0;
1733 }
1734
1735
