1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <drm/drm_edid.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/drm_dp_helper.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33 #include "atom.h"
34 #include "atombios_encoders.h"
35 #include "atombios_dp.h"
36 #include "amdgpu_connectors.h"
37 #include "amdgpu_i2c.h"
38 #include "amdgpu_display.h"
39
40 #include <linux/pm_runtime.h>
41
amdgpu_connector_hotplug(struct drm_connector * connector)42 void amdgpu_connector_hotplug(struct drm_connector *connector)
43 {
44 struct drm_device *dev = connector->dev;
45 struct amdgpu_device *adev = drm_to_adev(dev);
46 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
47
48 /* bail if the connector does not have hpd pin, e.g.,
49 * VGA, TV, etc.
50 */
51 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
52 return;
53
54 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
55
56 /* if the connector is already off, don't turn it back on */
57 if (connector->dpms != DRM_MODE_DPMS_ON)
58 return;
59
60 /* just deal with DP (not eDP) here. */
61 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
62 struct amdgpu_connector_atom_dig *dig_connector =
63 amdgpu_connector->con_priv;
64
65 /* if existing sink type was not DP no need to retrain */
66 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
67 return;
68
69 /* first get sink type as it may be reset after (un)plug */
70 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
71 /* don't do anything if sink is not display port, i.e.,
72 * passive dp->(dvi|hdmi) adaptor
73 */
74 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
75 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
76 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
77 /* Don't start link training before we have the DPCD */
78 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
79 return;
80
81 /* Turn the connector off and back on immediately, which
82 * will trigger link training
83 */
84 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
86 }
87 }
88 }
89
amdgpu_connector_property_change_mode(struct drm_encoder * encoder)90 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
91 {
92 struct drm_crtc *crtc = encoder->crtc;
93
94 if (crtc && crtc->enabled) {
95 drm_crtc_helper_set_mode(crtc, &crtc->mode,
96 crtc->x, crtc->y, crtc->primary->fb);
97 }
98 }
99
amdgpu_connector_get_monitor_bpc(struct drm_connector * connector)100 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
101 {
102 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
103 struct amdgpu_connector_atom_dig *dig_connector;
104 int bpc = 8;
105 unsigned mode_clock, max_tmds_clock;
106
107 switch (connector->connector_type) {
108 case DRM_MODE_CONNECTOR_DVII:
109 case DRM_MODE_CONNECTOR_HDMIB:
110 if (amdgpu_connector->use_digital) {
111 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
112 if (connector->display_info.bpc)
113 bpc = connector->display_info.bpc;
114 }
115 }
116 break;
117 case DRM_MODE_CONNECTOR_DVID:
118 case DRM_MODE_CONNECTOR_HDMIA:
119 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
120 if (connector->display_info.bpc)
121 bpc = connector->display_info.bpc;
122 }
123 break;
124 case DRM_MODE_CONNECTOR_DisplayPort:
125 dig_connector = amdgpu_connector->con_priv;
126 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
127 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
128 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
129 if (connector->display_info.bpc)
130 bpc = connector->display_info.bpc;
131 }
132 break;
133 case DRM_MODE_CONNECTOR_eDP:
134 case DRM_MODE_CONNECTOR_LVDS:
135 if (connector->display_info.bpc)
136 bpc = connector->display_info.bpc;
137 else {
138 const struct drm_connector_helper_funcs *connector_funcs =
139 connector->helper_private;
140 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
141 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
142 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
143
144 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
145 bpc = 6;
146 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
147 bpc = 8;
148 }
149 break;
150 }
151
152 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
153 /*
154 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
155 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
156 * 12 bpc is always supported on hdmi deep color sinks, as this is
157 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
158 */
159 if (bpc > 12) {
160 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
161 connector->name, bpc);
162 bpc = 12;
163 }
164
165 /* Any defined maximum tmds clock limit we must not exceed? */
166 if (connector->display_info.max_tmds_clock > 0) {
167 /* mode_clock is clock in kHz for mode to be modeset on this connector */
168 mode_clock = amdgpu_connector->pixelclock_for_modeset;
169
170 /* Maximum allowable input clock in kHz */
171 max_tmds_clock = connector->display_info.max_tmds_clock;
172
173 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
174 connector->name, mode_clock, max_tmds_clock);
175
176 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
177 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
178 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
179 (mode_clock * 5/4 <= max_tmds_clock))
180 bpc = 10;
181 else
182 bpc = 8;
183
184 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
185 connector->name, bpc);
186 }
187
188 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
189 bpc = 8;
190 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
191 connector->name, bpc);
192 }
193 } else if (bpc > 8) {
194 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
195 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
196 connector->name);
197 bpc = 8;
198 }
199 }
200
201 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
202 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
203 connector->name);
204 bpc = 8;
205 }
206
207 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
208 connector->name, connector->display_info.bpc, bpc);
209
210 return bpc;
211 }
212
213 static void
amdgpu_connector_update_scratch_regs(struct drm_connector * connector,enum drm_connector_status status)214 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
215 enum drm_connector_status status)
216 {
217 struct drm_encoder *best_encoder;
218 struct drm_encoder *encoder;
219 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
220 bool connected;
221
222 best_encoder = connector_funcs->best_encoder(connector);
223
224 drm_connector_for_each_possible_encoder(connector, encoder) {
225 if ((encoder == best_encoder) && (status == connector_status_connected))
226 connected = true;
227 else
228 connected = false;
229
230 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
231 }
232 }
233
234 static struct drm_encoder *
amdgpu_connector_find_encoder(struct drm_connector * connector,int encoder_type)235 amdgpu_connector_find_encoder(struct drm_connector *connector,
236 int encoder_type)
237 {
238 struct drm_encoder *encoder;
239
240 drm_connector_for_each_possible_encoder(connector, encoder) {
241 if (encoder->encoder_type == encoder_type)
242 return encoder;
243 }
244
245 return NULL;
246 }
247
amdgpu_connector_edid(struct drm_connector * connector)248 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
249 {
250 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
251 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
252
253 if (amdgpu_connector->edid) {
254 return amdgpu_connector->edid;
255 } else if (edid_blob) {
256 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
257 if (edid)
258 amdgpu_connector->edid = edid;
259 }
260 return amdgpu_connector->edid;
261 }
262
263 static struct edid *
amdgpu_connector_get_hardcoded_edid(struct amdgpu_device * adev)264 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
265 {
266 struct edid *edid;
267
268 if (adev->mode_info.bios_hardcoded_edid) {
269 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
270 if (edid) {
271 memcpy((unsigned char *)edid,
272 (unsigned char *)adev->mode_info.bios_hardcoded_edid,
273 adev->mode_info.bios_hardcoded_edid_size);
274 return edid;
275 }
276 }
277 return NULL;
278 }
279
amdgpu_connector_get_edid(struct drm_connector * connector)280 static void amdgpu_connector_get_edid(struct drm_connector *connector)
281 {
282 struct drm_device *dev = connector->dev;
283 struct amdgpu_device *adev = drm_to_adev(dev);
284 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
285
286 if (amdgpu_connector->edid)
287 return;
288
289 /* on hw with routers, select right port */
290 if (amdgpu_connector->router.ddc_valid)
291 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
292
293 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
294 ENCODER_OBJECT_ID_NONE) &&
295 amdgpu_connector->ddc_bus->has_aux) {
296 amdgpu_connector->edid = drm_get_edid(connector,
297 &amdgpu_connector->ddc_bus->aux.ddc);
298 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
299 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
300 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
301
302 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
303 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
304 amdgpu_connector->ddc_bus->has_aux)
305 amdgpu_connector->edid = drm_get_edid(connector,
306 &amdgpu_connector->ddc_bus->aux.ddc);
307 else if (amdgpu_connector->ddc_bus)
308 amdgpu_connector->edid = drm_get_edid(connector,
309 &amdgpu_connector->ddc_bus->adapter);
310 } else if (amdgpu_connector->ddc_bus) {
311 amdgpu_connector->edid = drm_get_edid(connector,
312 &amdgpu_connector->ddc_bus->adapter);
313 }
314
315 if (!amdgpu_connector->edid) {
316 /* some laptops provide a hardcoded edid in rom for LCDs */
317 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
318 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
319 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
320 }
321 }
322
amdgpu_connector_free_edid(struct drm_connector * connector)323 static void amdgpu_connector_free_edid(struct drm_connector *connector)
324 {
325 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
326
327 kfree(amdgpu_connector->edid);
328 amdgpu_connector->edid = NULL;
329 }
330
amdgpu_connector_ddc_get_modes(struct drm_connector * connector)331 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
332 {
333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
334 int ret;
335
336 if (amdgpu_connector->edid) {
337 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
338 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
339 return ret;
340 }
341 drm_connector_update_edid_property(connector, NULL);
342 return 0;
343 }
344
345 static struct drm_encoder *
amdgpu_connector_best_single_encoder(struct drm_connector * connector)346 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
347 {
348 struct drm_encoder *encoder;
349
350 /* pick the first one */
351 drm_connector_for_each_possible_encoder(connector, encoder)
352 return encoder;
353
354 return NULL;
355 }
356
amdgpu_get_native_mode(struct drm_connector * connector)357 static void amdgpu_get_native_mode(struct drm_connector *connector)
358 {
359 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
360 struct amdgpu_encoder *amdgpu_encoder;
361
362 if (encoder == NULL)
363 return;
364
365 amdgpu_encoder = to_amdgpu_encoder(encoder);
366
367 if (!list_empty(&connector->probed_modes)) {
368 struct drm_display_mode *preferred_mode =
369 list_first_entry(&connector->probed_modes,
370 struct drm_display_mode, head);
371
372 amdgpu_encoder->native_mode = *preferred_mode;
373 } else {
374 amdgpu_encoder->native_mode.clock = 0;
375 }
376 }
377
378 static struct drm_display_mode *
amdgpu_connector_lcd_native_mode(struct drm_encoder * encoder)379 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
380 {
381 struct drm_device *dev = encoder->dev;
382 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
383 struct drm_display_mode *mode = NULL;
384 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
385
386 if (native_mode->hdisplay != 0 &&
387 native_mode->vdisplay != 0 &&
388 native_mode->clock != 0) {
389 mode = drm_mode_duplicate(dev, native_mode);
390 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
391 drm_mode_set_name(mode);
392
393 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
394 } else if (native_mode->hdisplay != 0 &&
395 native_mode->vdisplay != 0) {
396 /* mac laptops without an edid */
397 /* Note that this is not necessarily the exact panel mode,
398 * but an approximation based on the cvt formula. For these
399 * systems we should ideally read the mode info out of the
400 * registers or add a mode table, but this works and is much
401 * simpler.
402 */
403 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
404 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
405 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
406 }
407 return mode;
408 }
409
amdgpu_connector_add_common_modes(struct drm_encoder * encoder,struct drm_connector * connector)410 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
411 struct drm_connector *connector)
412 {
413 struct drm_device *dev = encoder->dev;
414 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
415 struct drm_display_mode *mode = NULL;
416 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
417 int i;
418 static const struct mode_size {
419 int w;
420 int h;
421 } common_modes[17] = {
422 { 640, 480},
423 { 720, 480},
424 { 800, 600},
425 { 848, 480},
426 {1024, 768},
427 {1152, 768},
428 {1280, 720},
429 {1280, 800},
430 {1280, 854},
431 {1280, 960},
432 {1280, 1024},
433 {1440, 900},
434 {1400, 1050},
435 {1680, 1050},
436 {1600, 1200},
437 {1920, 1080},
438 {1920, 1200}
439 };
440
441 for (i = 0; i < 17; i++) {
442 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
443 if (common_modes[i].w > 1024 ||
444 common_modes[i].h > 768)
445 continue;
446 }
447 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
448 if (common_modes[i].w > native_mode->hdisplay ||
449 common_modes[i].h > native_mode->vdisplay ||
450 (common_modes[i].w == native_mode->hdisplay &&
451 common_modes[i].h == native_mode->vdisplay))
452 continue;
453 }
454 if (common_modes[i].w < 320 || common_modes[i].h < 200)
455 continue;
456
457 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
458 drm_mode_probed_add(connector, mode);
459 }
460 }
461
amdgpu_connector_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)462 static int amdgpu_connector_set_property(struct drm_connector *connector,
463 struct drm_property *property,
464 uint64_t val)
465 {
466 struct drm_device *dev = connector->dev;
467 struct amdgpu_device *adev = drm_to_adev(dev);
468 struct drm_encoder *encoder;
469 struct amdgpu_encoder *amdgpu_encoder;
470
471 if (property == adev->mode_info.coherent_mode_property) {
472 struct amdgpu_encoder_atom_dig *dig;
473 bool new_coherent_mode;
474
475 /* need to find digital encoder on connector */
476 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
477 if (!encoder)
478 return 0;
479
480 amdgpu_encoder = to_amdgpu_encoder(encoder);
481
482 if (!amdgpu_encoder->enc_priv)
483 return 0;
484
485 dig = amdgpu_encoder->enc_priv;
486 new_coherent_mode = val ? true : false;
487 if (dig->coherent_mode != new_coherent_mode) {
488 dig->coherent_mode = new_coherent_mode;
489 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
490 }
491 }
492
493 if (property == adev->mode_info.audio_property) {
494 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
495 /* need to find digital encoder on connector */
496 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
497 if (!encoder)
498 return 0;
499
500 amdgpu_encoder = to_amdgpu_encoder(encoder);
501
502 if (amdgpu_connector->audio != val) {
503 amdgpu_connector->audio = val;
504 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
505 }
506 }
507
508 if (property == adev->mode_info.dither_property) {
509 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
510 /* need to find digital encoder on connector */
511 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
512 if (!encoder)
513 return 0;
514
515 amdgpu_encoder = to_amdgpu_encoder(encoder);
516
517 if (amdgpu_connector->dither != val) {
518 amdgpu_connector->dither = val;
519 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
520 }
521 }
522
523 if (property == adev->mode_info.underscan_property) {
524 /* need to find digital encoder on connector */
525 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
526 if (!encoder)
527 return 0;
528
529 amdgpu_encoder = to_amdgpu_encoder(encoder);
530
531 if (amdgpu_encoder->underscan_type != val) {
532 amdgpu_encoder->underscan_type = val;
533 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
534 }
535 }
536
537 if (property == adev->mode_info.underscan_hborder_property) {
538 /* need to find digital encoder on connector */
539 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
540 if (!encoder)
541 return 0;
542
543 amdgpu_encoder = to_amdgpu_encoder(encoder);
544
545 if (amdgpu_encoder->underscan_hborder != val) {
546 amdgpu_encoder->underscan_hborder = val;
547 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
548 }
549 }
550
551 if (property == adev->mode_info.underscan_vborder_property) {
552 /* need to find digital encoder on connector */
553 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
554 if (!encoder)
555 return 0;
556
557 amdgpu_encoder = to_amdgpu_encoder(encoder);
558
559 if (amdgpu_encoder->underscan_vborder != val) {
560 amdgpu_encoder->underscan_vborder = val;
561 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
562 }
563 }
564
565 if (property == adev->mode_info.load_detect_property) {
566 struct amdgpu_connector *amdgpu_connector =
567 to_amdgpu_connector(connector);
568
569 if (val == 0)
570 amdgpu_connector->dac_load_detect = false;
571 else
572 amdgpu_connector->dac_load_detect = true;
573 }
574
575 if (property == dev->mode_config.scaling_mode_property) {
576 enum amdgpu_rmx_type rmx_type;
577
578 if (connector->encoder) {
579 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
580 } else {
581 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
582 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
583 }
584
585 switch (val) {
586 default:
587 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
588 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
589 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
590 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
591 }
592 if (amdgpu_encoder->rmx_type == rmx_type)
593 return 0;
594
595 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
596 (amdgpu_encoder->native_mode.clock == 0))
597 return 0;
598
599 amdgpu_encoder->rmx_type = rmx_type;
600
601 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
602 }
603
604 return 0;
605 }
606
607 static void
amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder * encoder,struct drm_connector * connector)608 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
609 struct drm_connector *connector)
610 {
611 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
612 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
613 struct drm_display_mode *t, *mode;
614
615 /* If the EDID preferred mode doesn't match the native mode, use it */
616 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
617 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
618 if (mode->hdisplay != native_mode->hdisplay ||
619 mode->vdisplay != native_mode->vdisplay)
620 memcpy(native_mode, mode, sizeof(*mode));
621 }
622 }
623
624 /* Try to get native mode details from EDID if necessary */
625 if (!native_mode->clock) {
626 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
627 if (mode->hdisplay == native_mode->hdisplay &&
628 mode->vdisplay == native_mode->vdisplay) {
629 *native_mode = *mode;
630 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
631 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
632 break;
633 }
634 }
635 }
636
637 if (!native_mode->clock) {
638 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
639 amdgpu_encoder->rmx_type = RMX_OFF;
640 }
641 }
642
amdgpu_connector_lvds_get_modes(struct drm_connector * connector)643 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
644 {
645 struct drm_encoder *encoder;
646 int ret = 0;
647 struct drm_display_mode *mode;
648
649 amdgpu_connector_get_edid(connector);
650 ret = amdgpu_connector_ddc_get_modes(connector);
651 if (ret > 0) {
652 encoder = amdgpu_connector_best_single_encoder(connector);
653 if (encoder) {
654 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
655 /* add scaled modes */
656 amdgpu_connector_add_common_modes(encoder, connector);
657 }
658 return ret;
659 }
660
661 encoder = amdgpu_connector_best_single_encoder(connector);
662 if (!encoder)
663 return 0;
664
665 /* we have no EDID modes */
666 mode = amdgpu_connector_lcd_native_mode(encoder);
667 if (mode) {
668 ret = 1;
669 drm_mode_probed_add(connector, mode);
670 /* add the width/height from vbios tables if available */
671 connector->display_info.width_mm = mode->width_mm;
672 connector->display_info.height_mm = mode->height_mm;
673 /* add scaled modes */
674 amdgpu_connector_add_common_modes(encoder, connector);
675 }
676
677 return ret;
678 }
679
amdgpu_connector_lvds_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)680 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
681 struct drm_display_mode *mode)
682 {
683 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
684
685 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
686 return MODE_PANEL;
687
688 if (encoder) {
689 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
690 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
691
692 /* AVIVO hardware supports downscaling modes larger than the panel
693 * to the panel size, but I'm not sure this is desirable.
694 */
695 if ((mode->hdisplay > native_mode->hdisplay) ||
696 (mode->vdisplay > native_mode->vdisplay))
697 return MODE_PANEL;
698
699 /* if scaling is disabled, block non-native modes */
700 if (amdgpu_encoder->rmx_type == RMX_OFF) {
701 if ((mode->hdisplay != native_mode->hdisplay) ||
702 (mode->vdisplay != native_mode->vdisplay))
703 return MODE_PANEL;
704 }
705 }
706
707 return MODE_OK;
708 }
709
710 static enum drm_connector_status
amdgpu_connector_lvds_detect(struct drm_connector * connector,bool force)711 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
712 {
713 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
714 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
715 enum drm_connector_status ret = connector_status_disconnected;
716 int r;
717
718 if (!drm_kms_helper_is_poll_worker()) {
719 r = pm_runtime_get_sync(connector->dev->dev);
720 if (r < 0) {
721 pm_runtime_put_autosuspend(connector->dev->dev);
722 return connector_status_disconnected;
723 }
724 }
725
726 if (encoder) {
727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
728 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
729
730 /* check if panel is valid */
731 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
732 ret = connector_status_connected;
733
734 }
735
736 /* check for edid as well */
737 amdgpu_connector_get_edid(connector);
738 if (amdgpu_connector->edid)
739 ret = connector_status_connected;
740 /* check acpi lid status ??? */
741
742 amdgpu_connector_update_scratch_regs(connector, ret);
743
744 if (!drm_kms_helper_is_poll_worker()) {
745 pm_runtime_mark_last_busy(connector->dev->dev);
746 pm_runtime_put_autosuspend(connector->dev->dev);
747 }
748
749 return ret;
750 }
751
amdgpu_connector_unregister(struct drm_connector * connector)752 static void amdgpu_connector_unregister(struct drm_connector *connector)
753 {
754 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
755
756 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
757 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
758 amdgpu_connector->ddc_bus->has_aux = false;
759 }
760 }
761
amdgpu_connector_destroy(struct drm_connector * connector)762 static void amdgpu_connector_destroy(struct drm_connector *connector)
763 {
764 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
765
766 amdgpu_connector_free_edid(connector);
767 kfree(amdgpu_connector->con_priv);
768 drm_connector_unregister(connector);
769 drm_connector_cleanup(connector);
770 kfree(connector);
771 }
772
amdgpu_connector_set_lcd_property(struct drm_connector * connector,struct drm_property * property,uint64_t value)773 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
774 struct drm_property *property,
775 uint64_t value)
776 {
777 struct drm_device *dev = connector->dev;
778 struct amdgpu_encoder *amdgpu_encoder;
779 enum amdgpu_rmx_type rmx_type;
780
781 DRM_DEBUG_KMS("\n");
782 if (property != dev->mode_config.scaling_mode_property)
783 return 0;
784
785 if (connector->encoder)
786 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
787 else {
788 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
789 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
790 }
791
792 switch (value) {
793 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
794 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
795 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
796 default:
797 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
798 }
799 if (amdgpu_encoder->rmx_type == rmx_type)
800 return 0;
801
802 amdgpu_encoder->rmx_type = rmx_type;
803
804 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
805 return 0;
806 }
807
808
809 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
810 .get_modes = amdgpu_connector_lvds_get_modes,
811 .mode_valid = amdgpu_connector_lvds_mode_valid,
812 .best_encoder = amdgpu_connector_best_single_encoder,
813 };
814
815 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
816 .dpms = drm_helper_connector_dpms,
817 .detect = amdgpu_connector_lvds_detect,
818 .fill_modes = drm_helper_probe_single_connector_modes,
819 .early_unregister = amdgpu_connector_unregister,
820 .destroy = amdgpu_connector_destroy,
821 .set_property = amdgpu_connector_set_lcd_property,
822 };
823
amdgpu_connector_vga_get_modes(struct drm_connector * connector)824 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
825 {
826 int ret;
827
828 amdgpu_connector_get_edid(connector);
829 ret = amdgpu_connector_ddc_get_modes(connector);
830
831 return ret;
832 }
833
amdgpu_connector_vga_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)834 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
835 struct drm_display_mode *mode)
836 {
837 struct drm_device *dev = connector->dev;
838 struct amdgpu_device *adev = drm_to_adev(dev);
839
840 /* XXX check mode bandwidth */
841
842 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
843 return MODE_CLOCK_HIGH;
844
845 return MODE_OK;
846 }
847
848 static enum drm_connector_status
amdgpu_connector_vga_detect(struct drm_connector * connector,bool force)849 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
850 {
851 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
852 struct drm_encoder *encoder;
853 const struct drm_encoder_helper_funcs *encoder_funcs;
854 bool dret = false;
855 enum drm_connector_status ret = connector_status_disconnected;
856 int r;
857
858 if (!drm_kms_helper_is_poll_worker()) {
859 r = pm_runtime_get_sync(connector->dev->dev);
860 if (r < 0) {
861 pm_runtime_put_autosuspend(connector->dev->dev);
862 return connector_status_disconnected;
863 }
864 }
865
866 encoder = amdgpu_connector_best_single_encoder(connector);
867 if (!encoder)
868 ret = connector_status_disconnected;
869
870 if (amdgpu_connector->ddc_bus)
871 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
872 if (dret) {
873 amdgpu_connector->detected_by_load = false;
874 amdgpu_connector_free_edid(connector);
875 amdgpu_connector_get_edid(connector);
876
877 if (!amdgpu_connector->edid) {
878 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
879 connector->name);
880 ret = connector_status_connected;
881 } else {
882 amdgpu_connector->use_digital =
883 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
884
885 /* some oems have boards with separate digital and analog connectors
886 * with a shared ddc line (often vga + hdmi)
887 */
888 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
889 amdgpu_connector_free_edid(connector);
890 ret = connector_status_disconnected;
891 } else {
892 ret = connector_status_connected;
893 }
894 }
895 } else {
896
897 /* if we aren't forcing don't do destructive polling */
898 if (!force) {
899 /* only return the previous status if we last
900 * detected a monitor via load.
901 */
902 if (amdgpu_connector->detected_by_load)
903 ret = connector->status;
904 goto out;
905 }
906
907 if (amdgpu_connector->dac_load_detect && encoder) {
908 encoder_funcs = encoder->helper_private;
909 ret = encoder_funcs->detect(encoder, connector);
910 if (ret != connector_status_disconnected)
911 amdgpu_connector->detected_by_load = true;
912 }
913 }
914
915 amdgpu_connector_update_scratch_regs(connector, ret);
916
917 out:
918 if (!drm_kms_helper_is_poll_worker()) {
919 pm_runtime_mark_last_busy(connector->dev->dev);
920 pm_runtime_put_autosuspend(connector->dev->dev);
921 }
922
923 return ret;
924 }
925
926 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
927 .get_modes = amdgpu_connector_vga_get_modes,
928 .mode_valid = amdgpu_connector_vga_mode_valid,
929 .best_encoder = amdgpu_connector_best_single_encoder,
930 };
931
932 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
933 .dpms = drm_helper_connector_dpms,
934 .detect = amdgpu_connector_vga_detect,
935 .fill_modes = drm_helper_probe_single_connector_modes,
936 .early_unregister = amdgpu_connector_unregister,
937 .destroy = amdgpu_connector_destroy,
938 .set_property = amdgpu_connector_set_property,
939 };
940
941 static bool
amdgpu_connector_check_hpd_status_unchanged(struct drm_connector * connector)942 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
943 {
944 struct drm_device *dev = connector->dev;
945 struct amdgpu_device *adev = drm_to_adev(dev);
946 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
947 enum drm_connector_status status;
948
949 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
950 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
951 status = connector_status_connected;
952 else
953 status = connector_status_disconnected;
954 if (connector->status == status)
955 return true;
956 }
957
958 return false;
959 }
960
961 /*
962 * DVI is complicated
963 * Do a DDC probe, if DDC probe passes, get the full EDID so
964 * we can do analog/digital monitor detection at this point.
965 * If the monitor is an analog monitor or we got no DDC,
966 * we need to find the DAC encoder object for this connector.
967 * If we got no DDC, we do load detection on the DAC encoder object.
968 * If we got analog DDC or load detection passes on the DAC encoder
969 * we have to check if this analog encoder is shared with anyone else (TV)
970 * if its shared we have to set the other connector to disconnected.
971 */
972 static enum drm_connector_status
amdgpu_connector_dvi_detect(struct drm_connector * connector,bool force)973 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
974 {
975 struct drm_device *dev = connector->dev;
976 struct amdgpu_device *adev = drm_to_adev(dev);
977 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
978 const struct drm_encoder_helper_funcs *encoder_funcs;
979 int r;
980 enum drm_connector_status ret = connector_status_disconnected;
981 bool dret = false, broken_edid = false;
982
983 if (!drm_kms_helper_is_poll_worker()) {
984 r = pm_runtime_get_sync(connector->dev->dev);
985 if (r < 0) {
986 pm_runtime_put_autosuspend(connector->dev->dev);
987 return connector_status_disconnected;
988 }
989 }
990
991 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
992 ret = connector->status;
993 goto exit;
994 }
995
996 if (amdgpu_connector->ddc_bus)
997 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
998 if (dret) {
999 amdgpu_connector->detected_by_load = false;
1000 amdgpu_connector_free_edid(connector);
1001 amdgpu_connector_get_edid(connector);
1002
1003 if (!amdgpu_connector->edid) {
1004 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1005 connector->name);
1006 ret = connector_status_connected;
1007 broken_edid = true; /* defer use_digital to later */
1008 } else {
1009 amdgpu_connector->use_digital =
1010 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1011
1012 /* some oems have boards with separate digital and analog connectors
1013 * with a shared ddc line (often vga + hdmi)
1014 */
1015 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1016 amdgpu_connector_free_edid(connector);
1017 ret = connector_status_disconnected;
1018 } else {
1019 ret = connector_status_connected;
1020 }
1021
1022 /* This gets complicated. We have boards with VGA + HDMI with a
1023 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1024 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1025 * you don't really know what's connected to which port as both are digital.
1026 */
1027 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1028 struct drm_connector *list_connector;
1029 struct drm_connector_list_iter iter;
1030 struct amdgpu_connector *list_amdgpu_connector;
1031
1032 drm_connector_list_iter_begin(dev, &iter);
1033 drm_for_each_connector_iter(list_connector,
1034 &iter) {
1035 if (connector == list_connector)
1036 continue;
1037 list_amdgpu_connector = to_amdgpu_connector(list_connector);
1038 if (list_amdgpu_connector->shared_ddc &&
1039 (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1040 amdgpu_connector->ddc_bus->rec.i2c_id)) {
1041 /* cases where both connectors are digital */
1042 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1043 /* hpd is our only option in this case */
1044 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1045 amdgpu_connector_free_edid(connector);
1046 ret = connector_status_disconnected;
1047 }
1048 }
1049 }
1050 }
1051 drm_connector_list_iter_end(&iter);
1052 }
1053 }
1054 }
1055
1056 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1057 goto out;
1058
1059 /* DVI-D and HDMI-A are digital only */
1060 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1061 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1062 goto out;
1063
1064 /* if we aren't forcing don't do destructive polling */
1065 if (!force) {
1066 /* only return the previous status if we last
1067 * detected a monitor via load.
1068 */
1069 if (amdgpu_connector->detected_by_load)
1070 ret = connector->status;
1071 goto out;
1072 }
1073
1074 /* find analog encoder */
1075 if (amdgpu_connector->dac_load_detect) {
1076 struct drm_encoder *encoder;
1077
1078 drm_connector_for_each_possible_encoder(connector, encoder) {
1079 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1080 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1081 continue;
1082
1083 encoder_funcs = encoder->helper_private;
1084 if (encoder_funcs->detect) {
1085 if (!broken_edid) {
1086 if (ret != connector_status_connected) {
1087 /* deal with analog monitors without DDC */
1088 ret = encoder_funcs->detect(encoder, connector);
1089 if (ret == connector_status_connected) {
1090 amdgpu_connector->use_digital = false;
1091 }
1092 if (ret != connector_status_disconnected)
1093 amdgpu_connector->detected_by_load = true;
1094 }
1095 } else {
1096 enum drm_connector_status lret;
1097 /* assume digital unless load detected otherwise */
1098 amdgpu_connector->use_digital = true;
1099 lret = encoder_funcs->detect(encoder, connector);
1100 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1101 if (lret == connector_status_connected)
1102 amdgpu_connector->use_digital = false;
1103 }
1104 break;
1105 }
1106 }
1107 }
1108
1109 out:
1110 /* updated in get modes as well since we need to know if it's analog or digital */
1111 amdgpu_connector_update_scratch_regs(connector, ret);
1112
1113 exit:
1114 if (!drm_kms_helper_is_poll_worker()) {
1115 pm_runtime_mark_last_busy(connector->dev->dev);
1116 pm_runtime_put_autosuspend(connector->dev->dev);
1117 }
1118
1119 return ret;
1120 }
1121
1122 /* okay need to be smart in here about which encoder to pick */
1123 static struct drm_encoder *
amdgpu_connector_dvi_encoder(struct drm_connector * connector)1124 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1125 {
1126 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1127 struct drm_encoder *encoder;
1128
1129 drm_connector_for_each_possible_encoder(connector, encoder) {
1130 if (amdgpu_connector->use_digital == true) {
1131 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1132 return encoder;
1133 } else {
1134 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1135 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1136 return encoder;
1137 }
1138 }
1139
1140 /* see if we have a default encoder TODO */
1141
1142 /* then check use digitial */
1143 /* pick the first one */
1144 drm_connector_for_each_possible_encoder(connector, encoder)
1145 return encoder;
1146
1147 return NULL;
1148 }
1149
amdgpu_connector_dvi_force(struct drm_connector * connector)1150 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1151 {
1152 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1153 if (connector->force == DRM_FORCE_ON)
1154 amdgpu_connector->use_digital = false;
1155 if (connector->force == DRM_FORCE_ON_DIGITAL)
1156 amdgpu_connector->use_digital = true;
1157 }
1158
amdgpu_connector_dvi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1159 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1160 struct drm_display_mode *mode)
1161 {
1162 struct drm_device *dev = connector->dev;
1163 struct amdgpu_device *adev = drm_to_adev(dev);
1164 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1165
1166 /* XXX check mode bandwidth */
1167
1168 if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1169 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1170 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1171 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1172 return MODE_OK;
1173 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1174 /* HDMI 1.3+ supports max clock of 340 Mhz */
1175 if (mode->clock > 340000)
1176 return MODE_CLOCK_HIGH;
1177 else
1178 return MODE_OK;
1179 } else {
1180 return MODE_CLOCK_HIGH;
1181 }
1182 }
1183
1184 /* check against the max pixel clock */
1185 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1186 return MODE_CLOCK_HIGH;
1187
1188 return MODE_OK;
1189 }
1190
1191 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1192 .get_modes = amdgpu_connector_vga_get_modes,
1193 .mode_valid = amdgpu_connector_dvi_mode_valid,
1194 .best_encoder = amdgpu_connector_dvi_encoder,
1195 };
1196
1197 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1198 .dpms = drm_helper_connector_dpms,
1199 .detect = amdgpu_connector_dvi_detect,
1200 .fill_modes = drm_helper_probe_single_connector_modes,
1201 .set_property = amdgpu_connector_set_property,
1202 .early_unregister = amdgpu_connector_unregister,
1203 .destroy = amdgpu_connector_destroy,
1204 .force = amdgpu_connector_dvi_force,
1205 };
1206
amdgpu_connector_dp_get_modes(struct drm_connector * connector)1207 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1208 {
1209 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1210 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1211 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1212 int ret;
1213
1214 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1215 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1216 struct drm_display_mode *mode;
1217
1218 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1219 if (!amdgpu_dig_connector->edp_on)
1220 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1221 ATOM_TRANSMITTER_ACTION_POWER_ON);
1222 amdgpu_connector_get_edid(connector);
1223 ret = amdgpu_connector_ddc_get_modes(connector);
1224 if (!amdgpu_dig_connector->edp_on)
1225 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1226 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1227 } else {
1228 /* need to setup ddc on the bridge */
1229 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1230 ENCODER_OBJECT_ID_NONE) {
1231 if (encoder)
1232 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1233 }
1234 amdgpu_connector_get_edid(connector);
1235 ret = amdgpu_connector_ddc_get_modes(connector);
1236 }
1237
1238 if (ret > 0) {
1239 if (encoder) {
1240 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1241 /* add scaled modes */
1242 amdgpu_connector_add_common_modes(encoder, connector);
1243 }
1244 return ret;
1245 }
1246
1247 if (!encoder)
1248 return 0;
1249
1250 /* we have no EDID modes */
1251 mode = amdgpu_connector_lcd_native_mode(encoder);
1252 if (mode) {
1253 ret = 1;
1254 drm_mode_probed_add(connector, mode);
1255 /* add the width/height from vbios tables if available */
1256 connector->display_info.width_mm = mode->width_mm;
1257 connector->display_info.height_mm = mode->height_mm;
1258 /* add scaled modes */
1259 amdgpu_connector_add_common_modes(encoder, connector);
1260 }
1261 } else {
1262 /* need to setup ddc on the bridge */
1263 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1264 ENCODER_OBJECT_ID_NONE) {
1265 if (encoder)
1266 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1267 }
1268 amdgpu_connector_get_edid(connector);
1269 ret = amdgpu_connector_ddc_get_modes(connector);
1270
1271 amdgpu_get_native_mode(connector);
1272 }
1273
1274 return ret;
1275 }
1276
amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector * connector)1277 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1278 {
1279 struct drm_encoder *encoder;
1280 struct amdgpu_encoder *amdgpu_encoder;
1281
1282 drm_connector_for_each_possible_encoder(connector, encoder) {
1283 amdgpu_encoder = to_amdgpu_encoder(encoder);
1284
1285 switch (amdgpu_encoder->encoder_id) {
1286 case ENCODER_OBJECT_ID_TRAVIS:
1287 case ENCODER_OBJECT_ID_NUTMEG:
1288 return amdgpu_encoder->encoder_id;
1289 default:
1290 break;
1291 }
1292 }
1293
1294 return ENCODER_OBJECT_ID_NONE;
1295 }
1296
amdgpu_connector_encoder_is_hbr2(struct drm_connector * connector)1297 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1298 {
1299 struct drm_encoder *encoder;
1300 struct amdgpu_encoder *amdgpu_encoder;
1301 bool found = false;
1302
1303 drm_connector_for_each_possible_encoder(connector, encoder) {
1304 amdgpu_encoder = to_amdgpu_encoder(encoder);
1305 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1306 found = true;
1307 }
1308
1309 return found;
1310 }
1311
amdgpu_connector_is_dp12_capable(struct drm_connector * connector)1312 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1313 {
1314 struct drm_device *dev = connector->dev;
1315 struct amdgpu_device *adev = drm_to_adev(dev);
1316
1317 if ((adev->clock.default_dispclk >= 53900) &&
1318 amdgpu_connector_encoder_is_hbr2(connector)) {
1319 return true;
1320 }
1321
1322 return false;
1323 }
1324
1325 static enum drm_connector_status
amdgpu_connector_dp_detect(struct drm_connector * connector,bool force)1326 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1327 {
1328 struct drm_device *dev = connector->dev;
1329 struct amdgpu_device *adev = drm_to_adev(dev);
1330 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1331 enum drm_connector_status ret = connector_status_disconnected;
1332 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1333 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1334 int r;
1335
1336 if (!drm_kms_helper_is_poll_worker()) {
1337 r = pm_runtime_get_sync(connector->dev->dev);
1338 if (r < 0) {
1339 pm_runtime_put_autosuspend(connector->dev->dev);
1340 return connector_status_disconnected;
1341 }
1342 }
1343
1344 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1345 ret = connector->status;
1346 goto out;
1347 }
1348
1349 amdgpu_connector_free_edid(connector);
1350
1351 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1352 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1353 if (encoder) {
1354 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1355 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1356
1357 /* check if panel is valid */
1358 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1359 ret = connector_status_connected;
1360 }
1361 /* eDP is always DP */
1362 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1363 if (!amdgpu_dig_connector->edp_on)
1364 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1365 ATOM_TRANSMITTER_ACTION_POWER_ON);
1366 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1367 ret = connector_status_connected;
1368 if (!amdgpu_dig_connector->edp_on)
1369 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1370 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1371 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1372 ENCODER_OBJECT_ID_NONE) {
1373 /* DP bridges are always DP */
1374 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1375 /* get the DPCD from the bridge */
1376 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1377
1378 if (encoder) {
1379 /* setup ddc on the bridge */
1380 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1381 /* bridge chips are always aux */
1382 /* try DDC */
1383 if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1384 ret = connector_status_connected;
1385 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1386 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1387 ret = encoder_funcs->detect(encoder, connector);
1388 }
1389 }
1390 } else {
1391 amdgpu_dig_connector->dp_sink_type =
1392 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1393 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1394 ret = connector_status_connected;
1395 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1396 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1397 } else {
1398 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1399 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1400 ret = connector_status_connected;
1401 } else {
1402 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1403 if (amdgpu_display_ddc_probe(amdgpu_connector,
1404 false))
1405 ret = connector_status_connected;
1406 }
1407 }
1408 }
1409
1410 amdgpu_connector_update_scratch_regs(connector, ret);
1411 out:
1412 if (!drm_kms_helper_is_poll_worker()) {
1413 pm_runtime_mark_last_busy(connector->dev->dev);
1414 pm_runtime_put_autosuspend(connector->dev->dev);
1415 }
1416
1417 drm_dp_set_subconnector_property(&amdgpu_connector->base,
1418 ret,
1419 amdgpu_dig_connector->dpcd,
1420 amdgpu_dig_connector->downstream_ports);
1421 return ret;
1422 }
1423
amdgpu_connector_dp_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1424 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1425 struct drm_display_mode *mode)
1426 {
1427 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1428 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1429
1430 /* XXX check mode bandwidth */
1431
1432 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1433 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1434 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1435
1436 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1437 return MODE_PANEL;
1438
1439 if (encoder) {
1440 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1441 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1442
1443 /* AVIVO hardware supports downscaling modes larger than the panel
1444 * to the panel size, but I'm not sure this is desirable.
1445 */
1446 if ((mode->hdisplay > native_mode->hdisplay) ||
1447 (mode->vdisplay > native_mode->vdisplay))
1448 return MODE_PANEL;
1449
1450 /* if scaling is disabled, block non-native modes */
1451 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1452 if ((mode->hdisplay != native_mode->hdisplay) ||
1453 (mode->vdisplay != native_mode->vdisplay))
1454 return MODE_PANEL;
1455 }
1456 }
1457 return MODE_OK;
1458 } else {
1459 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1460 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1461 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1462 } else {
1463 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1464 /* HDMI 1.3+ supports max clock of 340 Mhz */
1465 if (mode->clock > 340000)
1466 return MODE_CLOCK_HIGH;
1467 } else {
1468 if (mode->clock > 165000)
1469 return MODE_CLOCK_HIGH;
1470 }
1471 }
1472 }
1473
1474 return MODE_OK;
1475 }
1476
1477 static int
amdgpu_connector_late_register(struct drm_connector * connector)1478 amdgpu_connector_late_register(struct drm_connector *connector)
1479 {
1480 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1481 int r = 0;
1482
1483 if (amdgpu_connector->ddc_bus->has_aux) {
1484 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1485 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1486 }
1487
1488 return r;
1489 }
1490
1491 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1492 .get_modes = amdgpu_connector_dp_get_modes,
1493 .mode_valid = amdgpu_connector_dp_mode_valid,
1494 .best_encoder = amdgpu_connector_dvi_encoder,
1495 };
1496
1497 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1498 .dpms = drm_helper_connector_dpms,
1499 .detect = amdgpu_connector_dp_detect,
1500 .fill_modes = drm_helper_probe_single_connector_modes,
1501 .set_property = amdgpu_connector_set_property,
1502 .early_unregister = amdgpu_connector_unregister,
1503 .destroy = amdgpu_connector_destroy,
1504 .force = amdgpu_connector_dvi_force,
1505 .late_register = amdgpu_connector_late_register,
1506 };
1507
1508 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1509 .dpms = drm_helper_connector_dpms,
1510 .detect = amdgpu_connector_dp_detect,
1511 .fill_modes = drm_helper_probe_single_connector_modes,
1512 .set_property = amdgpu_connector_set_lcd_property,
1513 .early_unregister = amdgpu_connector_unregister,
1514 .destroy = amdgpu_connector_destroy,
1515 .force = amdgpu_connector_dvi_force,
1516 .late_register = amdgpu_connector_late_register,
1517 };
1518
1519 void
amdgpu_connector_add(struct amdgpu_device * adev,uint32_t connector_id,uint32_t supported_device,int connector_type,struct amdgpu_i2c_bus_rec * i2c_bus,uint16_t connector_object_id,struct amdgpu_hpd * hpd,struct amdgpu_router * router)1520 amdgpu_connector_add(struct amdgpu_device *adev,
1521 uint32_t connector_id,
1522 uint32_t supported_device,
1523 int connector_type,
1524 struct amdgpu_i2c_bus_rec *i2c_bus,
1525 uint16_t connector_object_id,
1526 struct amdgpu_hpd *hpd,
1527 struct amdgpu_router *router)
1528 {
1529 struct drm_device *dev = adev_to_drm(adev);
1530 struct drm_connector *connector;
1531 struct drm_connector_list_iter iter;
1532 struct amdgpu_connector *amdgpu_connector;
1533 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1534 struct drm_encoder *encoder;
1535 struct amdgpu_encoder *amdgpu_encoder;
1536 struct i2c_adapter *ddc = NULL;
1537 uint32_t subpixel_order = SubPixelNone;
1538 bool shared_ddc = false;
1539 bool is_dp_bridge = false;
1540 bool has_aux = false;
1541
1542 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1543 return;
1544
1545 /* see if we already added it */
1546 drm_connector_list_iter_begin(dev, &iter);
1547 drm_for_each_connector_iter(connector, &iter) {
1548 amdgpu_connector = to_amdgpu_connector(connector);
1549 if (amdgpu_connector->connector_id == connector_id) {
1550 amdgpu_connector->devices |= supported_device;
1551 drm_connector_list_iter_end(&iter);
1552 return;
1553 }
1554 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1555 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1556 amdgpu_connector->shared_ddc = true;
1557 shared_ddc = true;
1558 }
1559 if (amdgpu_connector->router_bus && router->ddc_valid &&
1560 (amdgpu_connector->router.router_id == router->router_id)) {
1561 amdgpu_connector->shared_ddc = false;
1562 shared_ddc = false;
1563 }
1564 }
1565 }
1566 drm_connector_list_iter_end(&iter);
1567
1568 /* check if it's a dp bridge */
1569 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1570 amdgpu_encoder = to_amdgpu_encoder(encoder);
1571 if (amdgpu_encoder->devices & supported_device) {
1572 switch (amdgpu_encoder->encoder_id) {
1573 case ENCODER_OBJECT_ID_TRAVIS:
1574 case ENCODER_OBJECT_ID_NUTMEG:
1575 is_dp_bridge = true;
1576 break;
1577 default:
1578 break;
1579 }
1580 }
1581 }
1582
1583 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1584 if (!amdgpu_connector)
1585 return;
1586
1587 connector = &amdgpu_connector->base;
1588
1589 amdgpu_connector->connector_id = connector_id;
1590 amdgpu_connector->devices = supported_device;
1591 amdgpu_connector->shared_ddc = shared_ddc;
1592 amdgpu_connector->connector_object_id = connector_object_id;
1593 amdgpu_connector->hpd = *hpd;
1594
1595 amdgpu_connector->router = *router;
1596 if (router->ddc_valid || router->cd_valid) {
1597 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1598 if (!amdgpu_connector->router_bus)
1599 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1600 }
1601
1602 if (is_dp_bridge) {
1603 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1604 if (!amdgpu_dig_connector)
1605 goto failed;
1606 amdgpu_connector->con_priv = amdgpu_dig_connector;
1607 if (i2c_bus->valid) {
1608 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1609 if (amdgpu_connector->ddc_bus) {
1610 has_aux = true;
1611 ddc = &amdgpu_connector->ddc_bus->adapter;
1612 } else {
1613 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1614 }
1615 }
1616 switch (connector_type) {
1617 case DRM_MODE_CONNECTOR_VGA:
1618 case DRM_MODE_CONNECTOR_DVIA:
1619 default:
1620 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1621 &amdgpu_connector_dp_funcs,
1622 connector_type,
1623 ddc);
1624 drm_connector_helper_add(&amdgpu_connector->base,
1625 &amdgpu_connector_dp_helper_funcs);
1626 connector->interlace_allowed = true;
1627 connector->doublescan_allowed = true;
1628 amdgpu_connector->dac_load_detect = true;
1629 drm_object_attach_property(&amdgpu_connector->base.base,
1630 adev->mode_info.load_detect_property,
1631 1);
1632 drm_object_attach_property(&amdgpu_connector->base.base,
1633 dev->mode_config.scaling_mode_property,
1634 DRM_MODE_SCALE_NONE);
1635 break;
1636 case DRM_MODE_CONNECTOR_DVII:
1637 case DRM_MODE_CONNECTOR_DVID:
1638 case DRM_MODE_CONNECTOR_HDMIA:
1639 case DRM_MODE_CONNECTOR_HDMIB:
1640 case DRM_MODE_CONNECTOR_DisplayPort:
1641 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1642 &amdgpu_connector_dp_funcs,
1643 connector_type,
1644 ddc);
1645 drm_connector_helper_add(&amdgpu_connector->base,
1646 &amdgpu_connector_dp_helper_funcs);
1647 drm_object_attach_property(&amdgpu_connector->base.base,
1648 adev->mode_info.underscan_property,
1649 UNDERSCAN_OFF);
1650 drm_object_attach_property(&amdgpu_connector->base.base,
1651 adev->mode_info.underscan_hborder_property,
1652 0);
1653 drm_object_attach_property(&amdgpu_connector->base.base,
1654 adev->mode_info.underscan_vborder_property,
1655 0);
1656
1657 drm_object_attach_property(&amdgpu_connector->base.base,
1658 dev->mode_config.scaling_mode_property,
1659 DRM_MODE_SCALE_NONE);
1660
1661 drm_object_attach_property(&amdgpu_connector->base.base,
1662 adev->mode_info.dither_property,
1663 AMDGPU_FMT_DITHER_DISABLE);
1664
1665 if (amdgpu_audio != 0)
1666 drm_object_attach_property(&amdgpu_connector->base.base,
1667 adev->mode_info.audio_property,
1668 AMDGPU_AUDIO_AUTO);
1669
1670 subpixel_order = SubPixelHorizontalRGB;
1671 connector->interlace_allowed = true;
1672 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1673 connector->doublescan_allowed = true;
1674 else
1675 connector->doublescan_allowed = false;
1676 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1677 amdgpu_connector->dac_load_detect = true;
1678 drm_object_attach_property(&amdgpu_connector->base.base,
1679 adev->mode_info.load_detect_property,
1680 1);
1681 }
1682 break;
1683 case DRM_MODE_CONNECTOR_LVDS:
1684 case DRM_MODE_CONNECTOR_eDP:
1685 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1686 &amdgpu_connector_edp_funcs,
1687 connector_type,
1688 ddc);
1689 drm_connector_helper_add(&amdgpu_connector->base,
1690 &amdgpu_connector_dp_helper_funcs);
1691 drm_object_attach_property(&amdgpu_connector->base.base,
1692 dev->mode_config.scaling_mode_property,
1693 DRM_MODE_SCALE_FULLSCREEN);
1694 subpixel_order = SubPixelHorizontalRGB;
1695 connector->interlace_allowed = false;
1696 connector->doublescan_allowed = false;
1697 break;
1698 }
1699 } else {
1700 switch (connector_type) {
1701 case DRM_MODE_CONNECTOR_VGA:
1702 if (i2c_bus->valid) {
1703 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1704 if (!amdgpu_connector->ddc_bus)
1705 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1706 else
1707 ddc = &amdgpu_connector->ddc_bus->adapter;
1708 }
1709 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1710 &amdgpu_connector_vga_funcs,
1711 connector_type,
1712 ddc);
1713 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1714 amdgpu_connector->dac_load_detect = true;
1715 drm_object_attach_property(&amdgpu_connector->base.base,
1716 adev->mode_info.load_detect_property,
1717 1);
1718 drm_object_attach_property(&amdgpu_connector->base.base,
1719 dev->mode_config.scaling_mode_property,
1720 DRM_MODE_SCALE_NONE);
1721 /* no HPD on analog connectors */
1722 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1723 connector->interlace_allowed = true;
1724 connector->doublescan_allowed = true;
1725 break;
1726 case DRM_MODE_CONNECTOR_DVIA:
1727 if (i2c_bus->valid) {
1728 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1729 if (!amdgpu_connector->ddc_bus)
1730 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1731 else
1732 ddc = &amdgpu_connector->ddc_bus->adapter;
1733 }
1734 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1735 &amdgpu_connector_vga_funcs,
1736 connector_type,
1737 ddc);
1738 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1739 amdgpu_connector->dac_load_detect = true;
1740 drm_object_attach_property(&amdgpu_connector->base.base,
1741 adev->mode_info.load_detect_property,
1742 1);
1743 drm_object_attach_property(&amdgpu_connector->base.base,
1744 dev->mode_config.scaling_mode_property,
1745 DRM_MODE_SCALE_NONE);
1746 /* no HPD on analog connectors */
1747 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1748 connector->interlace_allowed = true;
1749 connector->doublescan_allowed = true;
1750 break;
1751 case DRM_MODE_CONNECTOR_DVII:
1752 case DRM_MODE_CONNECTOR_DVID:
1753 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1754 if (!amdgpu_dig_connector)
1755 goto failed;
1756 amdgpu_connector->con_priv = amdgpu_dig_connector;
1757 if (i2c_bus->valid) {
1758 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1759 if (!amdgpu_connector->ddc_bus)
1760 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1761 else
1762 ddc = &amdgpu_connector->ddc_bus->adapter;
1763 }
1764 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1765 &amdgpu_connector_dvi_funcs,
1766 connector_type,
1767 ddc);
1768 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1769 subpixel_order = SubPixelHorizontalRGB;
1770 drm_object_attach_property(&amdgpu_connector->base.base,
1771 adev->mode_info.coherent_mode_property,
1772 1);
1773 drm_object_attach_property(&amdgpu_connector->base.base,
1774 adev->mode_info.underscan_property,
1775 UNDERSCAN_OFF);
1776 drm_object_attach_property(&amdgpu_connector->base.base,
1777 adev->mode_info.underscan_hborder_property,
1778 0);
1779 drm_object_attach_property(&amdgpu_connector->base.base,
1780 adev->mode_info.underscan_vborder_property,
1781 0);
1782 drm_object_attach_property(&amdgpu_connector->base.base,
1783 dev->mode_config.scaling_mode_property,
1784 DRM_MODE_SCALE_NONE);
1785
1786 if (amdgpu_audio != 0) {
1787 drm_object_attach_property(&amdgpu_connector->base.base,
1788 adev->mode_info.audio_property,
1789 AMDGPU_AUDIO_AUTO);
1790 }
1791 drm_object_attach_property(&amdgpu_connector->base.base,
1792 adev->mode_info.dither_property,
1793 AMDGPU_FMT_DITHER_DISABLE);
1794 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1795 amdgpu_connector->dac_load_detect = true;
1796 drm_object_attach_property(&amdgpu_connector->base.base,
1797 adev->mode_info.load_detect_property,
1798 1);
1799 }
1800 connector->interlace_allowed = true;
1801 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1802 connector->doublescan_allowed = true;
1803 else
1804 connector->doublescan_allowed = false;
1805 break;
1806 case DRM_MODE_CONNECTOR_HDMIA:
1807 case DRM_MODE_CONNECTOR_HDMIB:
1808 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1809 if (!amdgpu_dig_connector)
1810 goto failed;
1811 amdgpu_connector->con_priv = amdgpu_dig_connector;
1812 if (i2c_bus->valid) {
1813 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1814 if (!amdgpu_connector->ddc_bus)
1815 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1816 else
1817 ddc = &amdgpu_connector->ddc_bus->adapter;
1818 }
1819 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1820 &amdgpu_connector_dvi_funcs,
1821 connector_type,
1822 ddc);
1823 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1824 drm_object_attach_property(&amdgpu_connector->base.base,
1825 adev->mode_info.coherent_mode_property,
1826 1);
1827 drm_object_attach_property(&amdgpu_connector->base.base,
1828 adev->mode_info.underscan_property,
1829 UNDERSCAN_OFF);
1830 drm_object_attach_property(&amdgpu_connector->base.base,
1831 adev->mode_info.underscan_hborder_property,
1832 0);
1833 drm_object_attach_property(&amdgpu_connector->base.base,
1834 adev->mode_info.underscan_vborder_property,
1835 0);
1836 drm_object_attach_property(&amdgpu_connector->base.base,
1837 dev->mode_config.scaling_mode_property,
1838 DRM_MODE_SCALE_NONE);
1839 if (amdgpu_audio != 0) {
1840 drm_object_attach_property(&amdgpu_connector->base.base,
1841 adev->mode_info.audio_property,
1842 AMDGPU_AUDIO_AUTO);
1843 }
1844 drm_object_attach_property(&amdgpu_connector->base.base,
1845 adev->mode_info.dither_property,
1846 AMDGPU_FMT_DITHER_DISABLE);
1847 subpixel_order = SubPixelHorizontalRGB;
1848 connector->interlace_allowed = true;
1849 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1850 connector->doublescan_allowed = true;
1851 else
1852 connector->doublescan_allowed = false;
1853 break;
1854 case DRM_MODE_CONNECTOR_DisplayPort:
1855 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1856 if (!amdgpu_dig_connector)
1857 goto failed;
1858 amdgpu_connector->con_priv = amdgpu_dig_connector;
1859 if (i2c_bus->valid) {
1860 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1861 if (amdgpu_connector->ddc_bus) {
1862 has_aux = true;
1863 ddc = &amdgpu_connector->ddc_bus->adapter;
1864 } else {
1865 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1866 }
1867 }
1868 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1869 &amdgpu_connector_dp_funcs,
1870 connector_type,
1871 ddc);
1872 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1873 subpixel_order = SubPixelHorizontalRGB;
1874 drm_object_attach_property(&amdgpu_connector->base.base,
1875 adev->mode_info.coherent_mode_property,
1876 1);
1877 drm_object_attach_property(&amdgpu_connector->base.base,
1878 adev->mode_info.underscan_property,
1879 UNDERSCAN_OFF);
1880 drm_object_attach_property(&amdgpu_connector->base.base,
1881 adev->mode_info.underscan_hborder_property,
1882 0);
1883 drm_object_attach_property(&amdgpu_connector->base.base,
1884 adev->mode_info.underscan_vborder_property,
1885 0);
1886 drm_object_attach_property(&amdgpu_connector->base.base,
1887 dev->mode_config.scaling_mode_property,
1888 DRM_MODE_SCALE_NONE);
1889 if (amdgpu_audio != 0) {
1890 drm_object_attach_property(&amdgpu_connector->base.base,
1891 adev->mode_info.audio_property,
1892 AMDGPU_AUDIO_AUTO);
1893 }
1894 drm_object_attach_property(&amdgpu_connector->base.base,
1895 adev->mode_info.dither_property,
1896 AMDGPU_FMT_DITHER_DISABLE);
1897 connector->interlace_allowed = true;
1898 /* in theory with a DP to VGA converter... */
1899 connector->doublescan_allowed = false;
1900 break;
1901 case DRM_MODE_CONNECTOR_eDP:
1902 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1903 if (!amdgpu_dig_connector)
1904 goto failed;
1905 amdgpu_connector->con_priv = amdgpu_dig_connector;
1906 if (i2c_bus->valid) {
1907 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1908 if (amdgpu_connector->ddc_bus) {
1909 has_aux = true;
1910 ddc = &amdgpu_connector->ddc_bus->adapter;
1911 } else {
1912 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1913 }
1914 }
1915 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1916 &amdgpu_connector_edp_funcs,
1917 connector_type,
1918 ddc);
1919 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1920 drm_object_attach_property(&amdgpu_connector->base.base,
1921 dev->mode_config.scaling_mode_property,
1922 DRM_MODE_SCALE_FULLSCREEN);
1923 subpixel_order = SubPixelHorizontalRGB;
1924 connector->interlace_allowed = false;
1925 connector->doublescan_allowed = false;
1926 break;
1927 case DRM_MODE_CONNECTOR_LVDS:
1928 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1929 if (!amdgpu_dig_connector)
1930 goto failed;
1931 amdgpu_connector->con_priv = amdgpu_dig_connector;
1932 if (i2c_bus->valid) {
1933 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1934 if (!amdgpu_connector->ddc_bus)
1935 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1936 else
1937 ddc = &amdgpu_connector->ddc_bus->adapter;
1938 }
1939 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1940 &amdgpu_connector_lvds_funcs,
1941 connector_type,
1942 ddc);
1943 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1944 drm_object_attach_property(&amdgpu_connector->base.base,
1945 dev->mode_config.scaling_mode_property,
1946 DRM_MODE_SCALE_FULLSCREEN);
1947 subpixel_order = SubPixelHorizontalRGB;
1948 connector->interlace_allowed = false;
1949 connector->doublescan_allowed = false;
1950 break;
1951 }
1952 }
1953
1954 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1955 if (i2c_bus->valid) {
1956 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1957 DRM_CONNECTOR_POLL_DISCONNECT;
1958 }
1959 } else
1960 connector->polled = DRM_CONNECTOR_POLL_HPD;
1961
1962 connector->display_info.subpixel_order = subpixel_order;
1963
1964 if (has_aux)
1965 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1966
1967 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1968 connector_type == DRM_MODE_CONNECTOR_eDP) {
1969 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
1970 }
1971
1972 return;
1973
1974 failed:
1975 drm_connector_cleanup(connector);
1976 kfree(connector);
1977 }
1978
