1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 //
8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
10
11 /*
12 * Hardware interface for generic AMD ACP processor
13 */
14
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18
19 #include "../ops.h"
20 #include "acp.h"
21 #include "acp-dsp-offset.h"
22
smn_write(struct pci_dev * dev,u32 smn_addr,u32 data)23 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data)
24 {
25 pci_write_config_dword(dev, 0x60, smn_addr);
26 pci_write_config_dword(dev, 0x64, data);
27
28 return 0;
29 }
30
smn_read(struct pci_dev * dev,u32 smn_addr,u32 * data)31 static int smn_read(struct pci_dev *dev, u32 smn_addr, u32 *data)
32 {
33 pci_write_config_dword(dev, 0x60, smn_addr);
34 pci_read_config_dword(dev, 0x64, data);
35
36 return 0;
37 }
38
init_dma_descriptor(struct acp_dev_data * adata)39 static void init_dma_descriptor(struct acp_dev_data *adata)
40 {
41 struct snd_sof_dev *sdev = adata->dev;
42 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
43 unsigned int addr;
44
45 addr = desc->sram_pte_offset + sdev->debug_box.offset +
46 offsetof(struct scratch_reg_conf, dma_desc);
47
48 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);
49 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);
50 }
51
configure_dma_descriptor(struct acp_dev_data * adata,unsigned short idx,struct dma_descriptor * dscr_info)52 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
53 struct dma_descriptor *dscr_info)
54 {
55 struct snd_sof_dev *sdev = adata->dev;
56 unsigned int offset;
57
58 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +
59 offsetof(struct scratch_reg_conf, dma_desc) +
60 idx * sizeof(struct dma_descriptor);
61
62 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);
63 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
64 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
65 }
66
config_dma_channel(struct acp_dev_data * adata,unsigned int ch,unsigned int idx,unsigned int dscr_count)67 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
68 unsigned int idx, unsigned int dscr_count)
69 {
70 struct snd_sof_dev *sdev = adata->dev;
71 unsigned int val, status;
72 int ret;
73
74 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),
75 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
76
77 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,
78 val & (1 << ch), ACP_REG_POLL_INTERVAL,
79 ACP_REG_POLL_TIMEOUT_US);
80 if (ret < 0) {
81 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);
82 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
83
84 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
85 return ret;
86 }
87
88 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);
89 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);
90 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);
91 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);
92 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
93
94 return ret;
95 }
96
acpbus_dma_start(struct acp_dev_data * adata,unsigned int ch,unsigned int dscr_count,struct dma_descriptor * dscr_info)97 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,
98 unsigned int dscr_count, struct dma_descriptor *dscr_info)
99 {
100 struct snd_sof_dev *sdev = adata->dev;
101 int ret;
102 u16 dscr;
103
104 if (!dscr_info || !dscr_count)
105 return -EINVAL;
106
107 for (dscr = 0; dscr < dscr_count; dscr++)
108 configure_dma_descriptor(adata, dscr, dscr_info++);
109
110 ret = config_dma_channel(adata, ch, 0, dscr_count);
111 if (ret < 0)
112 dev_err(sdev->dev, "config dma ch failed:%d\n", ret);
113
114 return ret;
115 }
116
configure_and_run_dma(struct acp_dev_data * adata,unsigned int src_addr,unsigned int dest_addr,int dsp_data_size)117 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
118 unsigned int dest_addr, int dsp_data_size)
119 {
120 struct snd_sof_dev *sdev = adata->dev;
121 unsigned int desc_count, index;
122 int ret;
123
124 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0;
125 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) {
126 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE;
127 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE;
128 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE;
129 if (dsp_data_size < ACP_PAGE_SIZE)
130 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size;
131 }
132
133 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info);
134 if (ret)
135 dev_err(sdev->dev, "acpbus_dma_start failed\n");
136
137 /* Clear descriptor array */
138 for (index = 0; index < desc_count; index++)
139 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor));
140
141 return ret;
142 }
143
144 /*
145 * psp_mbox_ready- function to poll ready bit of psp mbox
146 * @adata: acp device data
147 * @ack: bool variable to check ready bit status or psp ack
148 */
149
psp_mbox_ready(struct acp_dev_data * adata,bool ack)150 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack)
151 {
152 struct snd_sof_dev *sdev = adata->dev;
153 int timeout;
154 u32 data;
155
156 for (timeout = ACP_PSP_TIMEOUT_COUNTER; timeout > 0; timeout--) {
157 msleep(20);
158 smn_read(adata->smn_dev, MP0_C2PMSG_114_REG, &data);
159 if (data & MBOX_READY_MASK)
160 return 0;
161 }
162
163 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);
164
165 if (ack)
166 return -ETIMEDOUT;
167
168 return -EBUSY;
169 }
170
171 /*
172 * psp_send_cmd - function to send psp command over mbox
173 * @adata: acp device data
174 * @cmd: non zero integer value for command type
175 */
176
psp_send_cmd(struct acp_dev_data * adata,int cmd)177 static int psp_send_cmd(struct acp_dev_data *adata, int cmd)
178 {
179 struct snd_sof_dev *sdev = adata->dev;
180 int ret, timeout;
181 u32 data;
182
183 if (!cmd)
184 return -EINVAL;
185
186 /* Get a non-zero Doorbell value from PSP */
187 for (timeout = ACP_PSP_TIMEOUT_COUNTER; timeout > 0; timeout--) {
188 msleep(MBOX_DELAY);
189 smn_read(adata->smn_dev, MP0_C2PMSG_73_REG, &data);
190 if (data)
191 break;
192 }
193
194 if (!timeout) {
195 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);
196 return -EINVAL;
197 }
198
199 /* Check if PSP is ready for new command */
200 ret = psp_mbox_ready(adata, 0);
201 if (ret)
202 return ret;
203
204 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd);
205
206 /* Ring the Doorbell for PSP */
207 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data);
208
209 /* Check MBOX ready as PSP ack */
210 ret = psp_mbox_ready(adata, 1);
211
212 return ret;
213 }
214
configure_and_run_sha_dma(struct acp_dev_data * adata,void * image_addr,unsigned int start_addr,unsigned int dest_addr,unsigned int image_length)215 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
216 unsigned int start_addr, unsigned int dest_addr,
217 unsigned int image_length)
218 {
219 struct snd_sof_dev *sdev = adata->dev;
220 unsigned int tx_count, fw_qualifier, val;
221 int ret;
222
223 if (!image_addr) {
224 dev_err(sdev->dev, "SHA DMA image address is NULL\n");
225 return -EINVAL;
226 }
227
228 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);
229 if (val & ACP_SHA_RUN) {
230 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);
231 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,
232 val, val & ACP_SHA_RESET,
233 ACP_REG_POLL_INTERVAL,
234 ACP_REG_POLL_TIMEOUT_US);
235 if (ret < 0) {
236 dev_err(sdev->dev, "SHA DMA Failed to Reset\n");
237 return ret;
238 }
239 }
240
241 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
242 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
243 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
244 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
245
246 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
247 tx_count, tx_count == image_length,
248 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
249 if (ret < 0) {
250 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);
251 return ret;
252 }
253
254 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND);
255 if (ret)
256 return ret;
257
258 fw_qualifier = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER);
259 if (!(fw_qualifier & DSP_FW_RUN_ENABLE)) {
260 dev_err(sdev->dev, "PSP validation failed\n");
261 return -EINVAL;
262 }
263
264 return 0;
265 }
266
acp_dma_status(struct acp_dev_data * adata,unsigned char ch)267 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)
268 {
269 struct snd_sof_dev *sdev = adata->dev;
270 unsigned int val;
271 int ret = 0;
272
273 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));
274 if (val & ACP_DMA_CH_RUN) {
275 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val,
276 ACP_REG_POLL_INTERVAL,
277 ACP_DMA_COMPLETE_TIMEOUT_US);
278 if (ret < 0)
279 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);
280 }
281
282 return ret;
283 }
284
memcpy_from_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * dst,size_t bytes)285 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)
286 {
287 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
288 int i, j;
289
290 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
291 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);
292 }
293
memcpy_to_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * src,size_t bytes)294 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)
295 {
296 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
297 int i, j;
298
299 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
300 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
301 }
302
acp_memory_init(struct snd_sof_dev * sdev)303 static int acp_memory_init(struct snd_sof_dev *sdev)
304 {
305 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
306 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
307
308 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,
309 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);
310 init_dma_descriptor(adata);
311
312 return 0;
313 }
314
acp_irq_thread(int irq,void * context)315 static irqreturn_t acp_irq_thread(int irq, void *context)
316 {
317 struct snd_sof_dev *sdev = context;
318 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
319 unsigned int base = desc->dsp_intr_base;
320 unsigned int val, count = ACP_HW_SEM_RETRY_COUNT;
321
322 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat);
323 if (val & ACP_SHA_STAT) {
324 /* Clear SHA interrupt raised by PSP */
325 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, val);
326 return IRQ_HANDLED;
327 }
328
329 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
330 if (val & ACP_DSP_TO_HOST_IRQ) {
331 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {
332 /* Wait until acquired HW Semaphore lock or timeout */
333 count--;
334 if (!count) {
335 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
336 return IRQ_NONE;
337 }
338 }
339
340 sof_ops(sdev)->irq_thread(irq, sdev);
341 val |= ACP_DSP_TO_HOST_IRQ;
342 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, val);
343
344 /* Unlock or Release HW Semaphore */
345 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
346
347 return IRQ_HANDLED;
348 }
349
350 return IRQ_NONE;
351 };
352
acp_irq_handler(int irq,void * dev_id)353 static irqreturn_t acp_irq_handler(int irq, void *dev_id)
354 {
355 struct snd_sof_dev *sdev = dev_id;
356 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
357 unsigned int base = desc->dsp_intr_base;
358 unsigned int val;
359
360 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
361 if (val)
362 return IRQ_WAKE_THREAD;
363
364 return IRQ_NONE;
365 }
366
acp_power_on(struct snd_sof_dev * sdev)367 static int acp_power_on(struct snd_sof_dev *sdev)
368 {
369 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
370 unsigned int base = desc->pgfsm_base;
371 unsigned int val;
372 int ret;
373
374 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
375
376 if (val == ACP_POWERED_ON)
377 return 0;
378
379 if (val & ACP_PGFSM_STATUS_MASK)
380 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
381 ACP_PGFSM_CNTL_POWER_ON_MASK);
382
383 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
384 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
385 if (ret < 0)
386 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");
387
388 return ret;
389 }
390
acp_reset(struct snd_sof_dev * sdev)391 static int acp_reset(struct snd_sof_dev *sdev)
392 {
393 unsigned int val;
394 int ret;
395
396 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);
397
398 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
399 val & ACP_SOFT_RESET_DONE_MASK,
400 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
401 if (ret < 0) {
402 dev_err(sdev->dev, "timeout asserting reset\n");
403 return ret;
404 }
405
406 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);
407
408 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
409 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
410 if (ret < 0)
411 dev_err(sdev->dev, "timeout in releasing reset\n");
412
413 return ret;
414 }
415
acp_init(struct snd_sof_dev * sdev)416 static int acp_init(struct snd_sof_dev *sdev)
417 {
418 int ret;
419
420 /* power on */
421 ret = acp_power_on(sdev);
422 if (ret) {
423 dev_err(sdev->dev, "ACP power on failed\n");
424 return ret;
425 }
426
427 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);
428 /* Reset */
429 return acp_reset(sdev);
430 }
431
amd_sof_acp_suspend(struct snd_sof_dev * sdev,u32 target_state)432 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
433 {
434 int ret;
435
436 ret = acp_reset(sdev);
437 if (ret) {
438 dev_err(sdev->dev, "ACP Reset failed\n");
439 return ret;
440 }
441
442 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);
443
444 return 0;
445 }
446 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON);
447
amd_sof_acp_resume(struct snd_sof_dev * sdev)448 int amd_sof_acp_resume(struct snd_sof_dev *sdev)
449 {
450 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
451 int ret;
452
453 ret = acp_init(sdev);
454 if (ret) {
455 dev_err(sdev->dev, "ACP Init failed\n");
456 return ret;
457 }
458
459 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, 0x03);
460
461 ret = acp_memory_init(sdev);
462
463 return ret;
464 }
465 EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON);
466
amd_sof_acp_probe(struct snd_sof_dev * sdev)467 int amd_sof_acp_probe(struct snd_sof_dev *sdev)
468 {
469 struct pci_dev *pci = to_pci_dev(sdev->dev);
470 struct acp_dev_data *adata;
471 const struct sof_amd_acp_desc *chip;
472 unsigned int addr;
473 int ret;
474
475 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),
476 GFP_KERNEL);
477 if (!adata)
478 return -ENOMEM;
479
480 adata->dev = sdev;
481 addr = pci_resource_start(pci, ACP_DSP_BAR);
482 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));
483 if (!sdev->bar[ACP_DSP_BAR]) {
484 dev_err(sdev->dev, "ioremap error\n");
485 return -ENXIO;
486 }
487
488 pci_set_master(pci);
489
490 sdev->pdata->hw_pdata = adata;
491
492 chip = get_chip_info(sdev->pdata);
493 if (!chip) {
494 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);
495 return -EIO;
496 }
497
498 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL);
499 if (!adata->smn_dev) {
500 dev_err(sdev->dev, "Failed to get host bridge device\n");
501 return -ENODEV;
502 }
503
504 sdev->ipc_irq = pci->irq;
505 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,
506 IRQF_SHARED, "AudioDSP", sdev);
507 if (ret < 0) {
508 dev_err(sdev->dev, "failed to register IRQ %d\n",
509 sdev->ipc_irq);
510 pci_dev_put(adata->smn_dev);
511 return ret;
512 }
513
514 ret = acp_init(sdev);
515 if (ret < 0) {
516 free_irq(sdev->ipc_irq, sdev);
517 pci_dev_put(adata->smn_dev);
518 return ret;
519 }
520
521 sdev->dsp_box.offset = 0;
522 sdev->dsp_box.size = BOX_SIZE_512;
523
524 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;
525 sdev->host_box.size = BOX_SIZE_512;
526
527 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;
528 sdev->debug_box.size = BOX_SIZE_1024;
529
530 acp_memory_init(sdev);
531
532 acp_dsp_stream_init(sdev);
533
534 return 0;
535 }
536 EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON);
537
amd_sof_acp_remove(struct snd_sof_dev * sdev)538 int amd_sof_acp_remove(struct snd_sof_dev *sdev)
539 {
540 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
541
542 if (adata->smn_dev)
543 pci_dev_put(adata->smn_dev);
544
545 if (sdev->ipc_irq)
546 free_irq(sdev->ipc_irq, sdev);
547
548 return acp_reset(sdev);
549 }
550 EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON);
551
552 MODULE_DESCRIPTION("AMD ACP sof driver");
553 MODULE_LICENSE("Dual BSD/GPL");
554
