1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Shared support code for AMD K8 northbridges and derivatives.
4 * Copyright 2006 Andi Kleen, SUSE Labs.
5 */
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/types.h>
10 #include <linux/slab.h>
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/export.h>
14 #include <linux/spinlock.h>
15 #include <linux/pci_ids.h>
16 #include <asm/amd_nb.h>
17
18 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
22 #define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
23 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
24 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
25 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
26 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
27 #define PCI_DEVICE_ID_AMD_1AH_M00H_ROOT 0x153a
28 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
29 #define PCI_DEVICE_ID_AMD_MI200_ROOT 0x14bb
30
31 #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
32 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
33 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
34 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
35 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
36 #define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4 0x1728
37 #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
38 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
39 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
40 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
41 #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
42 #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
43 #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4 0x12fc
44 #define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4 0x12c4
45 #define PCI_DEVICE_ID_AMD_MI200_DF_F4 0x14d4
46
47 /* Protect the PCI config register pairs used for SMN. */
48 static DEFINE_MUTEX(smn_mutex);
49
50 static u32 *flush_words;
51
52 static const struct pci_device_id amd_root_ids[] = {
53 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
54 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
55 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
56 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
57 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
58 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
59 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
60 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_ROOT) },
63 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
64 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_ROOT) },
65 {}
66 };
67
68 #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
69
70 static const struct pci_device_id amd_nb_misc_ids[] = {
71 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
72 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
73 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
74 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
75 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
76 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
77 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
78 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
79 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
80 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
81 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
82 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
83 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
84 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
85 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
86 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
87 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
88 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
89 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
90 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
91 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
92 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
93 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
94 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
95 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F3) },
96 {}
97 };
98
99 static const struct pci_device_id amd_nb_link_ids[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
101 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
102 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
103 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
104 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
105 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
106 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
107 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
108 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
109 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
110 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
111 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
112 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
113 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
114 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
115 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
116 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4) },
117 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F4) },
118 {}
119 };
120
121 static const struct pci_device_id hygon_root_ids[] = {
122 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
123 {}
124 };
125
126 static const struct pci_device_id hygon_nb_misc_ids[] = {
127 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
128 {}
129 };
130
131 static const struct pci_device_id hygon_nb_link_ids[] = {
132 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
133 {}
134 };
135
136 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
137 { 0x00, 0x18, 0x20 },
138 { 0xff, 0x00, 0x20 },
139 { 0xfe, 0x00, 0x20 },
140 { }
141 };
142
143 static struct amd_northbridge_info amd_northbridges;
144
amd_nb_num(void)145 u16 amd_nb_num(void)
146 {
147 return amd_northbridges.num;
148 }
149 EXPORT_SYMBOL_GPL(amd_nb_num);
150
amd_nb_has_feature(unsigned int feature)151 bool amd_nb_has_feature(unsigned int feature)
152 {
153 return ((amd_northbridges.flags & feature) == feature);
154 }
155 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
156
node_to_amd_nb(int node)157 struct amd_northbridge *node_to_amd_nb(int node)
158 {
159 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
160 }
161 EXPORT_SYMBOL_GPL(node_to_amd_nb);
162
next_northbridge(struct pci_dev * dev,const struct pci_device_id * ids)163 static struct pci_dev *next_northbridge(struct pci_dev *dev,
164 const struct pci_device_id *ids)
165 {
166 do {
167 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
168 if (!dev)
169 break;
170 } while (!pci_match_id(ids, dev));
171 return dev;
172 }
173
__amd_smn_rw(u16 node,u32 address,u32 * value,bool write)174 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
175 {
176 struct pci_dev *root;
177 int err = -ENODEV;
178
179 if (node >= amd_northbridges.num)
180 goto out;
181
182 root = node_to_amd_nb(node)->root;
183 if (!root)
184 goto out;
185
186 mutex_lock(&smn_mutex);
187
188 err = pci_write_config_dword(root, 0x60, address);
189 if (err) {
190 pr_warn("Error programming SMN address 0x%x.\n", address);
191 goto out_unlock;
192 }
193
194 err = (write ? pci_write_config_dword(root, 0x64, *value)
195 : pci_read_config_dword(root, 0x64, value));
196 if (err)
197 pr_warn("Error %s SMN address 0x%x.\n",
198 (write ? "writing to" : "reading from"), address);
199
200 out_unlock:
201 mutex_unlock(&smn_mutex);
202
203 out:
204 return err;
205 }
206
amd_smn_read(u16 node,u32 address,u32 * value)207 int amd_smn_read(u16 node, u32 address, u32 *value)
208 {
209 return __amd_smn_rw(node, address, value, false);
210 }
211 EXPORT_SYMBOL_GPL(amd_smn_read);
212
amd_smn_write(u16 node,u32 address,u32 value)213 int amd_smn_write(u16 node, u32 address, u32 value)
214 {
215 return __amd_smn_rw(node, address, &value, true);
216 }
217 EXPORT_SYMBOL_GPL(amd_smn_write);
218
219
amd_cache_northbridges(void)220 static int amd_cache_northbridges(void)
221 {
222 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
223 const struct pci_device_id *link_ids = amd_nb_link_ids;
224 const struct pci_device_id *root_ids = amd_root_ids;
225 struct pci_dev *root, *misc, *link;
226 struct amd_northbridge *nb;
227 u16 roots_per_misc = 0;
228 u16 misc_count = 0;
229 u16 root_count = 0;
230 u16 i, j;
231
232 if (amd_northbridges.num)
233 return 0;
234
235 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
236 root_ids = hygon_root_ids;
237 misc_ids = hygon_nb_misc_ids;
238 link_ids = hygon_nb_link_ids;
239 }
240
241 misc = NULL;
242 while ((misc = next_northbridge(misc, misc_ids)))
243 misc_count++;
244
245 if (!misc_count)
246 return -ENODEV;
247
248 root = NULL;
249 while ((root = next_northbridge(root, root_ids)))
250 root_count++;
251
252 if (root_count) {
253 roots_per_misc = root_count / misc_count;
254
255 /*
256 * There should be _exactly_ N roots for each DF/SMN
257 * interface.
258 */
259 if (!roots_per_misc || (root_count % roots_per_misc)) {
260 pr_info("Unsupported AMD DF/PCI configuration found\n");
261 return -ENODEV;
262 }
263 }
264
265 nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
266 if (!nb)
267 return -ENOMEM;
268
269 amd_northbridges.nb = nb;
270 amd_northbridges.num = misc_count;
271
272 link = misc = root = NULL;
273 for (i = 0; i < amd_northbridges.num; i++) {
274 node_to_amd_nb(i)->root = root =
275 next_northbridge(root, root_ids);
276 node_to_amd_nb(i)->misc = misc =
277 next_northbridge(misc, misc_ids);
278 node_to_amd_nb(i)->link = link =
279 next_northbridge(link, link_ids);
280
281 /*
282 * If there are more PCI root devices than data fabric/
283 * system management network interfaces, then the (N)
284 * PCI roots per DF/SMN interface are functionally the
285 * same (for DF/SMN access) and N-1 are redundant. N-1
286 * PCI roots should be skipped per DF/SMN interface so
287 * the following DF/SMN interfaces get mapped to
288 * correct PCI roots.
289 */
290 for (j = 1; j < roots_per_misc; j++)
291 root = next_northbridge(root, root_ids);
292 }
293
294 if (amd_gart_present())
295 amd_northbridges.flags |= AMD_NB_GART;
296
297 /*
298 * Check for L3 cache presence.
299 */
300 if (!cpuid_edx(0x80000006))
301 return 0;
302
303 /*
304 * Some CPU families support L3 Cache Index Disable. There are some
305 * limitations because of E382 and E388 on family 0x10.
306 */
307 if (boot_cpu_data.x86 == 0x10 &&
308 boot_cpu_data.x86_model >= 0x8 &&
309 (boot_cpu_data.x86_model > 0x9 ||
310 boot_cpu_data.x86_stepping >= 0x1))
311 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
312
313 if (boot_cpu_data.x86 == 0x15)
314 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
315
316 /* L3 cache partitioning is supported on family 0x15 */
317 if (boot_cpu_data.x86 == 0x15)
318 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
319
320 return 0;
321 }
322
323 /*
324 * Ignores subdevice/subvendor but as far as I can figure out
325 * they're useless anyways
326 */
early_is_amd_nb(u32 device)327 bool __init early_is_amd_nb(u32 device)
328 {
329 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
330 const struct pci_device_id *id;
331 u32 vendor = device & 0xffff;
332
333 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
334 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
335 return false;
336
337 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
338 misc_ids = hygon_nb_misc_ids;
339
340 device >>= 16;
341 for (id = misc_ids; id->vendor; id++)
342 if (vendor == id->vendor && device == id->device)
343 return true;
344 return false;
345 }
346
amd_get_mmconfig_range(struct resource * res)347 struct resource *amd_get_mmconfig_range(struct resource *res)
348 {
349 u32 address;
350 u64 base, msr;
351 unsigned int segn_busn_bits;
352
353 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
354 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
355 return NULL;
356
357 /* assume all cpus from fam10h have mmconfig */
358 if (boot_cpu_data.x86 < 0x10)
359 return NULL;
360
361 address = MSR_FAM10H_MMIO_CONF_BASE;
362 rdmsrl(address, msr);
363
364 /* mmconfig is not enabled */
365 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
366 return NULL;
367
368 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
369
370 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
371 FAM10H_MMIO_CONF_BUSRANGE_MASK;
372
373 res->flags = IORESOURCE_MEM;
374 res->start = base;
375 res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
376 return res;
377 }
378
amd_get_subcaches(int cpu)379 int amd_get_subcaches(int cpu)
380 {
381 struct pci_dev *link = node_to_amd_nb(topology_die_id(cpu))->link;
382 unsigned int mask;
383
384 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
385 return 0;
386
387 pci_read_config_dword(link, 0x1d4, &mask);
388
389 return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
390 }
391
amd_set_subcaches(int cpu,unsigned long mask)392 int amd_set_subcaches(int cpu, unsigned long mask)
393 {
394 static unsigned int reset, ban;
395 struct amd_northbridge *nb = node_to_amd_nb(topology_die_id(cpu));
396 unsigned int reg;
397 int cuid;
398
399 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
400 return -EINVAL;
401
402 /* if necessary, collect reset state of L3 partitioning and BAN mode */
403 if (reset == 0) {
404 pci_read_config_dword(nb->link, 0x1d4, &reset);
405 pci_read_config_dword(nb->misc, 0x1b8, &ban);
406 ban &= 0x180000;
407 }
408
409 /* deactivate BAN mode if any subcaches are to be disabled */
410 if (mask != 0xf) {
411 pci_read_config_dword(nb->misc, 0x1b8, ®);
412 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
413 }
414
415 cuid = cpu_data(cpu).cpu_core_id;
416 mask <<= 4 * cuid;
417 mask |= (0xf ^ (1 << cuid)) << 26;
418
419 pci_write_config_dword(nb->link, 0x1d4, mask);
420
421 /* reset BAN mode if L3 partitioning returned to reset state */
422 pci_read_config_dword(nb->link, 0x1d4, ®);
423 if (reg == reset) {
424 pci_read_config_dword(nb->misc, 0x1b8, ®);
425 reg &= ~0x180000;
426 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
427 }
428
429 return 0;
430 }
431
amd_cache_gart(void)432 static void amd_cache_gart(void)
433 {
434 u16 i;
435
436 if (!amd_nb_has_feature(AMD_NB_GART))
437 return;
438
439 flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
440 if (!flush_words) {
441 amd_northbridges.flags &= ~AMD_NB_GART;
442 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
443 return;
444 }
445
446 for (i = 0; i != amd_northbridges.num; i++)
447 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
448 }
449
amd_flush_garts(void)450 void amd_flush_garts(void)
451 {
452 int flushed, i;
453 unsigned long flags;
454 static DEFINE_SPINLOCK(gart_lock);
455
456 if (!amd_nb_has_feature(AMD_NB_GART))
457 return;
458
459 /*
460 * Avoid races between AGP and IOMMU. In theory it's not needed
461 * but I'm not sure if the hardware won't lose flush requests
462 * when another is pending. This whole thing is so expensive anyways
463 * that it doesn't matter to serialize more. -AK
464 */
465 spin_lock_irqsave(&gart_lock, flags);
466 flushed = 0;
467 for (i = 0; i < amd_northbridges.num; i++) {
468 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
469 flush_words[i] | 1);
470 flushed++;
471 }
472 for (i = 0; i < amd_northbridges.num; i++) {
473 u32 w;
474 /* Make sure the hardware actually executed the flush*/
475 for (;;) {
476 pci_read_config_dword(node_to_amd_nb(i)->misc,
477 0x9c, &w);
478 if (!(w & 1))
479 break;
480 cpu_relax();
481 }
482 }
483 spin_unlock_irqrestore(&gart_lock, flags);
484 if (!flushed)
485 pr_notice("nothing to flush?\n");
486 }
487 EXPORT_SYMBOL_GPL(amd_flush_garts);
488
__fix_erratum_688(void * info)489 static void __fix_erratum_688(void *info)
490 {
491 #define MSR_AMD64_IC_CFG 0xC0011021
492
493 msr_set_bit(MSR_AMD64_IC_CFG, 3);
494 msr_set_bit(MSR_AMD64_IC_CFG, 14);
495 }
496
497 /* Apply erratum 688 fix so machines without a BIOS fix work. */
fix_erratum_688(void)498 static __init void fix_erratum_688(void)
499 {
500 struct pci_dev *F4;
501 u32 val;
502
503 if (boot_cpu_data.x86 != 0x14)
504 return;
505
506 if (!amd_northbridges.num)
507 return;
508
509 F4 = node_to_amd_nb(0)->link;
510 if (!F4)
511 return;
512
513 if (pci_read_config_dword(F4, 0x164, &val))
514 return;
515
516 if (val & BIT(2))
517 return;
518
519 on_each_cpu(__fix_erratum_688, NULL, 0);
520
521 pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
522 }
523
init_amd_nbs(void)524 static __init int init_amd_nbs(void)
525 {
526 amd_cache_northbridges();
527 amd_cache_gart();
528
529 fix_erratum_688();
530
531 return 0;
532 }
533
534 /* This has to go after the PCI subsystem */
535 fs_initcall(init_amd_nbs);
536
