1 /* 2 * 3 * Copyright (C) 2013 Texas Instruments Incorporated 4 * 5 * Interconnects common for AM335x and AM43x 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/sizes.h> 18 #include "omap_hwmod.h" 19 #include "omap_hwmod_33xx_43xx_common_data.h" 20 21 /* mpu -> l3 main */ 22 struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { 23 .master = &am33xx_mpu_hwmod, 24 .slave = &am33xx_l3_main_hwmod, 25 .clk = "dpll_mpu_m2_ck", 26 .user = OCP_USER_MPU, 27 }; 28 29 /* l3 main -> l3 s */ 30 struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { 31 .master = &am33xx_l3_main_hwmod, 32 .slave = &am33xx_l3_s_hwmod, 33 .clk = "l3s_gclk", 34 .user = OCP_USER_MPU | OCP_USER_SDMA, 35 }; 36 37 /* l3 s -> l4 per/ls */ 38 struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { 39 .master = &am33xx_l3_s_hwmod, 40 .slave = &am33xx_l4_ls_hwmod, 41 .clk = "l3s_gclk", 42 .user = OCP_USER_MPU | OCP_USER_SDMA, 43 }; 44 45 /* l3 s -> l4 wkup */ 46 struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { 47 .master = &am33xx_l3_s_hwmod, 48 .slave = &am33xx_l4_wkup_hwmod, 49 .clk = "l3s_gclk", 50 .user = OCP_USER_MPU | OCP_USER_SDMA, 51 }; 52 53 /* l3 main -> l3 instr */ 54 struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { 55 .master = &am33xx_l3_main_hwmod, 56 .slave = &am33xx_l3_instr_hwmod, 57 .clk = "l3s_gclk", 58 .user = OCP_USER_MPU | OCP_USER_SDMA, 59 }; 60 61 /* mpu -> prcm */ 62 struct omap_hwmod_ocp_if am33xx_mpu__prcm = { 63 .master = &am33xx_mpu_hwmod, 64 .slave = &am33xx_prcm_hwmod, 65 .clk = "dpll_mpu_m2_ck", 66 .user = OCP_USER_MPU | OCP_USER_SDMA, 67 }; 68 69 /* l3 s -> l3 main*/ 70 struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { 71 .master = &am33xx_l3_s_hwmod, 72 .slave = &am33xx_l3_main_hwmod, 73 .clk = "l3s_gclk", 74 .user = OCP_USER_MPU | OCP_USER_SDMA, 75 }; 76 77 /* pru-icss -> l3 main */ 78 struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { 79 .master = &am33xx_pruss_hwmod, 80 .slave = &am33xx_l3_main_hwmod, 81 .clk = "l3_gclk", 82 .user = OCP_USER_MPU | OCP_USER_SDMA, 83 }; 84 85 /* gfx -> l3 main */ 86 struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { 87 .master = &am33xx_gfx_hwmod, 88 .slave = &am33xx_l3_main_hwmod, 89 .clk = "dpll_core_m4_ck", 90 .user = OCP_USER_MPU | OCP_USER_SDMA, 91 }; 92 93 /* l3 main -> gfx */ 94 struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { 95 .master = &am33xx_l3_main_hwmod, 96 .slave = &am33xx_gfx_hwmod, 97 .clk = "dpll_core_m4_ck", 98 .user = OCP_USER_MPU | OCP_USER_SDMA, 99 }; 100 101 /* l4 wkup -> rtc */ 102 struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { 103 .master = &am33xx_l4_wkup_hwmod, 104 .slave = &am33xx_rtc_hwmod, 105 .clk = "clkdiv32k_ick", 106 .user = OCP_USER_MPU, 107 }; 108 109 /* l4 per/ls -> DCAN0 */ 110 struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { 111 .master = &am33xx_l4_ls_hwmod, 112 .slave = &am33xx_dcan0_hwmod, 113 .clk = "l4ls_gclk", 114 .user = OCP_USER_MPU | OCP_USER_SDMA, 115 }; 116 117 /* l4 per/ls -> DCAN1 */ 118 struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { 119 .master = &am33xx_l4_ls_hwmod, 120 .slave = &am33xx_dcan1_hwmod, 121 .clk = "l4ls_gclk", 122 .user = OCP_USER_MPU | OCP_USER_SDMA, 123 }; 124 125 /* l4 per/ls -> GPIO2 */ 126 struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { 127 .master = &am33xx_l4_ls_hwmod, 128 .slave = &am33xx_gpio1_hwmod, 129 .clk = "l4ls_gclk", 130 .user = OCP_USER_MPU | OCP_USER_SDMA, 131 }; 132 133 /* l4 per/ls -> gpio3 */ 134 struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { 135 .master = &am33xx_l4_ls_hwmod, 136 .slave = &am33xx_gpio2_hwmod, 137 .clk = "l4ls_gclk", 138 .user = OCP_USER_MPU | OCP_USER_SDMA, 139 }; 140 141 /* l4 per/ls -> gpio4 */ 142 struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { 143 .master = &am33xx_l4_ls_hwmod, 144 .slave = &am33xx_gpio3_hwmod, 145 .clk = "l4ls_gclk", 146 .user = OCP_USER_MPU | OCP_USER_SDMA, 147 }; 148 149 struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { 150 .master = &am33xx_cpgmac0_hwmod, 151 .slave = &am33xx_mdio_hwmod, 152 .user = OCP_USER_MPU, 153 }; 154 155 struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { 156 .master = &am33xx_l4_ls_hwmod, 157 .slave = &am33xx_elm_hwmod, 158 .clk = "l4ls_gclk", 159 .user = OCP_USER_MPU, 160 }; 161 162 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { 163 .master = &am33xx_l4_ls_hwmod, 164 .slave = &am33xx_epwmss0_hwmod, 165 .clk = "l4ls_gclk", 166 .user = OCP_USER_MPU, 167 }; 168 169 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { 170 .master = &am33xx_l4_ls_hwmod, 171 .slave = &am33xx_epwmss1_hwmod, 172 .clk = "l4ls_gclk", 173 .user = OCP_USER_MPU, 174 }; 175 176 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { 177 .master = &am33xx_l4_ls_hwmod, 178 .slave = &am33xx_epwmss2_hwmod, 179 .clk = "l4ls_gclk", 180 .user = OCP_USER_MPU, 181 }; 182 183 /* l3s cfg -> gpmc */ 184 struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { 185 .master = &am33xx_l3_s_hwmod, 186 .slave = &am33xx_gpmc_hwmod, 187 .clk = "l3s_gclk", 188 .user = OCP_USER_MPU, 189 }; 190 191 /* i2c2 */ 192 struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { 193 .master = &am33xx_l4_ls_hwmod, 194 .slave = &am33xx_i2c2_hwmod, 195 .clk = "l4ls_gclk", 196 .user = OCP_USER_MPU, 197 }; 198 199 struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { 200 .master = &am33xx_l4_ls_hwmod, 201 .slave = &am33xx_i2c3_hwmod, 202 .clk = "l4ls_gclk", 203 .user = OCP_USER_MPU, 204 }; 205 206 /* l4 ls -> mailbox */ 207 struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { 208 .master = &am33xx_l4_ls_hwmod, 209 .slave = &am33xx_mailbox_hwmod, 210 .clk = "l4ls_gclk", 211 .user = OCP_USER_MPU, 212 }; 213 214 /* l4 ls -> spinlock */ 215 struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { 216 .master = &am33xx_l4_ls_hwmod, 217 .slave = &am33xx_spinlock_hwmod, 218 .clk = "l4ls_gclk", 219 .user = OCP_USER_MPU, 220 }; 221 222 /* l4 ls -> mcasp0 */ 223 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { 224 .master = &am33xx_l4_ls_hwmod, 225 .slave = &am33xx_mcasp0_hwmod, 226 .clk = "l4ls_gclk", 227 .user = OCP_USER_MPU, 228 }; 229 230 /* l4 ls -> mcasp1 */ 231 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { 232 .master = &am33xx_l4_ls_hwmod, 233 .slave = &am33xx_mcasp1_hwmod, 234 .clk = "l4ls_gclk", 235 .user = OCP_USER_MPU, 236 }; 237 238 /* l4 ls -> mmc0 */ 239 struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { 240 .master = &am33xx_l4_ls_hwmod, 241 .slave = &am33xx_mmc0_hwmod, 242 .clk = "l4ls_gclk", 243 .user = OCP_USER_MPU, 244 }; 245 246 /* l4 ls -> mmc1 */ 247 struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { 248 .master = &am33xx_l4_ls_hwmod, 249 .slave = &am33xx_mmc1_hwmod, 250 .clk = "l4ls_gclk", 251 .user = OCP_USER_MPU, 252 }; 253 254 /* l3 s -> mmc2 */ 255 struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { 256 .master = &am33xx_l3_s_hwmod, 257 .slave = &am33xx_mmc2_hwmod, 258 .clk = "l3s_gclk", 259 .user = OCP_USER_MPU, 260 }; 261 262 /* l4 ls -> mcspi0 */ 263 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { 264 .master = &am33xx_l4_ls_hwmod, 265 .slave = &am33xx_spi0_hwmod, 266 .clk = "l4ls_gclk", 267 .user = OCP_USER_MPU, 268 }; 269 270 /* l4 ls -> mcspi1 */ 271 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { 272 .master = &am33xx_l4_ls_hwmod, 273 .slave = &am33xx_spi1_hwmod, 274 .clk = "l4ls_gclk", 275 .user = OCP_USER_MPU, 276 }; 277 278 /* l4 per -> timer2 */ 279 struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { 280 .master = &am33xx_l4_ls_hwmod, 281 .slave = &am33xx_timer2_hwmod, 282 .clk = "l4ls_gclk", 283 .user = OCP_USER_MPU, 284 }; 285 286 /* l4 per -> timer3 */ 287 struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { 288 .master = &am33xx_l4_ls_hwmod, 289 .slave = &am33xx_timer3_hwmod, 290 .clk = "l4ls_gclk", 291 .user = OCP_USER_MPU, 292 }; 293 294 /* l4 per -> timer4 */ 295 struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { 296 .master = &am33xx_l4_ls_hwmod, 297 .slave = &am33xx_timer4_hwmod, 298 .clk = "l4ls_gclk", 299 .user = OCP_USER_MPU, 300 }; 301 302 /* l4 per -> timer5 */ 303 struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { 304 .master = &am33xx_l4_ls_hwmod, 305 .slave = &am33xx_timer5_hwmod, 306 .clk = "l4ls_gclk", 307 .user = OCP_USER_MPU, 308 }; 309 310 /* l4 per -> timer6 */ 311 struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { 312 .master = &am33xx_l4_ls_hwmod, 313 .slave = &am33xx_timer6_hwmod, 314 .clk = "l4ls_gclk", 315 .user = OCP_USER_MPU, 316 }; 317 318 /* l4 per -> timer7 */ 319 struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { 320 .master = &am33xx_l4_ls_hwmod, 321 .slave = &am33xx_timer7_hwmod, 322 .clk = "l4ls_gclk", 323 .user = OCP_USER_MPU, 324 }; 325 326 /* l3 main -> tpcc */ 327 struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { 328 .master = &am33xx_l3_main_hwmod, 329 .slave = &am33xx_tpcc_hwmod, 330 .clk = "l3_gclk", 331 .user = OCP_USER_MPU, 332 }; 333 334 /* l3 main -> tpcc0 */ 335 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { 336 .master = &am33xx_l3_main_hwmod, 337 .slave = &am33xx_tptc0_hwmod, 338 .clk = "l3_gclk", 339 .user = OCP_USER_MPU, 340 }; 341 342 /* l3 main -> tpcc1 */ 343 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { 344 .master = &am33xx_l3_main_hwmod, 345 .slave = &am33xx_tptc1_hwmod, 346 .clk = "l3_gclk", 347 .user = OCP_USER_MPU, 348 }; 349 350 /* l3 main -> tpcc2 */ 351 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { 352 .master = &am33xx_l3_main_hwmod, 353 .slave = &am33xx_tptc2_hwmod, 354 .clk = "l3_gclk", 355 .user = OCP_USER_MPU, 356 }; 357 358 /* l4 ls -> uart2 */ 359 struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { 360 .master = &am33xx_l4_ls_hwmod, 361 .slave = &am33xx_uart2_hwmod, 362 .clk = "l4ls_gclk", 363 .user = OCP_USER_MPU, 364 }; 365 366 /* l4 ls -> uart3 */ 367 struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { 368 .master = &am33xx_l4_ls_hwmod, 369 .slave = &am33xx_uart3_hwmod, 370 .clk = "l4ls_gclk", 371 .user = OCP_USER_MPU, 372 }; 373 374 /* l4 ls -> uart4 */ 375 struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { 376 .master = &am33xx_l4_ls_hwmod, 377 .slave = &am33xx_uart4_hwmod, 378 .clk = "l4ls_gclk", 379 .user = OCP_USER_MPU, 380 }; 381 382 /* l4 ls -> uart5 */ 383 struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { 384 .master = &am33xx_l4_ls_hwmod, 385 .slave = &am33xx_uart5_hwmod, 386 .clk = "l4ls_gclk", 387 .user = OCP_USER_MPU, 388 }; 389 390 /* l4 ls -> uart6 */ 391 struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { 392 .master = &am33xx_l4_ls_hwmod, 393 .slave = &am33xx_uart6_hwmod, 394 .clk = "l4ls_gclk", 395 .user = OCP_USER_MPU, 396 }; 397 398 /* l3 main -> ocmc */ 399 struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { 400 .master = &am33xx_l3_main_hwmod, 401 .slave = &am33xx_ocmcram_hwmod, 402 .user = OCP_USER_MPU | OCP_USER_SDMA, 403 }; 404 405 /* l3 main -> sha0 HIB2 */ 406 struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { 407 .master = &am33xx_l3_main_hwmod, 408 .slave = &am33xx_sha0_hwmod, 409 .clk = "sha0_fck", 410 .user = OCP_USER_MPU | OCP_USER_SDMA, 411 }; 412 413 /* l3 main -> AES0 HIB2 */ 414 struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { 415 .master = &am33xx_l3_main_hwmod, 416 .slave = &am33xx_aes0_hwmod, 417 .clk = "aes0_fck", 418 .user = OCP_USER_MPU | OCP_USER_SDMA, 419 }; 420 421 /* l4 per -> rng */ 422 struct omap_hwmod_ocp_if am33xx_l4_per__rng = { 423 .master = &am33xx_l4_ls_hwmod, 424 .slave = &am33xx_rng_hwmod, 425 .clk = "rng_fck", 426 .user = OCP_USER_MPU, 427 }; 428
