1 /*
2 * alternative runtime patching
3 * inspired by the x86 version
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define pr_fmt(fmt) "alternatives: " fmt
21
22 #include <linux/init.h>
23 #include <linux/cpu.h>
24 #include <asm/cacheflush.h>
25 #include <asm/alternative.h>
26 #include <asm/cpufeature.h>
27 #include <asm/insn.h>
28 #include <asm/sections.h>
29 #include <linux/stop_machine.h>
30
31 #define __ALT_PTR(a,f) ((void *)&(a)->f + (a)->f)
32 #define ALT_ORIG_PTR(a) __ALT_PTR(a, orig_offset)
33 #define ALT_REPL_PTR(a) __ALT_PTR(a, alt_offset)
34
35 int alternatives_applied;
36
37 struct alt_region {
38 struct alt_instr *begin;
39 struct alt_instr *end;
40 };
41
42 /*
43 * Check if the target PC is within an alternative block.
44 */
branch_insn_requires_update(struct alt_instr * alt,unsigned long pc)45 static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc)
46 {
47 unsigned long replptr;
48
49 if (kernel_text_address(pc))
50 return true;
51
52 replptr = (unsigned long)ALT_REPL_PTR(alt);
53 if (pc >= replptr && pc <= (replptr + alt->alt_len))
54 return false;
55
56 /*
57 * Branching into *another* alternate sequence is doomed, and
58 * we're not even trying to fix it up.
59 */
60 BUG();
61 }
62
63 #define align_down(x, a) ((unsigned long)(x) & ~(((unsigned long)(a)) - 1))
64
get_alt_insn(struct alt_instr * alt,__le32 * insnptr,__le32 * altinsnptr)65 static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr)
66 {
67 u32 insn;
68
69 insn = le32_to_cpu(*altinsnptr);
70
71 if (aarch64_insn_is_branch_imm(insn)) {
72 s32 offset = aarch64_get_branch_offset(insn);
73 unsigned long target;
74
75 target = (unsigned long)altinsnptr + offset;
76
77 /*
78 * If we're branching inside the alternate sequence,
79 * do not rewrite the instruction, as it is already
80 * correct. Otherwise, generate the new instruction.
81 */
82 if (branch_insn_requires_update(alt, target)) {
83 offset = target - (unsigned long)insnptr;
84 insn = aarch64_set_branch_offset(insn, offset);
85 }
86 } else if (aarch64_insn_is_adrp(insn)) {
87 s32 orig_offset, new_offset;
88 unsigned long target;
89
90 /*
91 * If we're replacing an adrp instruction, which uses PC-relative
92 * immediate addressing, adjust the offset to reflect the new
93 * PC. adrp operates on 4K aligned addresses.
94 */
95 orig_offset = aarch64_insn_adrp_get_offset(insn);
96 target = align_down(altinsnptr, SZ_4K) + orig_offset;
97 new_offset = target - align_down(insnptr, SZ_4K);
98 insn = aarch64_insn_adrp_set_offset(insn, new_offset);
99 } else if (aarch64_insn_uses_literal(insn)) {
100 /*
101 * Disallow patching unhandled instructions using PC relative
102 * literal addresses
103 */
104 BUG();
105 }
106
107 return insn;
108 }
109
patch_alternative(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)110 static void patch_alternative(struct alt_instr *alt,
111 __le32 *origptr, __le32 *updptr, int nr_inst)
112 {
113 __le32 *replptr;
114 int i;
115
116 replptr = ALT_REPL_PTR(alt);
117 for (i = 0; i < nr_inst; i++) {
118 u32 insn;
119
120 insn = get_alt_insn(alt, origptr + i, replptr + i);
121 updptr[i] = cpu_to_le32(insn);
122 }
123 }
124
125 /*
126 * We provide our own, private D-cache cleaning function so that we don't
127 * accidentally call into the cache.S code, which is patched by us at
128 * runtime.
129 */
clean_dcache_range_nopatch(u64 start,u64 end)130 static void clean_dcache_range_nopatch(u64 start, u64 end)
131 {
132 u64 cur, d_size, ctr_el0;
133
134 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
135 d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0,
136 CTR_DMINLINE_SHIFT);
137 cur = start & ~(d_size - 1);
138 do {
139 /*
140 * We must clean+invalidate to the PoC in order to avoid
141 * Cortex-A53 errata 826319, 827319, 824069 and 819472
142 * (this corresponds to ARM64_WORKAROUND_CLEAN_CACHE)
143 */
144 asm volatile("dc civac, %0" : : "r" (cur) : "memory");
145 } while (cur += d_size, cur < end);
146 }
147
__apply_alternatives(void * alt_region,bool is_module)148 static void __apply_alternatives(void *alt_region, bool is_module)
149 {
150 struct alt_instr *alt;
151 struct alt_region *region = alt_region;
152 __le32 *origptr, *updptr;
153 alternative_cb_t alt_cb;
154
155 for (alt = region->begin; alt < region->end; alt++) {
156 int nr_inst;
157
158 /* Use ARM64_CB_PATCH as an unconditional patch */
159 if (alt->cpufeature < ARM64_CB_PATCH &&
160 !cpus_have_cap(alt->cpufeature))
161 continue;
162
163 if (alt->cpufeature == ARM64_CB_PATCH)
164 BUG_ON(alt->alt_len != 0);
165 else
166 BUG_ON(alt->alt_len != alt->orig_len);
167
168 pr_info_once("patching kernel code\n");
169
170 origptr = ALT_ORIG_PTR(alt);
171 updptr = is_module ? origptr : lm_alias(origptr);
172 nr_inst = alt->orig_len / AARCH64_INSN_SIZE;
173
174 if (alt->cpufeature < ARM64_CB_PATCH)
175 alt_cb = patch_alternative;
176 else
177 alt_cb = ALT_REPL_PTR(alt);
178
179 alt_cb(alt, origptr, updptr, nr_inst);
180
181 if (!is_module) {
182 clean_dcache_range_nopatch((u64)origptr,
183 (u64)(origptr + nr_inst));
184 }
185 }
186
187 /*
188 * The core module code takes care of cache maintenance in
189 * flush_module_icache().
190 */
191 if (!is_module) {
192 dsb(ish);
193 __flush_icache_all();
194 isb();
195 }
196 }
197
198 /*
199 * We might be patching the stop_machine state machine, so implement a
200 * really simple polling protocol here.
201 */
__apply_alternatives_multi_stop(void * unused)202 static int __apply_alternatives_multi_stop(void *unused)
203 {
204 struct alt_region region = {
205 .begin = (struct alt_instr *)__alt_instructions,
206 .end = (struct alt_instr *)__alt_instructions_end,
207 };
208
209 /* We always have a CPU 0 at this point (__init) */
210 if (smp_processor_id()) {
211 while (!READ_ONCE(alternatives_applied))
212 cpu_relax();
213 isb();
214 } else {
215 BUG_ON(alternatives_applied);
216 __apply_alternatives(®ion, false);
217 /* Barriers provided by the cache flushing */
218 WRITE_ONCE(alternatives_applied, 1);
219 }
220
221 return 0;
222 }
223
apply_alternatives_all(void)224 void __init apply_alternatives_all(void)
225 {
226 /* better not try code patching on a live SMP system */
227 stop_machine(__apply_alternatives_multi_stop, NULL, cpu_online_mask);
228 }
229
230 #ifdef CONFIG_MODULES
apply_alternatives_module(void * start,size_t length)231 void apply_alternatives_module(void *start, size_t length)
232 {
233 struct alt_region region = {
234 .begin = start,
235 .end = start + length,
236 };
237
238 __apply_alternatives(®ion, true);
239 }
240 #endif
241
