1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2003-2015, 2018-2021 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #ifndef __iwl_trans_int_pcie_h__
8 #define __iwl_trans_int_pcie_h__
9
10 #include <linux/spinlock.h>
11 #include <linux/interrupt.h>
12 #include <linux/skbuff.h>
13 #include <linux/wait.h>
14 #include <linux/pci.h>
15 #include <linux/timer.h>
16 #include <linux/cpu.h>
17
18 #include "iwl-fh.h"
19 #include "iwl-csr.h"
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
22 #include "iwl-io.h"
23 #include "iwl-op-mode.h"
24 #include "iwl-drv.h"
25 #include "queue/tx.h"
26
27 /*
28 * RX related structures and functions
29 */
30 #define RX_NUM_QUEUES 1
31 #define RX_POST_REQ_ALLOC 2
32 #define RX_CLAIM_REQ_ALLOC 8
33 #define RX_PENDING_WATERMARK 16
34 #define FIRST_RX_QUEUE 512
35
36 struct iwl_host_cmd;
37
38 /*This file includes the declaration that are internal to the
39 * trans_pcie layer */
40
41 /**
42 * struct iwl_rx_mem_buffer
43 * @page_dma: bus address of rxb page
44 * @page: driver's pointer to the rxb page
45 * @list: list entry for the membuffer
46 * @invalid: rxb is in driver ownership - not owned by HW
47 * @vid: index of this rxb in the global table
48 * @offset: indicates which offset of the page (in bytes)
49 * this buffer uses (if multiple RBs fit into one page)
50 */
51 struct iwl_rx_mem_buffer {
52 dma_addr_t page_dma;
53 struct page *page;
54 struct list_head list;
55 u32 offset;
56 u16 vid;
57 bool invalid;
58 };
59
60 /**
61 * struct isr_statistics - interrupt statistics
62 *
63 */
64 struct isr_statistics {
65 u32 hw;
66 u32 sw;
67 u32 err_code;
68 u32 sch;
69 u32 alive;
70 u32 rfkill;
71 u32 ctkill;
72 u32 wakeup;
73 u32 rx;
74 u32 tx;
75 u32 unhandled;
76 };
77
78 /**
79 * struct iwl_rx_transfer_desc - transfer descriptor
80 * @addr: ptr to free buffer start address
81 * @rbid: unique tag of the buffer
82 * @reserved: reserved
83 */
84 struct iwl_rx_transfer_desc {
85 __le16 rbid;
86 __le16 reserved[3];
87 __le64 addr;
88 } __packed;
89
90 #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0)
91
92 /**
93 * struct iwl_rx_completion_desc - completion descriptor
94 * @reserved1: reserved
95 * @rbid: unique tag of the received buffer
96 * @flags: flags (0: fragmented, all others: reserved)
97 * @reserved2: reserved
98 */
99 struct iwl_rx_completion_desc {
100 __le32 reserved1;
101 __le16 rbid;
102 u8 flags;
103 u8 reserved2[25];
104 } __packed;
105
106 /**
107 * struct iwl_rxq - Rx queue
108 * @id: queue index
109 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
110 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
111 * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's
112 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
113 * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd)
114 * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd)
115 * @read: Shared index to newest available Rx buffer
116 * @write: Shared index to oldest written Rx packet
117 * @free_count: Number of pre-allocated buffers in rx_free
118 * @used_count: Number of RBDs handled to allocator to use for allocation
119 * @write_actual:
120 * @rx_free: list of RBDs with allocated RB ready for use
121 * @rx_used: list of RBDs with no RB attached
122 * @need_update: flag to indicate we need to update read/write index
123 * @rb_stts: driver's pointer to receive buffer status
124 * @rb_stts_dma: bus address of receive buffer status
125 * @lock:
126 * @queue: actual rx queue. Not used for multi-rx queue.
127 * @next_rb_is_fragment: indicates that the previous RB that we handled set
128 * the fragmented flag, so the next one is still another fragment
129 *
130 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
131 */
132 struct iwl_rxq {
133 int id;
134 void *bd;
135 dma_addr_t bd_dma;
136 union {
137 void *used_bd;
138 __le32 *bd_32;
139 struct iwl_rx_completion_desc *cd;
140 };
141 dma_addr_t used_bd_dma;
142 u32 read;
143 u32 write;
144 u32 free_count;
145 u32 used_count;
146 u32 write_actual;
147 u32 queue_size;
148 struct list_head rx_free;
149 struct list_head rx_used;
150 bool need_update, next_rb_is_fragment;
151 void *rb_stts;
152 dma_addr_t rb_stts_dma;
153 spinlock_t lock;
154 struct napi_struct napi;
155 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
156 };
157
158 /**
159 * struct iwl_rb_allocator - Rx allocator
160 * @req_pending: number of requests the allcator had not processed yet
161 * @req_ready: number of requests honored and ready for claiming
162 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
163 * the queue. This is a list of &struct iwl_rx_mem_buffer
164 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
165 * of &struct iwl_rx_mem_buffer
166 * @lock: protects the rbd_allocated and rbd_empty lists
167 * @alloc_wq: work queue for background calls
168 * @rx_alloc: work struct for background calls
169 */
170 struct iwl_rb_allocator {
171 atomic_t req_pending;
172 atomic_t req_ready;
173 struct list_head rbd_allocated;
174 struct list_head rbd_empty;
175 spinlock_t lock;
176 struct workqueue_struct *alloc_wq;
177 struct work_struct rx_alloc;
178 };
179
180 /**
181 * iwl_get_closed_rb_stts - get closed rb stts from different structs
182 * @rxq - the rxq to get the rb stts from
183 */
iwl_get_closed_rb_stts(struct iwl_trans * trans,struct iwl_rxq * rxq)184 static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
185 struct iwl_rxq *rxq)
186 {
187 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
188 __le16 *rb_stts = rxq->rb_stts;
189
190 return READ_ONCE(*rb_stts);
191 } else {
192 struct iwl_rb_status *rb_stts = rxq->rb_stts;
193
194 return READ_ONCE(rb_stts->closed_rb_num);
195 }
196 }
197
198 #ifdef CONFIG_IWLWIFI_DEBUGFS
199 /**
200 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
201 * debugfs file
202 *
203 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
204 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
205 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
206 * set the file can no longer be used.
207 */
208 enum iwl_fw_mon_dbgfs_state {
209 IWL_FW_MON_DBGFS_STATE_CLOSED,
210 IWL_FW_MON_DBGFS_STATE_OPEN,
211 IWL_FW_MON_DBGFS_STATE_DISABLED,
212 };
213 #endif
214
215 /**
216 * enum iwl_shared_irq_flags - level of sharing for irq
217 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
218 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
219 */
220 enum iwl_shared_irq_flags {
221 IWL_SHARED_IRQ_NON_RX = BIT(0),
222 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
223 };
224
225 /**
226 * enum iwl_image_response_code - image response values
227 * @IWL_IMAGE_RESP_DEF: the default value of the register
228 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
229 * @IWL_IMAGE_RESP_FAIL: iml reading failed
230 */
231 enum iwl_image_response_code {
232 IWL_IMAGE_RESP_DEF = 0,
233 IWL_IMAGE_RESP_SUCCESS = 1,
234 IWL_IMAGE_RESP_FAIL = 2,
235 };
236
237 /**
238 * struct cont_rec: continuous recording data structure
239 * @prev_wr_ptr: the last address that was read in monitor_data
240 * debugfs file
241 * @prev_wrap_cnt: the wrap count that was used during the last read in
242 * monitor_data debugfs file
243 * @state: the state of monitor_data debugfs file as described
244 * in &iwl_fw_mon_dbgfs_state enum
245 * @mutex: locked while reading from monitor_data debugfs file
246 */
247 #ifdef CONFIG_IWLWIFI_DEBUGFS
248 struct cont_rec {
249 u32 prev_wr_ptr;
250 u32 prev_wrap_cnt;
251 u8 state;
252 /* Used to sync monitor_data debugfs file with driver unload flow */
253 struct mutex mutex;
254 };
255 #endif
256
257 enum iwl_pcie_fw_reset_state {
258 FW_RESET_IDLE,
259 FW_RESET_REQUESTED,
260 FW_RESET_OK,
261 FW_RESET_ERROR,
262 };
263
264 /**
265 * struct iwl_trans_pcie - PCIe transport specific data
266 * @rxq: all the RX queue data
267 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
268 * @global_table: table mapping received VID from hw to rxb
269 * @rba: allocator for RX replenishing
270 * @ctxt_info: context information for FW self init
271 * @ctxt_info_gen3: context information for gen3 devices
272 * @prph_info: prph info for self init
273 * @prph_scratch: prph scratch for self init
274 * @ctxt_info_dma_addr: dma addr of context information
275 * @prph_info_dma_addr: dma addr of prph info
276 * @prph_scratch_dma_addr: dma addr of prph scratch
277 * @ctxt_info_dma_addr: dma addr of context information
278 * @init_dram: DRAM data of firmware image (including paging).
279 * Context information addresses will be taken from here.
280 * This is driver's local copy for keeping track of size and
281 * count for allocating and freeing the memory.
282 * @iml: image loader image virtual address
283 * @iml_dma_addr: image loader image DMA address
284 * @trans: pointer to the generic transport area
285 * @scd_base_addr: scheduler sram base address in SRAM
286 * @kw: keep warm address
287 * @pnvm_dram: DRAM area that contains the PNVM data
288 * @pci_dev: basic pci-network driver stuff
289 * @hw_base: pci hardware address support
290 * @ucode_write_complete: indicates that the ucode has been copied.
291 * @ucode_write_waitq: wait queue for uCode load
292 * @cmd_queue - command queue number
293 * @def_rx_queue - default rx queue number
294 * @rx_buf_size: Rx buffer size
295 * @scd_set_active: should the transport configure the SCD for HCMD queue
296 * @rx_page_order: page order for receive buffer size
297 * @rx_buf_bytes: RX buffer (RB) size in bytes
298 * @reg_lock: protect hw register access
299 * @mutex: to protect stop_device / start_fw / start_hw
300 * @cmd_in_flight: true when we have a host command in flight
301 #ifdef CONFIG_IWLWIFI_DEBUGFS
302 * @fw_mon_data: fw continuous recording data
303 #endif
304 * @msix_entries: array of MSI-X entries
305 * @msix_enabled: true if managed to enable MSI-X
306 * @shared_vec_mask: the type of causes the shared vector handles
307 * (see iwl_shared_irq_flags).
308 * @alloc_vecs: the number of interrupt vectors allocated by the OS
309 * @def_irq: default irq for non rx causes
310 * @fh_init_mask: initial unmasked fh causes
311 * @hw_init_mask: initial unmasked hw causes
312 * @fh_mask: current unmasked fh causes
313 * @hw_mask: current unmasked hw causes
314 * @in_rescan: true if we have triggered a device rescan
315 * @base_rb_stts: base virtual address of receive buffer status for all queues
316 * @base_rb_stts_dma: base physical address of receive buffer status
317 * @supported_dma_mask: DMA mask to validate the actual address against,
318 * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device
319 * @alloc_page_lock: spinlock for the page allocator
320 * @alloc_page: allocated page to still use parts of
321 * @alloc_page_used: how much of the allocated page was already used (bytes)
322 * @rf_name: name/version of the CRF, if any
323 */
324 struct iwl_trans_pcie {
325 struct iwl_rxq *rxq;
326 struct iwl_rx_mem_buffer *rx_pool;
327 struct iwl_rx_mem_buffer **global_table;
328 struct iwl_rb_allocator rba;
329 union {
330 struct iwl_context_info *ctxt_info;
331 struct iwl_context_info_gen3 *ctxt_info_gen3;
332 };
333 struct iwl_prph_info *prph_info;
334 struct iwl_prph_scratch *prph_scratch;
335 void *iml;
336 dma_addr_t ctxt_info_dma_addr;
337 dma_addr_t prph_info_dma_addr;
338 dma_addr_t prph_scratch_dma_addr;
339 dma_addr_t iml_dma_addr;
340 struct iwl_trans *trans;
341
342 struct net_device napi_dev;
343
344 /* INT ICT Table */
345 __le32 *ict_tbl;
346 dma_addr_t ict_tbl_dma;
347 int ict_index;
348 bool use_ict;
349 bool is_down, opmode_down;
350 s8 debug_rfkill;
351 struct isr_statistics isr_stats;
352
353 spinlock_t irq_lock;
354 struct mutex mutex;
355 u32 inta_mask;
356 u32 scd_base_addr;
357 struct iwl_dma_ptr kw;
358
359 struct iwl_dram_data pnvm_dram;
360 struct iwl_dram_data reduce_power_dram;
361
362 struct iwl_txq *txq_memory;
363
364 /* PCI bus related data */
365 struct pci_dev *pci_dev;
366 void __iomem *hw_base;
367
368 bool ucode_write_complete;
369 bool sx_complete;
370 wait_queue_head_t ucode_write_waitq;
371 wait_queue_head_t sx_waitq;
372
373 u8 def_rx_queue;
374 u8 n_no_reclaim_cmds;
375 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
376 u16 num_rx_bufs;
377
378 enum iwl_amsdu_size rx_buf_size;
379 bool scd_set_active;
380 bool pcie_dbg_dumped_once;
381 u32 rx_page_order;
382 u32 rx_buf_bytes;
383 u32 supported_dma_mask;
384
385 /* allocator lock for the two values below */
386 spinlock_t alloc_page_lock;
387 struct page *alloc_page;
388 u32 alloc_page_used;
389
390 /*protect hw register */
391 spinlock_t reg_lock;
392 bool cmd_hold_nic_awake;
393
394 #ifdef CONFIG_IWLWIFI_DEBUGFS
395 struct cont_rec fw_mon_data;
396 #endif
397
398 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
399 bool msix_enabled;
400 u8 shared_vec_mask;
401 u32 alloc_vecs;
402 u32 def_irq;
403 u32 fh_init_mask;
404 u32 hw_init_mask;
405 u32 fh_mask;
406 u32 hw_mask;
407 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
408 u16 tx_cmd_queue_size;
409 bool in_rescan;
410
411 void *base_rb_stts;
412 dma_addr_t base_rb_stts_dma;
413
414 bool fw_reset_handshake;
415 enum iwl_pcie_fw_reset_state fw_reset_state;
416 wait_queue_head_t fw_reset_waitq;
417
418 char rf_name[32];
419 };
420
421 static inline struct iwl_trans_pcie *
IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans * trans)422 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
423 {
424 return (void *)trans->trans_specific;
425 }
426
iwl_pcie_clear_irq(struct iwl_trans * trans,int queue)427 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
428 {
429 /*
430 * Before sending the interrupt the HW disables it to prevent
431 * a nested interrupt. This is done by writing 1 to the corresponding
432 * bit in the mask register. After handling the interrupt, it should be
433 * re-enabled by clearing this bit. This register is defined as
434 * write 1 clear (W1C) register, meaning that it's being clear
435 * by writing 1 to the bit.
436 */
437 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
438 }
439
440 static inline struct iwl_trans *
iwl_trans_pcie_get_trans(struct iwl_trans_pcie * trans_pcie)441 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
442 {
443 return container_of((void *)trans_pcie, struct iwl_trans,
444 trans_specific);
445 }
446
447 /*
448 * Convention: trans API functions: iwl_trans_pcie_XXX
449 * Other functions: iwl_pcie_XXX
450 */
451 struct iwl_trans
452 *iwl_trans_pcie_alloc(struct pci_dev *pdev,
453 const struct pci_device_id *ent,
454 const struct iwl_cfg_trans_params *cfg_trans);
455 void iwl_trans_pcie_free(struct iwl_trans *trans);
456
457 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
458 #define _iwl_trans_pcie_grab_nic_access(trans) \
459 __cond_lock(nic_access_nobh, \
460 likely(__iwl_trans_pcie_grab_nic_access(trans)))
461
462 /*****************************************************
463 * RX
464 ******************************************************/
465 int iwl_pcie_rx_init(struct iwl_trans *trans);
466 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
467 irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
468 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
469 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
470 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
471 int iwl_pcie_rx_stop(struct iwl_trans *trans);
472 void iwl_pcie_rx_free(struct iwl_trans *trans);
473 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
474 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
475 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
476 struct iwl_rxq *rxq);
477
478 /*****************************************************
479 * ICT - interrupt handling
480 ******************************************************/
481 irqreturn_t iwl_pcie_isr(int irq, void *data);
482 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
483 void iwl_pcie_free_ict(struct iwl_trans *trans);
484 void iwl_pcie_reset_ict(struct iwl_trans *trans);
485 void iwl_pcie_disable_ict(struct iwl_trans *trans);
486
487 /*****************************************************
488 * TX / HCMD
489 ******************************************************/
490 int iwl_pcie_tx_init(struct iwl_trans *trans);
491 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
492 int iwl_pcie_tx_stop(struct iwl_trans *trans);
493 void iwl_pcie_tx_free(struct iwl_trans *trans);
494 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
495 const struct iwl_trans_txq_scd_cfg *cfg,
496 unsigned int wdg_timeout);
497 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
498 bool configure_scd);
499 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
500 bool shared_mode);
501 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
502 struct iwl_device_tx_cmd *dev_cmd, int txq_id);
503 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
504 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
505 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
506 struct iwl_rx_cmd_buffer *rxb);
507 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
508
509 /*****************************************************
510 * Error handling
511 ******************************************************/
512 void iwl_pcie_dump_csr(struct iwl_trans *trans);
513
514 /*****************************************************
515 * Helpers
516 ******************************************************/
_iwl_disable_interrupts(struct iwl_trans * trans)517 static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
518 {
519 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
520
521 clear_bit(STATUS_INT_ENABLED, &trans->status);
522 if (!trans_pcie->msix_enabled) {
523 /* disable interrupts from uCode/NIC to host */
524 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
525
526 /* acknowledge/clear/reset any interrupts still pending
527 * from uCode or flow handler (Rx/Tx DMA) */
528 iwl_write32(trans, CSR_INT, 0xffffffff);
529 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
530 } else {
531 /* disable all the interrupt we might use */
532 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
533 trans_pcie->fh_init_mask);
534 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
535 trans_pcie->hw_init_mask);
536 }
537 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
538 }
539
iwl_pcie_get_num_sections(const struct fw_img * fw,int start)540 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
541 int start)
542 {
543 int i = 0;
544
545 while (start < fw->num_sec &&
546 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
547 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
548 start++;
549 i++;
550 }
551
552 return i;
553 }
554
iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans * trans)555 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
556 {
557 struct iwl_self_init_dram *dram = &trans->init_dram;
558 int i;
559
560 if (!dram->fw) {
561 WARN_ON(dram->fw_cnt);
562 return;
563 }
564
565 for (i = 0; i < dram->fw_cnt; i++)
566 dma_free_coherent(trans->dev, dram->fw[i].size,
567 dram->fw[i].block, dram->fw[i].physical);
568
569 kfree(dram->fw);
570 dram->fw_cnt = 0;
571 dram->fw = NULL;
572 }
573
iwl_disable_interrupts(struct iwl_trans * trans)574 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
575 {
576 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
577
578 spin_lock_bh(&trans_pcie->irq_lock);
579 _iwl_disable_interrupts(trans);
580 spin_unlock_bh(&trans_pcie->irq_lock);
581 }
582
_iwl_enable_interrupts(struct iwl_trans * trans)583 static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
584 {
585 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
586
587 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
588 set_bit(STATUS_INT_ENABLED, &trans->status);
589 if (!trans_pcie->msix_enabled) {
590 trans_pcie->inta_mask = CSR_INI_SET_MASK;
591 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
592 } else {
593 /*
594 * fh/hw_mask keeps all the unmasked causes.
595 * Unlike msi, in msix cause is enabled when it is unset.
596 */
597 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
598 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
599 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
600 ~trans_pcie->fh_mask);
601 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
602 ~trans_pcie->hw_mask);
603 }
604 }
605
iwl_enable_interrupts(struct iwl_trans * trans)606 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
607 {
608 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
609
610 spin_lock_bh(&trans_pcie->irq_lock);
611 _iwl_enable_interrupts(trans);
612 spin_unlock_bh(&trans_pcie->irq_lock);
613 }
iwl_enable_hw_int_msk_msix(struct iwl_trans * trans,u32 msk)614 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
615 {
616 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
617
618 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
619 trans_pcie->hw_mask = msk;
620 }
621
iwl_enable_fh_int_msk_msix(struct iwl_trans * trans,u32 msk)622 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
623 {
624 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
625
626 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
627 trans_pcie->fh_mask = msk;
628 }
629
iwl_enable_fw_load_int(struct iwl_trans * trans)630 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
631 {
632 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
633
634 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
635 if (!trans_pcie->msix_enabled) {
636 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
637 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
638 } else {
639 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
640 trans_pcie->hw_init_mask);
641 iwl_enable_fh_int_msk_msix(trans,
642 MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
643 }
644 }
645
iwl_enable_fw_load_int_ctx_info(struct iwl_trans * trans)646 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
647 {
648 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
649
650 IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
651
652 if (!trans_pcie->msix_enabled) {
653 /*
654 * When we'll receive the ALIVE interrupt, the ISR will call
655 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE
656 * interrupt (which is not really needed anymore) but also the
657 * RX interrupt which will allow us to receive the ALIVE
658 * notification (which is Rx) and continue the flow.
659 */
660 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX;
661 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
662 } else {
663 iwl_enable_hw_int_msk_msix(trans,
664 MSIX_HW_INT_CAUSES_REG_ALIVE);
665 /*
666 * Leave all the FH causes enabled to get the ALIVE
667 * notification.
668 */
669 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
670 }
671 }
672
queue_name(struct device * dev,struct iwl_trans_pcie * trans_p,int i)673 static inline const char *queue_name(struct device *dev,
674 struct iwl_trans_pcie *trans_p, int i)
675 {
676 if (trans_p->shared_vec_mask) {
677 int vec = trans_p->shared_vec_mask &
678 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
679
680 if (i == 0)
681 return DRV_NAME ":shared_IRQ";
682
683 return devm_kasprintf(dev, GFP_KERNEL,
684 DRV_NAME ":queue_%d", i + vec);
685 }
686 if (i == 0)
687 return DRV_NAME ":default_queue";
688
689 if (i == trans_p->alloc_vecs - 1)
690 return DRV_NAME ":exception";
691
692 return devm_kasprintf(dev, GFP_KERNEL,
693 DRV_NAME ":queue_%d", i);
694 }
695
iwl_enable_rfkill_int(struct iwl_trans * trans)696 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
697 {
698 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
699
700 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
701 if (!trans_pcie->msix_enabled) {
702 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
703 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
704 } else {
705 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
706 trans_pcie->fh_init_mask);
707 iwl_enable_hw_int_msk_msix(trans,
708 MSIX_HW_INT_CAUSES_REG_RF_KILL);
709 }
710
711 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
712 /*
713 * On 9000-series devices this bit isn't enabled by default, so
714 * when we power down the device we need set the bit to allow it
715 * to wake up the PCI-E bus for RF-kill interrupts.
716 */
717 iwl_set_bit(trans, CSR_GP_CNTRL,
718 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
719 }
720 }
721
722 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans);
723
iwl_is_rfkill_set(struct iwl_trans * trans)724 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
725 {
726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727
728 lockdep_assert_held(&trans_pcie->mutex);
729
730 if (trans_pcie->debug_rfkill == 1)
731 return true;
732
733 return !(iwl_read32(trans, CSR_GP_CNTRL) &
734 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
735 }
736
__iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)737 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
738 u32 reg, u32 mask, u32 value)
739 {
740 u32 v;
741
742 #ifdef CONFIG_IWLWIFI_DEBUG
743 WARN_ON_ONCE(value & ~mask);
744 #endif
745
746 v = iwl_read32(trans, reg);
747 v &= ~mask;
748 v |= value;
749 iwl_write32(trans, reg, v);
750 }
751
__iwl_trans_pcie_clear_bit(struct iwl_trans * trans,u32 reg,u32 mask)752 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
753 u32 reg, u32 mask)
754 {
755 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
756 }
757
__iwl_trans_pcie_set_bit(struct iwl_trans * trans,u32 reg,u32 mask)758 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
759 u32 reg, u32 mask)
760 {
761 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
762 }
763
iwl_pcie_dbg_on(struct iwl_trans * trans)764 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
765 {
766 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
767 }
768
769 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
770 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
771
772 #ifdef CONFIG_IWLWIFI_DEBUGFS
773 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
774 #else
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans)775 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
776 #endif
777
778 void iwl_pcie_rx_allocator_work(struct work_struct *data);
779
780 /* common functions that are used by gen2 transport */
781 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
782 void iwl_pcie_apm_config(struct iwl_trans *trans);
783 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
784 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
785 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
786 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
787 bool was_in_rfkill);
788 void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
789 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
790 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
791 struct iwl_dma_ptr *ptr, size_t size);
792 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
793 void iwl_pcie_apply_destination(struct iwl_trans *trans);
794
795 /* common functions that are used by gen3 transport */
796 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
797
798 /* transport gen 2 exported functions */
799 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
800 const struct fw_img *fw, bool run_in_rfkill);
801 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
802 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
803 struct iwl_host_cmd *cmd);
804 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
805 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
806 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
807 bool test, bool reset);
808 int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
809 struct iwl_host_cmd *cmd);
810 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
811 struct iwl_host_cmd *cmd);
812 #endif /* __iwl_trans_int_pcie_h__ */
813
