1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * linux/sound/soc/codecs/tlv320aic32x4.c
4 *
5 * Copyright 2011 Vista Silicon S.L.
6 *
7 * Author: Javier Martin <javier.martin@vista-silicon.com>
8 *
9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/gpio.h>
18 #include <linux/of_gpio.h>
19 #include <linux/cdev.h>
20 #include <linux/slab.h>
21 #include <linux/clk.h>
22 #include <linux/of_clk.h>
23 #include <linux/regulator/consumer.h>
24
25 #include <sound/tlv320aic32x4.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33
34 #include "tlv320aic32x4.h"
35
36 struct aic32x4_priv {
37 struct regmap *regmap;
38 u32 power_cfg;
39 u32 micpga_routing;
40 bool swapdacs;
41 int rstn_gpio;
42 const char *mclk_name;
43
44 struct regulator *supply_ldo;
45 struct regulator *supply_iov;
46 struct regulator *supply_dv;
47 struct regulator *supply_av;
48
49 struct aic32x4_setup_data *setup;
50 struct device *dev;
51 };
52
aic32x4_reset_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)53 static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
54 struct snd_kcontrol *kcontrol, int event)
55 {
56 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
57 u32 adc_reg;
58
59 /*
60 * Workaround: the datasheet does not mention a required programming
61 * sequence but experiments show the ADC needs to be reset after each
62 * capture to avoid audible artifacts.
63 */
64 switch (event) {
65 case SND_SOC_DAPM_POST_PMD:
66 adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
67 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
68 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
69 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
70 break;
71 }
72 return 0;
73 };
74
mic_bias_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)75 static int mic_bias_event(struct snd_soc_dapm_widget *w,
76 struct snd_kcontrol *kcontrol, int event)
77 {
78 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
79
80 switch (event) {
81 case SND_SOC_DAPM_POST_PMU:
82 /* Change Mic Bias Registor */
83 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
84 AIC32x4_MICBIAS_MASK,
85 AIC32X4_MICBIAS_LDOIN |
86 AIC32X4_MICBIAS_2075V);
87 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
88 break;
89 case SND_SOC_DAPM_PRE_PMD:
90 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
91 AIC32x4_MICBIAS_MASK, 0);
92 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
93 __func__);
94 break;
95 }
96
97 return 0;
98 }
99
100
aic32x4_get_mfp1_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)101 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
102 struct snd_ctl_elem_value *ucontrol)
103 {
104 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
105 u8 val;
106
107 val = snd_soc_component_read(component, AIC32X4_DINCTL);
108
109 ucontrol->value.integer.value[0] = (val & 0x01);
110
111 return 0;
112 };
113
aic32x4_set_mfp2_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)114 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
115 struct snd_ctl_elem_value *ucontrol)
116 {
117 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
118 u8 val;
119 u8 gpio_check;
120
121 val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
122 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
123 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
124 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
125 __func__);
126 return -EINVAL;
127 }
128
129 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
130 return 0;
131
132 if (ucontrol->value.integer.value[0])
133 val |= ucontrol->value.integer.value[0];
134 else
135 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
136
137 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
138
139 return 0;
140 };
141
aic32x4_get_mfp3_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)142 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
143 struct snd_ctl_elem_value *ucontrol)
144 {
145 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
146 u8 val;
147
148 val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
149
150 ucontrol->value.integer.value[0] = (val & 0x01);
151
152 return 0;
153 };
154
aic32x4_set_mfp4_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)155 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
156 struct snd_ctl_elem_value *ucontrol)
157 {
158 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
159 u8 val;
160 u8 gpio_check;
161
162 val = snd_soc_component_read(component, AIC32X4_MISOCTL);
163 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
164 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
165 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
166 __func__);
167 return -EINVAL;
168 }
169
170 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
171 return 0;
172
173 if (ucontrol->value.integer.value[0])
174 val |= ucontrol->value.integer.value[0];
175 else
176 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
177
178 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
179
180 return 0;
181 };
182
aic32x4_get_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)183 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
184 struct snd_ctl_elem_value *ucontrol)
185 {
186 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
187 u8 val;
188
189 val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
190 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
191
192 return 0;
193 };
194
aic32x4_set_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)195 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
196 struct snd_ctl_elem_value *ucontrol)
197 {
198 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
199 u8 val;
200 u8 gpio_check;
201
202 val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
203 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
204 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
205 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
206 __func__);
207 return -EINVAL;
208 }
209
210 if (ucontrol->value.integer.value[0] == (val & 0x1))
211 return 0;
212
213 if (ucontrol->value.integer.value[0])
214 val |= ucontrol->value.integer.value[0];
215 else
216 val &= 0xfe;
217
218 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
219
220 return 0;
221 };
222
223 static const struct snd_kcontrol_new aic32x4_mfp1[] = {
224 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
225 };
226
227 static const struct snd_kcontrol_new aic32x4_mfp2[] = {
228 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
229 };
230
231 static const struct snd_kcontrol_new aic32x4_mfp3[] = {
232 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
233 };
234
235 static const struct snd_kcontrol_new aic32x4_mfp4[] = {
236 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
237 };
238
239 static const struct snd_kcontrol_new aic32x4_mfp5[] = {
240 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
241 aic32x4_set_mfp5_gpio),
242 };
243
244 /* 0dB min, 0.5dB steps */
245 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
246 /* -63.5dB min, 0.5dB steps */
247 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
248 /* -6dB min, 1dB steps */
249 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
250 /* -12dB min, 0.5dB steps */
251 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
252
253 static const char * const lo_cm_text[] = {
254 "Full Chip", "1.65V",
255 };
256
257 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
258
259 static const char * const ptm_text[] = {
260 "P3", "P2", "P1",
261 };
262
263 static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
264 static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
265
266 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
267 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
268 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
269 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
270 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
271 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
272 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
273 tlv_driver_gain),
274 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
275 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
276 tlv_driver_gain),
277 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
278 AIC32X4_HPRGAIN, 6, 0x01, 1),
279 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
280 AIC32X4_LORGAIN, 6, 0x01, 1),
281 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
282 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
283 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
284
285 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
286 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
287
288 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
289 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
290 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
291 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
292
293 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
294
295 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
296 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
297 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
298 4, 0x07, 0),
299 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
300 0, 0x03, 0),
301 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
302 6, 0x03, 0),
303 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
304 1, 0x1F, 0),
305 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
306 0, 0x7F, 0),
307 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
308 3, 0x1F, 0),
309 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
310 3, 0x1F, 0),
311 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
312 0, 0x1F, 0),
313 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
314 0, 0x0F, 0),
315 };
316
317 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
318 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
319 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
320 };
321
322 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
323 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
324 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
325 };
326
327 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
328 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
329 };
330
331 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
332 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
333 };
334
335 static const char * const resistor_text[] = {
336 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
337 };
338
339 /* Left mixer pins */
340 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
341 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
342 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
343 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
344
345 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
346 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
347 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
348
349 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
350 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
351 };
352 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
353 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
354 };
355 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
356 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
357 };
358 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
359 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
360 };
361 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
362 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
363 };
364 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
365 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
366 };
367 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
368 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
369 };
370
371 /* Right mixer pins */
372 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
373 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
374 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
375 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
376 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
377 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
378 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
379
380 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
381 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
382 };
383 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
384 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
385 };
386 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
387 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
388 };
389 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
390 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
391 };
392 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
393 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
394 };
395 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
396 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
397 };
398 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
399 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
400 };
401
402 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
403 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
404 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
405 &hpl_output_mixer_controls[0],
406 ARRAY_SIZE(hpl_output_mixer_controls)),
407 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
408
409 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
410 &lol_output_mixer_controls[0],
411 ARRAY_SIZE(lol_output_mixer_controls)),
412 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
413
414 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
415 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
416 &hpr_output_mixer_controls[0],
417 ARRAY_SIZE(hpr_output_mixer_controls)),
418 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
419 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
420 &lor_output_mixer_controls[0],
421 ARRAY_SIZE(lor_output_mixer_controls)),
422 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
423
424 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
425 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
426 in1r_to_rmixer_controls),
427 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
428 in2r_to_rmixer_controls),
429 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
430 in3r_to_rmixer_controls),
431 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
432 in2l_to_rmixer_controls),
433 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
434 cmr_to_rmixer_controls),
435 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
436 in1l_to_rmixer_controls),
437 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
438 in3l_to_rmixer_controls),
439
440 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
441 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
442 in1l_to_lmixer_controls),
443 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
444 in2l_to_lmixer_controls),
445 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
446 in3l_to_lmixer_controls),
447 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
448 in1r_to_lmixer_controls),
449 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
450 cml_to_lmixer_controls),
451 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
452 in2r_to_lmixer_controls),
453 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
454 in3r_to_lmixer_controls),
455
456 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
457 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
458
459 SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
460
461 SND_SOC_DAPM_OUTPUT("HPL"),
462 SND_SOC_DAPM_OUTPUT("HPR"),
463 SND_SOC_DAPM_OUTPUT("LOL"),
464 SND_SOC_DAPM_OUTPUT("LOR"),
465 SND_SOC_DAPM_INPUT("IN1_L"),
466 SND_SOC_DAPM_INPUT("IN1_R"),
467 SND_SOC_DAPM_INPUT("IN2_L"),
468 SND_SOC_DAPM_INPUT("IN2_R"),
469 SND_SOC_DAPM_INPUT("IN3_L"),
470 SND_SOC_DAPM_INPUT("IN3_R"),
471 SND_SOC_DAPM_INPUT("CM_L"),
472 SND_SOC_DAPM_INPUT("CM_R"),
473 };
474
475 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
476 /* Left Output */
477 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
478 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
479
480 {"HPL Power", NULL, "HPL Output Mixer"},
481 {"HPL", NULL, "HPL Power"},
482
483 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
484
485 {"LOL Power", NULL, "LOL Output Mixer"},
486 {"LOL", NULL, "LOL Power"},
487
488 /* Right Output */
489 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
490 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
491
492 {"HPR Power", NULL, "HPR Output Mixer"},
493 {"HPR", NULL, "HPR Power"},
494
495 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
496
497 {"LOR Power", NULL, "LOR Output Mixer"},
498 {"LOR", NULL, "LOR Power"},
499
500 /* Right Input */
501 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
502 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
503 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
504 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
505
506 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
507 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
508 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
509 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
510
511 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
512 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
513 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
514 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
515
516 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
517 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
518 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
519 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
520
521 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
522 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
523 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
524 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
525
526 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
527 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
528 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
529 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
530
531 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
532 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
533 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
534 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
535
536 /* Left Input */
537 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
538 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
539 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
540 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
541
542 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
543 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
544 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
545 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
546
547 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
548 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
549 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
550 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
551
552 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
553 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
554 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
555 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
556
557 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
558 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
559 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
560 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
561
562 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
563 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
564 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
565 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
566
567 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
568 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
569 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
570 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
571 };
572
573 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
574 {
575 .selector_reg = 0,
576 .selector_mask = 0xff,
577 .window_start = 0,
578 .window_len = 128,
579 .range_min = 0,
580 .range_max = AIC32X4_RMICPGAVOL,
581 },
582 };
583
584 const struct regmap_config aic32x4_regmap_config = {
585 .max_register = AIC32X4_RMICPGAVOL,
586 .ranges = aic32x4_regmap_pages,
587 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
588 };
589 EXPORT_SYMBOL(aic32x4_regmap_config);
590
aic32x4_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)591 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
592 int clk_id, unsigned int freq, int dir)
593 {
594 struct snd_soc_component *component = codec_dai->component;
595 struct clk *mclk;
596 struct clk *pll;
597
598 pll = devm_clk_get(component->dev, "pll");
599 if (IS_ERR(pll))
600 return PTR_ERR(pll);
601
602 mclk = clk_get_parent(pll);
603
604 return clk_set_rate(mclk, freq);
605 }
606
aic32x4_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)607 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
608 {
609 struct snd_soc_component *component = codec_dai->component;
610 u8 iface_reg_1 = 0;
611 u8 iface_reg_2 = 0;
612 u8 iface_reg_3 = 0;
613
614 /* set master/slave audio interface */
615 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
616 case SND_SOC_DAIFMT_CBM_CFM:
617 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
618 break;
619 case SND_SOC_DAIFMT_CBS_CFS:
620 break;
621 default:
622 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
623 return -EINVAL;
624 }
625
626 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
627 case SND_SOC_DAIFMT_I2S:
628 break;
629 case SND_SOC_DAIFMT_DSP_A:
630 iface_reg_1 |= (AIC32X4_DSP_MODE <<
631 AIC32X4_IFACE1_DATATYPE_SHIFT);
632 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
633 iface_reg_2 = 0x01; /* add offset 1 */
634 break;
635 case SND_SOC_DAIFMT_DSP_B:
636 iface_reg_1 |= (AIC32X4_DSP_MODE <<
637 AIC32X4_IFACE1_DATATYPE_SHIFT);
638 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
639 break;
640 case SND_SOC_DAIFMT_RIGHT_J:
641 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
642 AIC32X4_IFACE1_DATATYPE_SHIFT);
643 break;
644 case SND_SOC_DAIFMT_LEFT_J:
645 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
646 AIC32X4_IFACE1_DATATYPE_SHIFT);
647 break;
648 default:
649 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
650 return -EINVAL;
651 }
652
653 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
654 AIC32X4_IFACE1_DATATYPE_MASK |
655 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
656 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
657 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
658 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
659 AIC32X4_BCLKINV_MASK, iface_reg_3);
660
661 return 0;
662 }
663
aic32x4_set_aosr(struct snd_soc_component * component,u8 aosr)664 static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
665 {
666 return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
667 }
668
aic32x4_set_dosr(struct snd_soc_component * component,u16 dosr)669 static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
670 {
671 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
672 snd_soc_component_write(component, AIC32X4_DOSRLSB,
673 (dosr & 0xff));
674
675 return 0;
676 }
677
aic32x4_set_processing_blocks(struct snd_soc_component * component,u8 r_block,u8 p_block)678 static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
679 u8 r_block, u8 p_block)
680 {
681 if (r_block > 18 || p_block > 25)
682 return -EINVAL;
683
684 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
685 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
686
687 return 0;
688 }
689
aic32x4_setup_clocks(struct snd_soc_component * component,unsigned int sample_rate,unsigned int channels,unsigned int bit_depth)690 static int aic32x4_setup_clocks(struct snd_soc_component *component,
691 unsigned int sample_rate, unsigned int channels,
692 unsigned int bit_depth)
693 {
694 u8 aosr;
695 u16 dosr;
696 u8 adc_resource_class, dac_resource_class;
697 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
698 u8 dosr_increment;
699 u16 max_dosr, min_dosr;
700 unsigned long adc_clock_rate, dac_clock_rate;
701 int ret;
702
703 struct clk_bulk_data clocks[] = {
704 { .id = "pll" },
705 { .id = "nadc" },
706 { .id = "madc" },
707 { .id = "ndac" },
708 { .id = "mdac" },
709 { .id = "bdiv" },
710 };
711 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
712 if (ret)
713 return ret;
714
715 if (sample_rate <= 48000) {
716 aosr = 128;
717 adc_resource_class = 6;
718 dac_resource_class = 8;
719 dosr_increment = 8;
720 aic32x4_set_processing_blocks(component, 1, 1);
721 } else if (sample_rate <= 96000) {
722 aosr = 64;
723 adc_resource_class = 6;
724 dac_resource_class = 8;
725 dosr_increment = 4;
726 aic32x4_set_processing_blocks(component, 1, 9);
727 } else if (sample_rate == 192000) {
728 aosr = 32;
729 adc_resource_class = 3;
730 dac_resource_class = 4;
731 dosr_increment = 2;
732 aic32x4_set_processing_blocks(component, 13, 19);
733 } else {
734 dev_err(component->dev, "Sampling rate not supported\n");
735 return -EINVAL;
736 }
737
738 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
739 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
740 dosr_increment;
741 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
742 dosr_increment;
743 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
744
745 for (nadc = max_nadc; nadc > 0; --nadc) {
746 adc_clock_rate = nadc * madc * aosr * sample_rate;
747 for (dosr = max_dosr; dosr >= min_dosr;
748 dosr -= dosr_increment) {
749 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
750 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
751 (min_mdac * dosr * sample_rate);
752 for (mdac = min_mdac; mdac <= 128; ++mdac) {
753 for (ndac = max_ndac; ndac > 0; --ndac) {
754 dac_clock_rate = ndac * mdac * dosr *
755 sample_rate;
756 if (dac_clock_rate == adc_clock_rate) {
757 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
758 continue;
759
760 clk_set_rate(clocks[0].clk,
761 dac_clock_rate);
762
763 clk_set_rate(clocks[1].clk,
764 sample_rate * aosr *
765 madc);
766 clk_set_rate(clocks[2].clk,
767 sample_rate * aosr);
768 aic32x4_set_aosr(component,
769 aosr);
770
771 clk_set_rate(clocks[3].clk,
772 sample_rate * dosr *
773 mdac);
774 clk_set_rate(clocks[4].clk,
775 sample_rate * dosr);
776 aic32x4_set_dosr(component,
777 dosr);
778
779 clk_set_rate(clocks[5].clk,
780 sample_rate * channels *
781 bit_depth);
782
783 return 0;
784 }
785 }
786 }
787 }
788 }
789
790 dev_err(component->dev,
791 "Could not set clocks to support sample rate.\n");
792 return -EINVAL;
793 }
794
aic32x4_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)795 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
796 struct snd_pcm_hw_params *params,
797 struct snd_soc_dai *dai)
798 {
799 struct snd_soc_component *component = dai->component;
800 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
801 u8 iface1_reg = 0;
802 u8 dacsetup_reg = 0;
803
804 aic32x4_setup_clocks(component, params_rate(params),
805 params_channels(params),
806 params_physical_width(params));
807
808 switch (params_physical_width(params)) {
809 case 16:
810 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
811 AIC32X4_IFACE1_DATALEN_SHIFT);
812 break;
813 case 20:
814 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
815 AIC32X4_IFACE1_DATALEN_SHIFT);
816 break;
817 case 24:
818 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
819 AIC32X4_IFACE1_DATALEN_SHIFT);
820 break;
821 case 32:
822 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
823 AIC32X4_IFACE1_DATALEN_SHIFT);
824 break;
825 }
826 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
827 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
828
829 if (params_channels(params) == 1) {
830 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
831 } else {
832 if (aic32x4->swapdacs)
833 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
834 else
835 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
836 }
837 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
838 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
839
840 return 0;
841 }
842
aic32x4_mute(struct snd_soc_dai * dai,int mute,int direction)843 static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
844 {
845 struct snd_soc_component *component = dai->component;
846
847 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
848 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
849
850 return 0;
851 }
852
aic32x4_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)853 static int aic32x4_set_bias_level(struct snd_soc_component *component,
854 enum snd_soc_bias_level level)
855 {
856 int ret;
857
858 struct clk_bulk_data clocks[] = {
859 { .id = "madc" },
860 { .id = "mdac" },
861 { .id = "bdiv" },
862 };
863
864 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
865 if (ret)
866 return ret;
867
868 switch (level) {
869 case SND_SOC_BIAS_ON:
870 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
871 if (ret) {
872 dev_err(component->dev, "Failed to enable clocks\n");
873 return ret;
874 }
875 break;
876 case SND_SOC_BIAS_PREPARE:
877 break;
878 case SND_SOC_BIAS_STANDBY:
879 /* Initial cold start */
880 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
881 break;
882
883 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
884 break;
885 case SND_SOC_BIAS_OFF:
886 break;
887 }
888 return 0;
889 }
890
891 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
892 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
893 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
894 | SNDRV_PCM_FMTBIT_S32_LE)
895
896 static const struct snd_soc_dai_ops aic32x4_ops = {
897 .hw_params = aic32x4_hw_params,
898 .mute_stream = aic32x4_mute,
899 .set_fmt = aic32x4_set_dai_fmt,
900 .set_sysclk = aic32x4_set_dai_sysclk,
901 .no_capture_mute = 1,
902 };
903
904 static struct snd_soc_dai_driver aic32x4_dai = {
905 .name = "tlv320aic32x4-hifi",
906 .playback = {
907 .stream_name = "Playback",
908 .channels_min = 1,
909 .channels_max = 2,
910 .rates = AIC32X4_RATES,
911 .formats = AIC32X4_FORMATS,},
912 .capture = {
913 .stream_name = "Capture",
914 .channels_min = 1,
915 .channels_max = 8,
916 .rates = AIC32X4_RATES,
917 .formats = AIC32X4_FORMATS,},
918 .ops = &aic32x4_ops,
919 .symmetric_rates = 1,
920 };
921
aic32x4_setup_gpios(struct snd_soc_component * component)922 static void aic32x4_setup_gpios(struct snd_soc_component *component)
923 {
924 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
925
926 /* setup GPIO functions */
927 /* MFP1 */
928 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
929 snd_soc_component_write(component, AIC32X4_DINCTL,
930 aic32x4->setup->gpio_func[0]);
931 snd_soc_add_component_controls(component, aic32x4_mfp1,
932 ARRAY_SIZE(aic32x4_mfp1));
933 }
934
935 /* MFP2 */
936 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
937 snd_soc_component_write(component, AIC32X4_DOUTCTL,
938 aic32x4->setup->gpio_func[1]);
939 snd_soc_add_component_controls(component, aic32x4_mfp2,
940 ARRAY_SIZE(aic32x4_mfp2));
941 }
942
943 /* MFP3 */
944 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
945 snd_soc_component_write(component, AIC32X4_SCLKCTL,
946 aic32x4->setup->gpio_func[2]);
947 snd_soc_add_component_controls(component, aic32x4_mfp3,
948 ARRAY_SIZE(aic32x4_mfp3));
949 }
950
951 /* MFP4 */
952 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
953 snd_soc_component_write(component, AIC32X4_MISOCTL,
954 aic32x4->setup->gpio_func[3]);
955 snd_soc_add_component_controls(component, aic32x4_mfp4,
956 ARRAY_SIZE(aic32x4_mfp4));
957 }
958
959 /* MFP5 */
960 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
961 snd_soc_component_write(component, AIC32X4_GPIOCTL,
962 aic32x4->setup->gpio_func[4]);
963 snd_soc_add_component_controls(component, aic32x4_mfp5,
964 ARRAY_SIZE(aic32x4_mfp5));
965 }
966 }
967
aic32x4_component_probe(struct snd_soc_component * component)968 static int aic32x4_component_probe(struct snd_soc_component *component)
969 {
970 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
971 u32 tmp_reg;
972 int ret;
973
974 struct clk_bulk_data clocks[] = {
975 { .id = "codec_clkin" },
976 { .id = "pll" },
977 { .id = "bdiv" },
978 { .id = "mdac" },
979 };
980
981 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
982 if (ret)
983 return ret;
984
985 if (aic32x4->setup)
986 aic32x4_setup_gpios(component);
987
988 clk_set_parent(clocks[0].clk, clocks[1].clk);
989 clk_set_parent(clocks[2].clk, clocks[3].clk);
990
991 /* Power platform configuration */
992 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
993 snd_soc_component_write(component, AIC32X4_MICBIAS,
994 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
995 }
996 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
997 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
998
999 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1000 AIC32X4_LDOCTLEN : 0;
1001 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1002
1003 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1004 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1005 tmp_reg |= AIC32X4_LDOIN_18_36;
1006 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1007 tmp_reg |= AIC32X4_LDOIN2HP;
1008 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1009
1010 /* Mic PGA routing */
1011 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1012 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1013 AIC32X4_LMICPGANIN_IN2R_10K);
1014 else
1015 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1016 AIC32X4_LMICPGANIN_CM1L_10K);
1017 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1018 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1019 AIC32X4_RMICPGANIN_IN1L_10K);
1020 else
1021 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1022 AIC32X4_RMICPGANIN_CM1R_10K);
1023
1024 /*
1025 * Workaround: for an unknown reason, the ADC needs to be powered up
1026 * and down for the first capture to work properly. It seems related to
1027 * a HW BUG or some kind of behavior not documented in the datasheet.
1028 */
1029 tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
1030 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1031 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1032 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1033
1034 /*
1035 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1036 * before using the analog circuits.
1037 */
1038 snd_soc_component_write(component, AIC32X4_REFPOWERUP,
1039 AIC32X4_REFPOWERUP_40MS);
1040 msleep(40);
1041
1042 return 0;
1043 }
1044
1045 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1046 .probe = aic32x4_component_probe,
1047 .set_bias_level = aic32x4_set_bias_level,
1048 .controls = aic32x4_snd_controls,
1049 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1050 .dapm_widgets = aic32x4_dapm_widgets,
1051 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1052 .dapm_routes = aic32x4_dapm_routes,
1053 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1054 .suspend_bias_off = 1,
1055 .idle_bias_on = 1,
1056 .use_pmdown_time = 1,
1057 .endianness = 1,
1058 .non_legacy_dai_naming = 1,
1059 };
1060
aic32x4_parse_dt(struct aic32x4_priv * aic32x4,struct device_node * np)1061 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1062 struct device_node *np)
1063 {
1064 struct aic32x4_setup_data *aic32x4_setup;
1065 int ret;
1066
1067 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1068 GFP_KERNEL);
1069 if (!aic32x4_setup)
1070 return -ENOMEM;
1071
1072 ret = of_property_match_string(np, "clock-names", "mclk");
1073 if (ret < 0)
1074 return -EINVAL;
1075 aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1076
1077 aic32x4->swapdacs = false;
1078 aic32x4->micpga_routing = 0;
1079 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1080
1081 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1082 aic32x4_setup->gpio_func, 5) >= 0)
1083 aic32x4->setup = aic32x4_setup;
1084 return 0;
1085 }
1086
aic32x4_disable_regulators(struct aic32x4_priv * aic32x4)1087 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1088 {
1089 regulator_disable(aic32x4->supply_iov);
1090
1091 if (!IS_ERR(aic32x4->supply_ldo))
1092 regulator_disable(aic32x4->supply_ldo);
1093
1094 if (!IS_ERR(aic32x4->supply_dv))
1095 regulator_disable(aic32x4->supply_dv);
1096
1097 if (!IS_ERR(aic32x4->supply_av))
1098 regulator_disable(aic32x4->supply_av);
1099 }
1100
aic32x4_setup_regulators(struct device * dev,struct aic32x4_priv * aic32x4)1101 static int aic32x4_setup_regulators(struct device *dev,
1102 struct aic32x4_priv *aic32x4)
1103 {
1104 int ret = 0;
1105
1106 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1107 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1108 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1109 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1110
1111 /* Check if the regulator requirements are fulfilled */
1112
1113 if (IS_ERR(aic32x4->supply_iov)) {
1114 dev_err(dev, "Missing supply 'iov'\n");
1115 return PTR_ERR(aic32x4->supply_iov);
1116 }
1117
1118 if (IS_ERR(aic32x4->supply_ldo)) {
1119 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1120 return -EPROBE_DEFER;
1121
1122 if (IS_ERR(aic32x4->supply_dv)) {
1123 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1124 return PTR_ERR(aic32x4->supply_dv);
1125 }
1126 if (IS_ERR(aic32x4->supply_av)) {
1127 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1128 return PTR_ERR(aic32x4->supply_av);
1129 }
1130 } else {
1131 if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1132 return -EPROBE_DEFER;
1133 if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1134 return -EPROBE_DEFER;
1135 }
1136
1137 ret = regulator_enable(aic32x4->supply_iov);
1138 if (ret) {
1139 dev_err(dev, "Failed to enable regulator iov\n");
1140 return ret;
1141 }
1142
1143 if (!IS_ERR(aic32x4->supply_ldo)) {
1144 ret = regulator_enable(aic32x4->supply_ldo);
1145 if (ret) {
1146 dev_err(dev, "Failed to enable regulator ldo\n");
1147 goto error_ldo;
1148 }
1149 }
1150
1151 if (!IS_ERR(aic32x4->supply_dv)) {
1152 ret = regulator_enable(aic32x4->supply_dv);
1153 if (ret) {
1154 dev_err(dev, "Failed to enable regulator dv\n");
1155 goto error_dv;
1156 }
1157 }
1158
1159 if (!IS_ERR(aic32x4->supply_av)) {
1160 ret = regulator_enable(aic32x4->supply_av);
1161 if (ret) {
1162 dev_err(dev, "Failed to enable regulator av\n");
1163 goto error_av;
1164 }
1165 }
1166
1167 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1168 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1169
1170 return 0;
1171
1172 error_av:
1173 if (!IS_ERR(aic32x4->supply_dv))
1174 regulator_disable(aic32x4->supply_dv);
1175
1176 error_dv:
1177 if (!IS_ERR(aic32x4->supply_ldo))
1178 regulator_disable(aic32x4->supply_ldo);
1179
1180 error_ldo:
1181 regulator_disable(aic32x4->supply_iov);
1182 return ret;
1183 }
1184
aic32x4_probe(struct device * dev,struct regmap * regmap)1185 int aic32x4_probe(struct device *dev, struct regmap *regmap)
1186 {
1187 struct aic32x4_priv *aic32x4;
1188 struct aic32x4_pdata *pdata = dev->platform_data;
1189 struct device_node *np = dev->of_node;
1190 int ret;
1191
1192 if (IS_ERR(regmap))
1193 return PTR_ERR(regmap);
1194
1195 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1196 GFP_KERNEL);
1197 if (aic32x4 == NULL)
1198 return -ENOMEM;
1199
1200 aic32x4->dev = dev;
1201 dev_set_drvdata(dev, aic32x4);
1202
1203 if (pdata) {
1204 aic32x4->power_cfg = pdata->power_cfg;
1205 aic32x4->swapdacs = pdata->swapdacs;
1206 aic32x4->micpga_routing = pdata->micpga_routing;
1207 aic32x4->rstn_gpio = pdata->rstn_gpio;
1208 aic32x4->mclk_name = "mclk";
1209 } else if (np) {
1210 ret = aic32x4_parse_dt(aic32x4, np);
1211 if (ret) {
1212 dev_err(dev, "Failed to parse DT node\n");
1213 return ret;
1214 }
1215 } else {
1216 aic32x4->power_cfg = 0;
1217 aic32x4->swapdacs = false;
1218 aic32x4->micpga_routing = 0;
1219 aic32x4->rstn_gpio = -1;
1220 aic32x4->mclk_name = "mclk";
1221 }
1222
1223 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1224 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1225 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1226 if (ret != 0)
1227 return ret;
1228 }
1229
1230 ret = aic32x4_setup_regulators(dev, aic32x4);
1231 if (ret) {
1232 dev_err(dev, "Failed to setup regulators\n");
1233 return ret;
1234 }
1235
1236 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1237 ndelay(10);
1238 gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
1239 mdelay(1);
1240 }
1241
1242 ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
1243 if (ret)
1244 goto err_disable_regulators;
1245
1246 ret = devm_snd_soc_register_component(dev,
1247 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1248 if (ret) {
1249 dev_err(dev, "Failed to register component\n");
1250 goto err_disable_regulators;
1251 }
1252
1253 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1254 if (ret)
1255 goto err_disable_regulators;
1256
1257 return 0;
1258
1259 err_disable_regulators:
1260 aic32x4_disable_regulators(aic32x4);
1261
1262 return ret;
1263 }
1264 EXPORT_SYMBOL(aic32x4_probe);
1265
aic32x4_remove(struct device * dev)1266 int aic32x4_remove(struct device *dev)
1267 {
1268 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1269
1270 aic32x4_disable_regulators(aic32x4);
1271
1272 return 0;
1273 }
1274 EXPORT_SYMBOL(aic32x4_remove);
1275
1276 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1277 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1278 MODULE_LICENSE("GPL");
1279
