1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #include <adf_accel_devices.h>
4 #include <adf_common_drv.h>
5 #include <adf_pf2vf_msg.h>
6 #include <adf_gen2_hw_data.h>
7 #include "adf_c62x_hw_data.h"
8 #include "icp_qat_hw.h"
9
10 /* Worker thread to service arbiter mappings */
11 static const u32 thrd_to_arb_map[ADF_C62X_MAX_ACCELENGINES] = {
12 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
13 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
14 };
15
16 static struct adf_hw_device_class c62x_class = {
17 .name = ADF_C62X_DEVICE_NAME,
18 .type = DEV_C62X,
19 .instances = 0
20 };
21
get_accel_mask(struct adf_hw_device_data * self)22 static u32 get_accel_mask(struct adf_hw_device_data *self)
23 {
24 u32 straps = self->straps;
25 u32 fuses = self->fuses;
26 u32 accel;
27
28 accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET;
29 accel &= ADF_C62X_ACCELERATORS_MASK;
30
31 return accel;
32 }
33
get_ae_mask(struct adf_hw_device_data * self)34 static u32 get_ae_mask(struct adf_hw_device_data *self)
35 {
36 u32 straps = self->straps;
37 u32 fuses = self->fuses;
38 unsigned long disabled;
39 u32 ae_disable;
40 int accel;
41
42 /* If an accel is disabled, then disable the corresponding two AEs */
43 disabled = ~get_accel_mask(self) & ADF_C62X_ACCELERATORS_MASK;
44 ae_disable = BIT(1) | BIT(0);
45 for_each_set_bit(accel, &disabled, ADF_C62X_MAX_ACCELERATORS)
46 straps |= ae_disable << (accel << 1);
47
48 return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK;
49 }
50
get_num_accels(struct adf_hw_device_data * self)51 static u32 get_num_accels(struct adf_hw_device_data *self)
52 {
53 u32 i, ctr = 0;
54
55 if (!self || !self->accel_mask)
56 return 0;
57
58 for (i = 0; i < ADF_C62X_MAX_ACCELERATORS; i++) {
59 if (self->accel_mask & (1 << i))
60 ctr++;
61 }
62 return ctr;
63 }
64
get_num_aes(struct adf_hw_device_data * self)65 static u32 get_num_aes(struct adf_hw_device_data *self)
66 {
67 u32 i, ctr = 0;
68
69 if (!self || !self->ae_mask)
70 return 0;
71
72 for (i = 0; i < ADF_C62X_MAX_ACCELENGINES; i++) {
73 if (self->ae_mask & (1 << i))
74 ctr++;
75 }
76 return ctr;
77 }
78
get_misc_bar_id(struct adf_hw_device_data * self)79 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
80 {
81 return ADF_C62X_PMISC_BAR;
82 }
83
get_etr_bar_id(struct adf_hw_device_data * self)84 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
85 {
86 return ADF_C62X_ETR_BAR;
87 }
88
get_sram_bar_id(struct adf_hw_device_data * self)89 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
90 {
91 return ADF_C62X_SRAM_BAR;
92 }
93
get_sku(struct adf_hw_device_data * self)94 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
95 {
96 int aes = get_num_aes(self);
97
98 if (aes == 8)
99 return DEV_SKU_2;
100 else if (aes == 10)
101 return DEV_SKU_4;
102
103 return DEV_SKU_UNKNOWN;
104 }
105
adf_get_arbiter_mapping(void)106 static const u32 *adf_get_arbiter_mapping(void)
107 {
108 return thrd_to_arb_map;
109 }
110
get_pf2vf_offset(u32 i)111 static u32 get_pf2vf_offset(u32 i)
112 {
113 return ADF_C62X_PF2VF_OFFSET(i);
114 }
115
adf_enable_error_correction(struct adf_accel_dev * accel_dev)116 static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
117 {
118 struct adf_hw_device_data *hw_device = accel_dev->hw_device;
119 struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C62X_PMISC_BAR];
120 unsigned long accel_mask = hw_device->accel_mask;
121 unsigned long ae_mask = hw_device->ae_mask;
122 void __iomem *csr = misc_bar->virt_addr;
123 unsigned int val, i;
124
125 /* Enable Accel Engine error detection & correction */
126 for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) {
127 val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i));
128 val |= ADF_C62X_ENABLE_AE_ECC_ERR;
129 ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val);
130 val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i));
131 val |= ADF_C62X_ENABLE_AE_ECC_PARITY_CORR;
132 ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val);
133 }
134
135 /* Enable shared memory error detection & correction */
136 for_each_set_bit(i, &accel_mask, ADF_C62X_MAX_ACCELERATORS) {
137 val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i));
138 val |= ADF_C62X_ERRSSMSH_EN;
139 ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val);
140 val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i));
141 val |= ADF_C62X_ERRSSMSH_EN;
142 ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val);
143 }
144 }
145
adf_enable_ints(struct adf_accel_dev * accel_dev)146 static void adf_enable_ints(struct adf_accel_dev *accel_dev)
147 {
148 void __iomem *addr;
149
150 addr = (&GET_BARS(accel_dev)[ADF_C62X_PMISC_BAR])->virt_addr;
151
152 /* Enable bundle and misc interrupts */
153 ADF_CSR_WR(addr, ADF_C62X_SMIAPF0_MASK_OFFSET,
154 ADF_C62X_SMIA0_MASK);
155 ADF_CSR_WR(addr, ADF_C62X_SMIAPF1_MASK_OFFSET,
156 ADF_C62X_SMIA1_MASK);
157 }
158
adf_enable_pf2vf_comms(struct adf_accel_dev * accel_dev)159 static int adf_enable_pf2vf_comms(struct adf_accel_dev *accel_dev)
160 {
161 spin_lock_init(&accel_dev->pf.vf2pf_ints_lock);
162
163 return 0;
164 }
165
configure_iov_threads(struct adf_accel_dev * accel_dev,bool enable)166 static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
167 {
168 adf_gen2_cfg_iov_thds(accel_dev, enable,
169 ADF_C62X_AE2FUNC_MAP_GRP_A_NUM_REGS,
170 ADF_C62X_AE2FUNC_MAP_GRP_B_NUM_REGS);
171 }
172
adf_init_hw_data_c62x(struct adf_hw_device_data * hw_data)173 void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
174 {
175 hw_data->dev_class = &c62x_class;
176 hw_data->instance_id = c62x_class.instances++;
177 hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS;
178 hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
179 hw_data->num_accel = ADF_C62X_MAX_ACCELERATORS;
180 hw_data->num_logical_accel = 1;
181 hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;
182 hw_data->tx_rx_gap = ADF_C62X_RX_RINGS_OFFSET;
183 hw_data->tx_rings_mask = ADF_C62X_TX_RINGS_MASK;
184 hw_data->alloc_irq = adf_isr_resource_alloc;
185 hw_data->free_irq = adf_isr_resource_free;
186 hw_data->enable_error_correction = adf_enable_error_correction;
187 hw_data->get_accel_mask = get_accel_mask;
188 hw_data->get_ae_mask = get_ae_mask;
189 hw_data->get_accel_cap = adf_gen2_get_accel_cap;
190 hw_data->get_num_accels = get_num_accels;
191 hw_data->get_num_aes = get_num_aes;
192 hw_data->get_sram_bar_id = get_sram_bar_id;
193 hw_data->get_etr_bar_id = get_etr_bar_id;
194 hw_data->get_misc_bar_id = get_misc_bar_id;
195 hw_data->get_admin_info = adf_gen2_get_admin_info;
196 hw_data->get_arb_info = adf_gen2_get_arb_info;
197 hw_data->get_sku = get_sku;
198 hw_data->fw_name = ADF_C62X_FW;
199 hw_data->fw_mmp_name = ADF_C62X_MMP;
200 hw_data->init_admin_comms = adf_init_admin_comms;
201 hw_data->exit_admin_comms = adf_exit_admin_comms;
202 hw_data->configure_iov_threads = configure_iov_threads;
203 hw_data->send_admin_init = adf_send_admin_init;
204 hw_data->init_arb = adf_init_arb;
205 hw_data->exit_arb = adf_exit_arb;
206 hw_data->get_arb_mapping = adf_get_arbiter_mapping;
207 hw_data->enable_ints = adf_enable_ints;
208 hw_data->reset_device = adf_reset_flr;
209 hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
210 hw_data->get_pf2vf_offset = get_pf2vf_offset;
211 hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
212 hw_data->disable_iov = adf_disable_sriov;
213 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
214
215 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
216 }
217
adf_clean_hw_data_c62x(struct adf_hw_device_data * hw_data)218 void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data)
219 {
220 hw_data->dev_class->instances--;
221 }
222
