1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #include <adf_accel_devices.h>
4 #include <adf_common_drv.h>
5 #include <adf_pf2vf_msg.h>
6 #include "adf_c3xxx_hw_data.h"
7
8 /* Worker thread to service arbiter mappings based on dev SKUs */
9 static const u32 thrd_to_arb_map_6_me_sku[] = {
10 0x12222AAA, 0x11222AAA, 0x12222AAA,
11 0x11222AAA, 0x12222AAA, 0x11222AAA
12 };
13
14 static struct adf_hw_device_class c3xxx_class = {
15 .name = ADF_C3XXX_DEVICE_NAME,
16 .type = DEV_C3XXX,
17 .instances = 0
18 };
19
get_accel_mask(u32 fuse)20 static u32 get_accel_mask(u32 fuse)
21 {
22 return (~fuse) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET &
23 ADF_C3XXX_ACCELERATORS_MASK;
24 }
25
get_ae_mask(u32 fuse)26 static u32 get_ae_mask(u32 fuse)
27 {
28 return (~fuse) & ADF_C3XXX_ACCELENGINES_MASK;
29 }
30
get_num_accels(struct adf_hw_device_data * self)31 static u32 get_num_accels(struct adf_hw_device_data *self)
32 {
33 u32 i, ctr = 0;
34
35 if (!self || !self->accel_mask)
36 return 0;
37
38 for (i = 0; i < ADF_C3XXX_MAX_ACCELERATORS; i++) {
39 if (self->accel_mask & (1 << i))
40 ctr++;
41 }
42 return ctr;
43 }
44
get_num_aes(struct adf_hw_device_data * self)45 static u32 get_num_aes(struct adf_hw_device_data *self)
46 {
47 u32 i, ctr = 0;
48
49 if (!self || !self->ae_mask)
50 return 0;
51
52 for (i = 0; i < ADF_C3XXX_MAX_ACCELENGINES; i++) {
53 if (self->ae_mask & (1 << i))
54 ctr++;
55 }
56 return ctr;
57 }
58
get_misc_bar_id(struct adf_hw_device_data * self)59 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
60 {
61 return ADF_C3XXX_PMISC_BAR;
62 }
63
get_etr_bar_id(struct adf_hw_device_data * self)64 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
65 {
66 return ADF_C3XXX_ETR_BAR;
67 }
68
get_sram_bar_id(struct adf_hw_device_data * self)69 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
70 {
71 return 0;
72 }
73
get_sku(struct adf_hw_device_data * self)74 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
75 {
76 int aes = get_num_aes(self);
77
78 if (aes == 6)
79 return DEV_SKU_4;
80
81 return DEV_SKU_UNKNOWN;
82 }
83
adf_get_arbiter_mapping(struct adf_accel_dev * accel_dev,u32 const ** arb_map_config)84 static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
85 u32 const **arb_map_config)
86 {
87 switch (accel_dev->accel_pci_dev.sku) {
88 case DEV_SKU_4:
89 *arb_map_config = thrd_to_arb_map_6_me_sku;
90 break;
91 default:
92 dev_err(&GET_DEV(accel_dev),
93 "The configuration doesn't match any SKU");
94 *arb_map_config = NULL;
95 }
96 }
97
get_pf2vf_offset(u32 i)98 static u32 get_pf2vf_offset(u32 i)
99 {
100 return ADF_C3XXX_PF2VF_OFFSET(i);
101 }
102
get_vintmsk_offset(u32 i)103 static u32 get_vintmsk_offset(u32 i)
104 {
105 return ADF_C3XXX_VINTMSK_OFFSET(i);
106 }
107
adf_enable_error_correction(struct adf_accel_dev * accel_dev)108 static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
109 {
110 struct adf_hw_device_data *hw_device = accel_dev->hw_device;
111 struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C3XXX_PMISC_BAR];
112 void __iomem *csr = misc_bar->virt_addr;
113 unsigned int val, i;
114
115 /* Enable Accel Engine error detection & correction */
116 for (i = 0; i < hw_device->get_num_aes(hw_device); i++) {
117 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i));
118 val |= ADF_C3XXX_ENABLE_AE_ECC_ERR;
119 ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val);
120 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i));
121 val |= ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR;
122 ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val);
123 }
124
125 /* Enable shared memory error detection & correction */
126 for (i = 0; i < hw_device->get_num_accels(hw_device); i++) {
127 val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i));
128 val |= ADF_C3XXX_ERRSSMSH_EN;
129 ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val);
130 val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i));
131 val |= ADF_C3XXX_ERRSSMSH_EN;
132 ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val);
133 }
134 }
135
adf_enable_ints(struct adf_accel_dev * accel_dev)136 static void adf_enable_ints(struct adf_accel_dev *accel_dev)
137 {
138 void __iomem *addr;
139
140 addr = (&GET_BARS(accel_dev)[ADF_C3XXX_PMISC_BAR])->virt_addr;
141
142 /* Enable bundle and misc interrupts */
143 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF0_MASK_OFFSET,
144 ADF_C3XXX_SMIA0_MASK);
145 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF1_MASK_OFFSET,
146 ADF_C3XXX_SMIA1_MASK);
147 }
148
adf_pf_enable_vf2pf_comms(struct adf_accel_dev * accel_dev)149 static int adf_pf_enable_vf2pf_comms(struct adf_accel_dev *accel_dev)
150 {
151 return 0;
152 }
153
adf_init_hw_data_c3xxx(struct adf_hw_device_data * hw_data)154 void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
155 {
156 hw_data->dev_class = &c3xxx_class;
157 hw_data->instance_id = c3xxx_class.instances++;
158 hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS;
159 hw_data->num_accel = ADF_C3XXX_MAX_ACCELERATORS;
160 hw_data->num_logical_accel = 1;
161 hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;
162 hw_data->tx_rx_gap = ADF_C3XXX_RX_RINGS_OFFSET;
163 hw_data->tx_rings_mask = ADF_C3XXX_TX_RINGS_MASK;
164 hw_data->alloc_irq = adf_isr_resource_alloc;
165 hw_data->free_irq = adf_isr_resource_free;
166 hw_data->enable_error_correction = adf_enable_error_correction;
167 hw_data->get_accel_mask = get_accel_mask;
168 hw_data->get_ae_mask = get_ae_mask;
169 hw_data->get_num_accels = get_num_accels;
170 hw_data->get_num_aes = get_num_aes;
171 hw_data->get_sram_bar_id = get_sram_bar_id;
172 hw_data->get_etr_bar_id = get_etr_bar_id;
173 hw_data->get_misc_bar_id = get_misc_bar_id;
174 hw_data->get_pf2vf_offset = get_pf2vf_offset;
175 hw_data->get_vintmsk_offset = get_vintmsk_offset;
176 hw_data->get_sku = get_sku;
177 hw_data->fw_name = ADF_C3XXX_FW;
178 hw_data->fw_mmp_name = ADF_C3XXX_MMP;
179 hw_data->init_admin_comms = adf_init_admin_comms;
180 hw_data->exit_admin_comms = adf_exit_admin_comms;
181 hw_data->disable_iov = adf_disable_sriov;
182 hw_data->send_admin_init = adf_send_admin_init;
183 hw_data->init_arb = adf_init_arb;
184 hw_data->exit_arb = adf_exit_arb;
185 hw_data->get_arb_mapping = adf_get_arbiter_mapping;
186 hw_data->enable_ints = adf_enable_ints;
187 hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;
188 hw_data->reset_device = adf_reset_flr;
189 hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;
190 }
191
adf_clean_hw_data_c3xxx(struct adf_hw_device_data * hw_data)192 void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
193 {
194 hw_data->dev_class->instances--;
195 }
196
