1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 *
5 * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
6 * -flush_cache_dup_mm (fork)
7 * -likewise for flush_cache_mm (exit/execve)
8 * -likewise for flush_cache_{range,page} (munmap, exit, COW-break)
9 *
10 * vineetg: April 2008
11 * -Added a critical CacheLine flush to copy_to_user_page( ) which
12 * was causing gdbserver to not setup breakpoints consistently
13 */
14
15 #ifndef _ASM_CACHEFLUSH_H
16 #define _ASM_CACHEFLUSH_H
17
18 #include <linux/mm.h>
19 #include <asm/shmparam.h>
20
21 void flush_cache_all(void);
22
23 void flush_icache_range(unsigned long kstart, unsigned long kend);
24 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
25 void __inv_icache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr);
26 void __flush_dcache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr);
27
28 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
29
30 void flush_dcache_page(struct page *page);
31 void flush_dcache_folio(struct folio *folio);
32 #define flush_dcache_folio flush_dcache_folio
33
34 void dma_cache_wback_inv(phys_addr_t start, unsigned long sz);
35 void dma_cache_inv(phys_addr_t start, unsigned long sz);
36 void dma_cache_wback(phys_addr_t start, unsigned long sz);
37
38 #define flush_dcache_mmap_lock(mapping) do { } while (0)
39 #define flush_dcache_mmap_unlock(mapping) do { } while (0)
40
41 /* TBD: optimize this */
42 #define flush_cache_vmap(start, end) flush_cache_all()
43 #define flush_cache_vunmap(start, end) flush_cache_all()
44
45 #define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */
46
47 #ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
48
49 #define flush_cache_mm(mm) /* called on munmap/exit */
50 #define flush_cache_range(mm, u_vstart, u_vend)
51 #define flush_cache_page(vma, u_vaddr, pfn) /* PF handling/COW-break */
52
53 #else /* VIPT aliasing dcache */
54
55 /* To clear out stale userspace mappings */
56 void flush_cache_mm(struct mm_struct *mm);
57 void flush_cache_range(struct vm_area_struct *vma,
58 unsigned long start,unsigned long end);
59 void flush_cache_page(struct vm_area_struct *vma,
60 unsigned long user_addr, unsigned long page);
61
62 /*
63 * To make sure that userspace mapping is flushed to memory before
64 * get_user_pages() uses a kernel mapping to access the page
65 */
66 #define ARCH_HAS_FLUSH_ANON_PAGE
67 void flush_anon_page(struct vm_area_struct *vma,
68 struct page *page, unsigned long u_vaddr);
69
70 #endif /* CONFIG_ARC_CACHE_VIPT_ALIASING */
71
72 /*
73 * A new pagecache page has PG_arch_1 clear - thus dcache dirty by default
74 * This works around some PIO based drivers which don't call flush_dcache_page
75 * to record that they dirtied the dcache
76 */
77 #define PG_dc_clean PG_arch_1
78
79 #define CACHE_COLORS_NUM 4
80 #define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1)
81 #define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)
82
83 /*
84 * Simple wrapper over config option
85 * Bootup code ensures that hardware matches kernel configuration
86 */
cache_is_vipt_aliasing(void)87 static inline int cache_is_vipt_aliasing(void)
88 {
89 return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
90 }
91
92 /*
93 * checks if two addresses (after page aligning) index into same cache set
94 */
95 #define addr_not_cache_congruent(addr1, addr2) \
96 ({ \
97 cache_is_vipt_aliasing() ? \
98 (CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0; \
99 })
100
101 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
102 do { \
103 memcpy(dst, src, len); \
104 if (vma->vm_flags & VM_EXEC) \
105 __sync_icache_dcache((unsigned long)(dst), vaddr, len); \
106 } while (0)
107
108 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
109 memcpy(dst, src, len); \
110
111 #endif
112
