1 /*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "acr_r370.h"
24 #include "acr_r367.h"
25
26 #include <core/msgqueue.h>
27 #include <engine/falcon.h>
28 #include <engine/sec2.h>
29
30 static void
acr_r370_generate_flcn_bl_desc(const struct nvkm_acr * acr,const struct ls_ucode_img * img,u64 wpr_addr,void * _desc)31 acr_r370_generate_flcn_bl_desc(const struct nvkm_acr *acr,
32 const struct ls_ucode_img *img, u64 wpr_addr,
33 void *_desc)
34 {
35 struct acr_r370_flcn_bl_desc *desc = _desc;
36 const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
37 u64 base, addr_code, addr_data;
38
39 base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
40 addr_code = base + pdesc->app_resident_code_offset;
41 addr_data = base + pdesc->app_resident_data_offset;
42
43 desc->ctx_dma = FALCON_DMAIDX_UCODE;
44 desc->code_dma_base = u64_to_flcn64(addr_code);
45 desc->non_sec_code_off = pdesc->app_resident_code_offset;
46 desc->non_sec_code_size = pdesc->app_resident_code_size;
47 desc->code_entry_point = pdesc->app_imem_entry;
48 desc->data_dma_base = u64_to_flcn64(addr_data);
49 desc->data_size = pdesc->app_resident_data_size;
50 }
51
52 const struct acr_r352_ls_func
53 acr_r370_ls_fecs_func = {
54 .load = acr_ls_ucode_load_fecs,
55 .generate_bl_desc = acr_r370_generate_flcn_bl_desc,
56 .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
57 };
58
59 const struct acr_r352_ls_func
60 acr_r370_ls_gpccs_func = {
61 .load = acr_ls_ucode_load_gpccs,
62 .generate_bl_desc = acr_r370_generate_flcn_bl_desc,
63 .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
64 /* GPCCS will be loaded using PRI */
65 .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD,
66 };
67
68 static void
acr_r370_generate_sec2_bl_desc(const struct nvkm_acr * acr,const struct ls_ucode_img * img,u64 wpr_addr,void * _desc)69 acr_r370_generate_sec2_bl_desc(const struct nvkm_acr *acr,
70 const struct ls_ucode_img *img, u64 wpr_addr,
71 void *_desc)
72 {
73 const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
74 const struct nvkm_sec2 *sec = acr->subdev->device->sec2;
75 struct acr_r370_flcn_bl_desc *desc = _desc;
76 u64 base, addr_code, addr_data;
77 u32 addr_args;
78
79 base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
80 /* For some reason we should not add app_resident_code_offset here */
81 addr_code = base;
82 addr_data = base + pdesc->app_resident_data_offset;
83 addr_args = sec->falcon->data.limit;
84 addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;
85
86 desc->ctx_dma = FALCON_SEC2_DMAIDX_UCODE;
87 desc->code_dma_base = u64_to_flcn64(addr_code);
88 desc->non_sec_code_off = pdesc->app_resident_code_offset;
89 desc->non_sec_code_size = pdesc->app_resident_code_size;
90 desc->code_entry_point = pdesc->app_imem_entry;
91 desc->data_dma_base = u64_to_flcn64(addr_data);
92 desc->data_size = pdesc->app_resident_data_size;
93 desc->argc = 1;
94 /* args are stored at the beginning of EMEM */
95 desc->argv = 0x01000000;
96 }
97
98 const struct acr_r352_ls_func
99 acr_r370_ls_sec2_func = {
100 .load = acr_ls_ucode_load_sec2,
101 .generate_bl_desc = acr_r370_generate_sec2_bl_desc,
102 .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
103 .post_run = acr_ls_sec2_post_run,
104 };
105
106 void
acr_r370_generate_hs_bl_desc(const struct hsf_load_header * hdr,void * _bl_desc,u64 offset)107 acr_r370_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,
108 u64 offset)
109 {
110 struct acr_r370_flcn_bl_desc *bl_desc = _bl_desc;
111
112 bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
113 bl_desc->non_sec_code_off = hdr->non_sec_code_off;
114 bl_desc->non_sec_code_size = hdr->non_sec_code_size;
115 bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0);
116 bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0);
117 bl_desc->code_entry_point = 0;
118 bl_desc->code_dma_base = u64_to_flcn64(offset);
119 bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base);
120 bl_desc->data_size = hdr->data_size;
121 }
122
123 const struct acr_r352_func
124 acr_r370_func = {
125 .fixup_hs_desc = acr_r367_fixup_hs_desc,
126 .generate_hs_bl_desc = acr_r370_generate_hs_bl_desc,
127 .hs_bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
128 .shadow_blob = true,
129 .ls_ucode_img_load = acr_r367_ls_ucode_img_load,
130 .ls_fill_headers = acr_r367_ls_fill_headers,
131 .ls_write_wpr = acr_r367_ls_write_wpr,
132 .ls_func = {
133 [NVKM_SECBOOT_FALCON_SEC2] = &acr_r370_ls_sec2_func,
134 [NVKM_SECBOOT_FALCON_FECS] = &acr_r370_ls_fecs_func,
135 [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r370_ls_gpccs_func,
136 },
137 };
138
139 struct nvkm_acr *
acr_r370_new(enum nvkm_secboot_falcon boot_falcon,unsigned long managed_falcons)140 acr_r370_new(enum nvkm_secboot_falcon boot_falcon,
141 unsigned long managed_falcons)
142 {
143 return acr_r352_new_(&acr_r370_func, boot_falcon, managed_falcons);
144 }
145
