1 /*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "acr_r352.h"
24 #include "hs_ucode.h"
25
26 #include <core/gpuobj.h>
27 #include <core/firmware.h>
28 #include <engine/falcon.h>
29 #include <subdev/pmu.h>
30 #include <core/msgqueue.h>
31 #include <engine/sec2.h>
32
33 /**
34 * struct acr_r352_flcn_bl_desc - DMEM bootloader descriptor
35 * @signature: 16B signature for secure code. 0s if no secure code
36 * @ctx_dma: DMA context to be used by BL while loading code/data
37 * @code_dma_base: 256B-aligned Physical FB Address where code is located
38 * (falcon's $xcbase register)
39 * @non_sec_code_off: offset from code_dma_base where the non-secure code is
40 * located. The offset must be multiple of 256 to help perf
41 * @non_sec_code_size: the size of the nonSecure code part.
42 * @sec_code_off: offset from code_dma_base where the secure code is
43 * located. The offset must be multiple of 256 to help perf
44 * @sec_code_size: offset from code_dma_base where the secure code is
45 * located. The offset must be multiple of 256 to help perf
46 * @code_entry_point: code entry point which will be invoked by BL after
47 * code is loaded.
48 * @data_dma_base: 256B aligned Physical FB Address where data is located.
49 * (falcon's $xdbase register)
50 * @data_size: size of data block. Should be multiple of 256B
51 *
52 * Structure used by the bootloader to load the rest of the code. This has
53 * to be filled by host and copied into DMEM at offset provided in the
54 * hsflcn_bl_desc.bl_desc_dmem_load_off.
55 */
56 struct acr_r352_flcn_bl_desc {
57 u32 reserved[4];
58 u32 signature[4];
59 u32 ctx_dma;
60 u32 code_dma_base;
61 u32 non_sec_code_off;
62 u32 non_sec_code_size;
63 u32 sec_code_off;
64 u32 sec_code_size;
65 u32 code_entry_point;
66 u32 data_dma_base;
67 u32 data_size;
68 u32 code_dma_base1;
69 u32 data_dma_base1;
70 };
71
72 /**
73 * acr_r352_generate_flcn_bl_desc - generate generic BL descriptor for LS image
74 */
75 static void
acr_r352_generate_flcn_bl_desc(const struct nvkm_acr * acr,const struct ls_ucode_img * img,u64 wpr_addr,void * _desc)76 acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr,
77 const struct ls_ucode_img *img, u64 wpr_addr,
78 void *_desc)
79 {
80 struct acr_r352_flcn_bl_desc *desc = _desc;
81 const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
82 u64 base, addr_code, addr_data;
83
84 base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
85 addr_code = (base + pdesc->app_resident_code_offset) >> 8;
86 addr_data = (base + pdesc->app_resident_data_offset) >> 8;
87
88 desc->ctx_dma = FALCON_DMAIDX_UCODE;
89 desc->code_dma_base = lower_32_bits(addr_code);
90 desc->code_dma_base1 = upper_32_bits(addr_code);
91 desc->non_sec_code_off = pdesc->app_resident_code_offset;
92 desc->non_sec_code_size = pdesc->app_resident_code_size;
93 desc->code_entry_point = pdesc->app_imem_entry;
94 desc->data_dma_base = lower_32_bits(addr_data);
95 desc->data_dma_base1 = upper_32_bits(addr_data);
96 desc->data_size = pdesc->app_resident_data_size;
97 }
98
99
100 /**
101 * struct hsflcn_acr_desc - data section of the HS firmware
102 *
103 * This header is to be copied at the beginning of DMEM by the HS bootloader.
104 *
105 * @signature: signature of ACR ucode
106 * @wpr_region_id: region ID holding the WPR header and its details
107 * @wpr_offset: offset from the WPR region holding the wpr header
108 * @regions: region descriptors
109 * @nonwpr_ucode_blob_size: size of LS blob
110 * @nonwpr_ucode_blob_start: FB location of LS blob is
111 */
112 struct hsflcn_acr_desc {
113 union {
114 u8 reserved_dmem[0x200];
115 u32 signatures[4];
116 } ucode_reserved_space;
117 u32 wpr_region_id;
118 u32 wpr_offset;
119 u32 mmu_mem_range;
120 #define FLCN_ACR_MAX_REGIONS 2
121 struct {
122 u32 no_regions;
123 struct {
124 u32 start_addr;
125 u32 end_addr;
126 u32 region_id;
127 u32 read_mask;
128 u32 write_mask;
129 u32 client_mask;
130 } region_props[FLCN_ACR_MAX_REGIONS];
131 } regions;
132 u32 ucode_blob_size;
133 u64 ucode_blob_base __aligned(8);
134 struct {
135 u32 vpr_enabled;
136 u32 vpr_start;
137 u32 vpr_end;
138 u32 hdcp_policies;
139 } vpr_desc;
140 };
141
142
143 /*
144 * Low-secure blob creation
145 */
146
147 /**
148 * struct acr_r352_lsf_lsb_header - LS firmware header
149 * @signature: signature to verify the firmware against
150 * @ucode_off: offset of the ucode blob in the WPR region. The ucode
151 * blob contains the bootloader, code and data of the
152 * LS falcon
153 * @ucode_size: size of the ucode blob, including bootloader
154 * @data_size: size of the ucode blob data
155 * @bl_code_size: size of the bootloader code
156 * @bl_imem_off: offset in imem of the bootloader
157 * @bl_data_off: offset of the bootloader data in WPR region
158 * @bl_data_size: size of the bootloader data
159 * @app_code_off: offset of the app code relative to ucode_off
160 * @app_code_size: size of the app code
161 * @app_data_off: offset of the app data relative to ucode_off
162 * @app_data_size: size of the app data
163 * @flags: flags for the secure bootloader
164 *
165 * This structure is written into the WPR region for each managed falcon. Each
166 * instance is referenced by the lsb_offset member of the corresponding
167 * lsf_wpr_header.
168 */
169 struct acr_r352_lsf_lsb_header {
170 /**
171 * LS falcon signatures
172 * @prd_keys: signature to use in production mode
173 * @dgb_keys: signature to use in debug mode
174 * @b_prd_present: whether the production key is present
175 * @b_dgb_present: whether the debug key is present
176 * @falcon_id: ID of the falcon the ucode applies to
177 */
178 struct {
179 u8 prd_keys[2][16];
180 u8 dbg_keys[2][16];
181 u32 b_prd_present;
182 u32 b_dbg_present;
183 u32 falcon_id;
184 } signature;
185 u32 ucode_off;
186 u32 ucode_size;
187 u32 data_size;
188 u32 bl_code_size;
189 u32 bl_imem_off;
190 u32 bl_data_off;
191 u32 bl_data_size;
192 u32 app_code_off;
193 u32 app_code_size;
194 u32 app_data_off;
195 u32 app_data_size;
196 u32 flags;
197 };
198
199 /**
200 * struct acr_r352_lsf_wpr_header - LS blob WPR Header
201 * @falcon_id: LS falcon ID
202 * @lsb_offset: offset of the lsb_lsf_header in the WPR region
203 * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon
204 * @lazy_bootstrap: skip bootstrapping by ACR
205 * @status: bootstrapping status
206 *
207 * An array of these is written at the beginning of the WPR region, one for
208 * each managed falcon. The array is terminated by an instance which falcon_id
209 * is LSF_FALCON_ID_INVALID.
210 */
211 struct acr_r352_lsf_wpr_header {
212 u32 falcon_id;
213 u32 lsb_offset;
214 u32 bootstrap_owner;
215 u32 lazy_bootstrap;
216 u32 status;
217 #define LSF_IMAGE_STATUS_NONE 0
218 #define LSF_IMAGE_STATUS_COPY 1
219 #define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2
220 #define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3
221 #define LSF_IMAGE_STATUS_VALIDATION_DONE 4
222 #define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5
223 #define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6
224 };
225
226 /**
227 * struct ls_ucode_img_r352 - ucode image augmented with r352 headers
228 */
229 struct ls_ucode_img_r352 {
230 struct ls_ucode_img base;
231
232 struct acr_r352_lsf_wpr_header wpr_header;
233 struct acr_r352_lsf_lsb_header lsb_header;
234 };
235 #define ls_ucode_img_r352(i) container_of(i, struct ls_ucode_img_r352, base)
236
237 /**
238 * ls_ucode_img_load() - create a lsf_ucode_img and load it
239 */
240 struct ls_ucode_img *
acr_r352_ls_ucode_img_load(const struct acr_r352 * acr,const struct nvkm_secboot * sb,enum nvkm_secboot_falcon falcon_id)241 acr_r352_ls_ucode_img_load(const struct acr_r352 *acr,
242 const struct nvkm_secboot *sb,
243 enum nvkm_secboot_falcon falcon_id)
244 {
245 const struct nvkm_subdev *subdev = acr->base.subdev;
246 struct ls_ucode_img_r352 *img;
247 int ret;
248
249 img = kzalloc(sizeof(*img), GFP_KERNEL);
250 if (!img)
251 return ERR_PTR(-ENOMEM);
252
253 img->base.falcon_id = falcon_id;
254
255 ret = acr->func->ls_func[falcon_id]->load(sb, &img->base);
256
257 if (ret) {
258 kfree(img->base.ucode_data);
259 kfree(img->base.sig);
260 kfree(img);
261 return ERR_PTR(ret);
262 }
263
264 /* Check that the signature size matches our expectations... */
265 if (img->base.sig_size != sizeof(img->lsb_header.signature)) {
266 nvkm_error(subdev, "invalid signature size for %s falcon!\n",
267 nvkm_secboot_falcon_name[falcon_id]);
268 return ERR_PTR(-EINVAL);
269 }
270
271 /* Copy signature to the right place */
272 memcpy(&img->lsb_header.signature, img->base.sig, img->base.sig_size);
273
274 /* not needed? the signature should already have the right value */
275 img->lsb_header.signature.falcon_id = falcon_id;
276
277 return &img->base;
278 }
279
280 #define LSF_LSB_HEADER_ALIGN 256
281 #define LSF_BL_DATA_ALIGN 256
282 #define LSF_BL_DATA_SIZE_ALIGN 256
283 #define LSF_BL_CODE_SIZE_ALIGN 256
284 #define LSF_UCODE_DATA_ALIGN 4096
285
286 /**
287 * acr_r352_ls_img_fill_headers - fill the WPR and LSB headers of an image
288 * @acr: ACR to use
289 * @img: image to generate for
290 * @offset: offset in the WPR region where this image starts
291 *
292 * Allocate space in the WPR area from offset and write the WPR and LSB headers
293 * accordingly.
294 *
295 * Return: offset at the end of this image.
296 */
297 static u32
acr_r352_ls_img_fill_headers(struct acr_r352 * acr,struct ls_ucode_img_r352 * img,u32 offset)298 acr_r352_ls_img_fill_headers(struct acr_r352 *acr,
299 struct ls_ucode_img_r352 *img, u32 offset)
300 {
301 struct ls_ucode_img *_img = &img->base;
302 struct acr_r352_lsf_wpr_header *whdr = &img->wpr_header;
303 struct acr_r352_lsf_lsb_header *lhdr = &img->lsb_header;
304 struct ls_ucode_img_desc *desc = &_img->ucode_desc;
305 const struct acr_r352_ls_func *func =
306 acr->func->ls_func[_img->falcon_id];
307
308 /* Fill WPR header */
309 whdr->falcon_id = _img->falcon_id;
310 whdr->bootstrap_owner = acr->base.boot_falcon;
311 whdr->status = LSF_IMAGE_STATUS_COPY;
312
313 /* Skip bootstrapping falcons started by someone else than ACR */
314 if (acr->lazy_bootstrap & BIT(_img->falcon_id))
315 whdr->lazy_bootstrap = 1;
316
317 /* Align, save off, and include an LSB header size */
318 offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN);
319 whdr->lsb_offset = offset;
320 offset += sizeof(*lhdr);
321
322 /*
323 * Align, save off, and include the original (static) ucode
324 * image size
325 */
326 offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN);
327 _img->ucode_off = lhdr->ucode_off = offset;
328 offset += _img->ucode_size;
329
330 /*
331 * For falcons that use a boot loader (BL), we append a loader
332 * desc structure on the end of the ucode image and consider
333 * this the boot loader data. The host will then copy the loader
334 * desc args to this space within the WPR region (before locking
335 * down) and the HS bin will then copy them to DMEM 0 for the
336 * loader.
337 */
338 lhdr->bl_code_size = ALIGN(desc->bootloader_size,
339 LSF_BL_CODE_SIZE_ALIGN);
340 lhdr->ucode_size = ALIGN(desc->app_resident_data_offset,
341 LSF_BL_CODE_SIZE_ALIGN) + lhdr->bl_code_size;
342 lhdr->data_size = ALIGN(desc->app_size, LSF_BL_CODE_SIZE_ALIGN) +
343 lhdr->bl_code_size - lhdr->ucode_size;
344 /*
345 * Though the BL is located at 0th offset of the image, the VA
346 * is different to make sure that it doesn't collide the actual
347 * OS VA range
348 */
349 lhdr->bl_imem_off = desc->bootloader_imem_offset;
350 lhdr->app_code_off = desc->app_start_offset +
351 desc->app_resident_code_offset;
352 lhdr->app_code_size = desc->app_resident_code_size;
353 lhdr->app_data_off = desc->app_start_offset +
354 desc->app_resident_data_offset;
355 lhdr->app_data_size = desc->app_resident_data_size;
356
357 lhdr->flags = func->lhdr_flags;
358 if (_img->falcon_id == acr->base.boot_falcon)
359 lhdr->flags |= LSF_FLAG_DMACTL_REQ_CTX;
360
361 /* Align and save off BL descriptor size */
362 lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN);
363
364 /*
365 * Align, save off, and include the additional BL data
366 */
367 offset = ALIGN(offset, LSF_BL_DATA_ALIGN);
368 lhdr->bl_data_off = offset;
369 offset += lhdr->bl_data_size;
370
371 return offset;
372 }
373
374 /**
375 * acr_r352_ls_fill_headers - fill WPR and LSB headers of all managed images
376 */
377 int
acr_r352_ls_fill_headers(struct acr_r352 * acr,struct list_head * imgs)378 acr_r352_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs)
379 {
380 struct ls_ucode_img_r352 *img;
381 struct list_head *l;
382 u32 count = 0;
383 u32 offset;
384
385 /* Count the number of images to manage */
386 list_for_each(l, imgs)
387 count++;
388
389 /*
390 * Start with an array of WPR headers at the base of the WPR.
391 * The expectation here is that the secure falcon will do a single DMA
392 * read of this array and cache it internally so it's ok to pack these.
393 * Also, we add 1 to the falcon count to indicate the end of the array.
394 */
395 offset = sizeof(img->wpr_header) * (count + 1);
396
397 /*
398 * Walk the managed falcons, accounting for the LSB structs
399 * as well as the ucode images.
400 */
401 list_for_each_entry(img, imgs, base.node) {
402 offset = acr_r352_ls_img_fill_headers(acr, img, offset);
403 }
404
405 return offset;
406 }
407
408 /**
409 * acr_r352_ls_write_wpr - write the WPR blob contents
410 */
411 int
acr_r352_ls_write_wpr(struct acr_r352 * acr,struct list_head * imgs,struct nvkm_gpuobj * wpr_blob,u64 wpr_addr)412 acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs,
413 struct nvkm_gpuobj *wpr_blob, u64 wpr_addr)
414 {
415 struct ls_ucode_img *_img;
416 u32 pos = 0;
417 u32 max_desc_size = 0;
418 u8 *gdesc;
419
420 /* Figure out how large we need gdesc to be. */
421 list_for_each_entry(_img, imgs, node) {
422 const struct acr_r352_ls_func *ls_func =
423 acr->func->ls_func[_img->falcon_id];
424
425 max_desc_size = max(max_desc_size, ls_func->bl_desc_size);
426 }
427
428 gdesc = kmalloc(max_desc_size, GFP_KERNEL);
429 if (!gdesc)
430 return -ENOMEM;
431
432 nvkm_kmap(wpr_blob);
433
434 list_for_each_entry(_img, imgs, node) {
435 struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img);
436 const struct acr_r352_ls_func *ls_func =
437 acr->func->ls_func[_img->falcon_id];
438
439 nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header,
440 sizeof(img->wpr_header));
441
442 nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset,
443 &img->lsb_header, sizeof(img->lsb_header));
444
445 /* Generate and write BL descriptor */
446 memset(gdesc, 0, ls_func->bl_desc_size);
447 ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc);
448
449 nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off,
450 gdesc, ls_func->bl_desc_size);
451
452 /* Copy ucode */
453 nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off,
454 _img->ucode_data, _img->ucode_size);
455
456 pos += sizeof(img->wpr_header);
457 }
458
459 nvkm_wo32(wpr_blob, pos, NVKM_SECBOOT_FALCON_INVALID);
460
461 nvkm_done(wpr_blob);
462
463 kfree(gdesc);
464
465 return 0;
466 }
467
468 /* Both size and address of WPR need to be 256K-aligned */
469 #define WPR_ALIGNMENT 0x40000
470 /**
471 * acr_r352_prepare_ls_blob() - prepare the LS blob
472 *
473 * For each securely managed falcon, load the FW, signatures and bootloaders and
474 * prepare a ucode blob. Then, compute the offsets in the WPR region for each
475 * blob, and finally write the headers and ucode blobs into a GPU object that
476 * will be copied into the WPR region by the HS firmware.
477 */
478 static int
acr_r352_prepare_ls_blob(struct acr_r352 * acr,struct nvkm_secboot * sb)479 acr_r352_prepare_ls_blob(struct acr_r352 *acr, struct nvkm_secboot *sb)
480 {
481 const struct nvkm_subdev *subdev = acr->base.subdev;
482 struct list_head imgs;
483 struct ls_ucode_img *img, *t;
484 unsigned long managed_falcons = acr->base.managed_falcons;
485 u64 wpr_addr = sb->wpr_addr;
486 u32 wpr_size = sb->wpr_size;
487 int managed_count = 0;
488 u32 image_wpr_size, ls_blob_size;
489 int falcon_id;
490 int ret;
491
492 INIT_LIST_HEAD(&imgs);
493
494 /* Load all LS blobs */
495 for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) {
496 struct ls_ucode_img *img;
497
498 img = acr->func->ls_ucode_img_load(acr, sb, falcon_id);
499 if (IS_ERR(img)) {
500 if (acr->base.optional_falcons & BIT(falcon_id)) {
501 managed_falcons &= ~BIT(falcon_id);
502 nvkm_info(subdev, "skipping %s falcon...\n",
503 nvkm_secboot_falcon_name[falcon_id]);
504 continue;
505 }
506 ret = PTR_ERR(img);
507 goto cleanup;
508 }
509
510 list_add_tail(&img->node, &imgs);
511 managed_count++;
512 }
513
514 /* Commit the actual list of falcons we will manage from now on */
515 acr->base.managed_falcons = managed_falcons;
516
517 /*
518 * If the boot falcon has a firmare, let it manage the bootstrap of other
519 * falcons.
520 */
521 if (acr->func->ls_func[acr->base.boot_falcon] &&
522 (managed_falcons & BIT(acr->base.boot_falcon))) {
523 for_each_set_bit(falcon_id, &managed_falcons,
524 NVKM_SECBOOT_FALCON_END) {
525 if (falcon_id == acr->base.boot_falcon)
526 continue;
527
528 acr->lazy_bootstrap |= BIT(falcon_id);
529 }
530 }
531
532 /*
533 * Fill the WPR and LSF headers with the right offsets and compute
534 * required WPR size
535 */
536 image_wpr_size = acr->func->ls_fill_headers(acr, &imgs);
537 image_wpr_size = ALIGN(image_wpr_size, WPR_ALIGNMENT);
538
539 ls_blob_size = image_wpr_size;
540
541 /*
542 * If we need a shadow area, allocate twice the size and use the
543 * upper half as WPR
544 */
545 if (wpr_size == 0 && acr->func->shadow_blob)
546 ls_blob_size *= 2;
547
548 /* Allocate GPU object that will contain the WPR region */
549 ret = nvkm_gpuobj_new(subdev->device, ls_blob_size, WPR_ALIGNMENT,
550 false, NULL, &acr->ls_blob);
551 if (ret)
552 goto cleanup;
553
554 nvkm_debug(subdev, "%d managed LS falcons, WPR size is %d bytes\n",
555 managed_count, image_wpr_size);
556
557 /* If WPR address and size are not fixed, set them to fit the LS blob */
558 if (wpr_size == 0) {
559 wpr_addr = acr->ls_blob->addr;
560 if (acr->func->shadow_blob)
561 wpr_addr += acr->ls_blob->size / 2;
562
563 wpr_size = image_wpr_size;
564 /*
565 * But if the WPR region is set by the bootloader, it is illegal for
566 * the HS blob to be larger than this region.
567 */
568 } else if (image_wpr_size > wpr_size) {
569 nvkm_error(subdev, "WPR region too small for FW blob!\n");
570 nvkm_error(subdev, "required: %dB\n", image_wpr_size);
571 nvkm_error(subdev, "available: %dB\n", wpr_size);
572 ret = -ENOSPC;
573 goto cleanup;
574 }
575
576 /* Write LS blob */
577 ret = acr->func->ls_write_wpr(acr, &imgs, acr->ls_blob, wpr_addr);
578 if (ret)
579 nvkm_gpuobj_del(&acr->ls_blob);
580
581 cleanup:
582 list_for_each_entry_safe(img, t, &imgs, node) {
583 kfree(img->ucode_data);
584 kfree(img->sig);
585 kfree(img);
586 }
587
588 return ret;
589 }
590
591
592
593
594 void
acr_r352_fixup_hs_desc(struct acr_r352 * acr,struct nvkm_secboot * sb,void * _desc)595 acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb,
596 void *_desc)
597 {
598 struct hsflcn_acr_desc *desc = _desc;
599 struct nvkm_gpuobj *ls_blob = acr->ls_blob;
600
601 /* WPR region information if WPR is not fixed */
602 if (sb->wpr_size == 0) {
603 u64 wpr_start = ls_blob->addr;
604 u64 wpr_end = wpr_start + ls_blob->size;
605
606 desc->wpr_region_id = 1;
607 desc->regions.no_regions = 2;
608 desc->regions.region_props[0].start_addr = wpr_start >> 8;
609 desc->regions.region_props[0].end_addr = wpr_end >> 8;
610 desc->regions.region_props[0].region_id = 1;
611 desc->regions.region_props[0].read_mask = 0xf;
612 desc->regions.region_props[0].write_mask = 0xc;
613 desc->regions.region_props[0].client_mask = 0x2;
614 } else {
615 desc->ucode_blob_base = ls_blob->addr;
616 desc->ucode_blob_size = ls_blob->size;
617 }
618 }
619
620 static void
acr_r352_generate_hs_bl_desc(const struct hsf_load_header * hdr,void * _bl_desc,u64 offset)621 acr_r352_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,
622 u64 offset)
623 {
624 struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc;
625 u64 addr_code, addr_data;
626
627 addr_code = offset >> 8;
628 addr_data = (offset + hdr->data_dma_base) >> 8;
629
630 bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
631 bl_desc->code_dma_base = lower_32_bits(addr_code);
632 bl_desc->non_sec_code_off = hdr->non_sec_code_off;
633 bl_desc->non_sec_code_size = hdr->non_sec_code_size;
634 bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0);
635 bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0);
636 bl_desc->code_entry_point = 0;
637 bl_desc->data_dma_base = lower_32_bits(addr_data);
638 bl_desc->data_size = hdr->data_size;
639 }
640
641 /**
642 * acr_r352_prepare_hs_blob - load and prepare a HS blob and BL descriptor
643 *
644 * @sb secure boot instance to prepare for
645 * @fw name of the HS firmware to load
646 * @blob pointer to gpuobj that will be allocated to receive the HS FW payload
647 * @bl_desc pointer to the BL descriptor to write for this firmware
648 * @patch whether we should patch the HS descriptor (only for HS loaders)
649 */
650 static int
acr_r352_prepare_hs_blob(struct acr_r352 * acr,struct nvkm_secboot * sb,const char * fw,struct nvkm_gpuobj ** blob,struct hsf_load_header * load_header,bool patch)651 acr_r352_prepare_hs_blob(struct acr_r352 *acr, struct nvkm_secboot *sb,
652 const char *fw, struct nvkm_gpuobj **blob,
653 struct hsf_load_header *load_header, bool patch)
654 {
655 struct nvkm_subdev *subdev = &sb->subdev;
656 void *acr_image;
657 struct fw_bin_header *hsbin_hdr;
658 struct hsf_fw_header *fw_hdr;
659 struct hsf_load_header *load_hdr;
660 void *acr_data;
661 int ret;
662
663 acr_image = hs_ucode_load_blob(subdev, sb->boot_falcon, fw);
664 if (IS_ERR(acr_image))
665 return PTR_ERR(acr_image);
666
667 hsbin_hdr = acr_image;
668 fw_hdr = acr_image + hsbin_hdr->header_offset;
669 load_hdr = acr_image + fw_hdr->hdr_offset;
670 acr_data = acr_image + hsbin_hdr->data_offset;
671
672 /* Patch descriptor with WPR information? */
673 if (patch) {
674 struct hsflcn_acr_desc *desc;
675
676 desc = acr_data + load_hdr->data_dma_base;
677 acr->func->fixup_hs_desc(acr, sb, desc);
678 }
679
680 if (load_hdr->num_apps > ACR_R352_MAX_APPS) {
681 nvkm_error(subdev, "more apps (%d) than supported (%d)!",
682 load_hdr->num_apps, ACR_R352_MAX_APPS);
683 ret = -EINVAL;
684 goto cleanup;
685 }
686 memcpy(load_header, load_hdr, sizeof(*load_header) +
687 (sizeof(load_hdr->apps[0]) * 2 * load_hdr->num_apps));
688
689 /* Create ACR blob and copy HS data to it */
690 ret = nvkm_gpuobj_new(subdev->device, ALIGN(hsbin_hdr->data_size, 256),
691 0x1000, false, NULL, blob);
692 if (ret)
693 goto cleanup;
694
695 nvkm_kmap(*blob);
696 nvkm_gpuobj_memcpy_to(*blob, 0, acr_data, hsbin_hdr->data_size);
697 nvkm_done(*blob);
698
699 cleanup:
700 kfree(acr_image);
701
702 return ret;
703 }
704
705 /**
706 * acr_r352_load_blobs - load blobs common to all ACR V1 versions.
707 *
708 * This includes the LS blob, HS ucode loading blob, and HS bootloader.
709 *
710 * The HS ucode unload blob is only used on dGPU if the WPR region is variable.
711 */
712 int
acr_r352_load_blobs(struct acr_r352 * acr,struct nvkm_secboot * sb)713 acr_r352_load_blobs(struct acr_r352 *acr, struct nvkm_secboot *sb)
714 {
715 struct nvkm_subdev *subdev = &sb->subdev;
716 int ret;
717
718 /* Firmware already loaded? */
719 if (acr->firmware_ok)
720 return 0;
721
722 /* Load and prepare the managed falcon's firmwares */
723 ret = acr_r352_prepare_ls_blob(acr, sb);
724 if (ret)
725 return ret;
726
727 /* Load the HS firmware that will load the LS firmwares */
728 if (!acr->load_blob) {
729 ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_load",
730 &acr->load_blob,
731 &acr->load_bl_header, true);
732 if (ret)
733 return ret;
734 }
735
736 /* If the ACR region is dynamically programmed, we need an unload FW */
737 if (sb->wpr_size == 0) {
738 ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_unload",
739 &acr->unload_blob,
740 &acr->unload_bl_header, false);
741 if (ret)
742 return ret;
743 }
744
745 /* Load the HS firmware bootloader */
746 if (!acr->hsbl_blob) {
747 acr->hsbl_blob = nvkm_acr_load_firmware(subdev, "acr/bl", 0);
748 if (IS_ERR(acr->hsbl_blob)) {
749 ret = PTR_ERR(acr->hsbl_blob);
750 acr->hsbl_blob = NULL;
751 return ret;
752 }
753
754 if (acr->base.boot_falcon != NVKM_SECBOOT_FALCON_PMU) {
755 acr->hsbl_unload_blob = nvkm_acr_load_firmware(subdev,
756 "acr/unload_bl", 0);
757 if (IS_ERR(acr->hsbl_unload_blob)) {
758 ret = PTR_ERR(acr->hsbl_unload_blob);
759 acr->hsbl_unload_blob = NULL;
760 return ret;
761 }
762 } else {
763 acr->hsbl_unload_blob = acr->hsbl_blob;
764 }
765 }
766
767 acr->firmware_ok = true;
768 nvkm_debug(&sb->subdev, "LS blob successfully created\n");
769
770 return 0;
771 }
772
773 /**
774 * acr_r352_load() - prepare HS falcon to run the specified blob, mapped.
775 *
776 * Returns the start address to use, or a negative error value.
777 */
778 static int
acr_r352_load(struct nvkm_acr * _acr,struct nvkm_falcon * falcon,struct nvkm_gpuobj * blob,u64 offset)779 acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon,
780 struct nvkm_gpuobj *blob, u64 offset)
781 {
782 struct acr_r352 *acr = acr_r352(_acr);
783 const u32 bl_desc_size = acr->func->hs_bl_desc_size;
784 const struct hsf_load_header *load_hdr;
785 struct fw_bin_header *bl_hdr;
786 struct fw_bl_desc *hsbl_desc;
787 void *bl, *blob_data, *hsbl_code, *hsbl_data;
788 u32 code_size;
789 u8 *bl_desc;
790
791 bl_desc = kzalloc(bl_desc_size, GFP_KERNEL);
792 if (!bl_desc)
793 return -ENOMEM;
794
795 /* Find the bootloader descriptor for our blob and copy it */
796 if (blob == acr->load_blob) {
797 load_hdr = &acr->load_bl_header;
798 bl = acr->hsbl_blob;
799 } else if (blob == acr->unload_blob) {
800 load_hdr = &acr->unload_bl_header;
801 bl = acr->hsbl_unload_blob;
802 } else {
803 nvkm_error(_acr->subdev, "invalid secure boot blob!\n");
804 return -EINVAL;
805 }
806
807 bl_hdr = bl;
808 hsbl_desc = bl + bl_hdr->header_offset;
809 blob_data = bl + bl_hdr->data_offset;
810 hsbl_code = blob_data + hsbl_desc->code_off;
811 hsbl_data = blob_data + hsbl_desc->data_off;
812 code_size = ALIGN(hsbl_desc->code_size, 256);
813
814 /*
815 * Copy HS bootloader data
816 */
817 nvkm_falcon_load_dmem(falcon, hsbl_data, 0x0, hsbl_desc->data_size, 0);
818
819 /* Copy HS bootloader code to end of IMEM */
820 nvkm_falcon_load_imem(falcon, hsbl_code, falcon->code.limit - code_size,
821 code_size, hsbl_desc->start_tag, 0, false);
822
823 /* Generate the BL header */
824 acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset);
825
826 /*
827 * Copy HS BL header where the HS descriptor expects it to be
828 */
829 nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off,
830 bl_desc_size, 0);
831
832 kfree(bl_desc);
833 return hsbl_desc->start_tag << 8;
834 }
835
836 static int
acr_r352_shutdown(struct acr_r352 * acr,struct nvkm_secboot * sb)837 acr_r352_shutdown(struct acr_r352 *acr, struct nvkm_secboot *sb)
838 {
839 struct nvkm_subdev *subdev = &sb->subdev;
840 int i;
841
842 /* Run the unload blob to unprotect the WPR region */
843 if (acr->unload_blob && sb->wpr_set) {
844 int ret;
845
846 nvkm_debug(subdev, "running HS unload blob\n");
847 ret = sb->func->run_blob(sb, acr->unload_blob, sb->halt_falcon);
848 if (ret < 0)
849 return ret;
850 /*
851 * Unload blob will return this error code - it is not an error
852 * and the expected behavior on RM as well
853 */
854 if (ret && ret != 0x1d) {
855 nvkm_error(subdev, "HS unload failed, ret 0x%08x", ret);
856 return -EINVAL;
857 }
858 nvkm_debug(subdev, "HS unload blob completed\n");
859 }
860
861 for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++)
862 acr->falcon_state[i] = NON_SECURE;
863
864 sb->wpr_set = false;
865
866 return 0;
867 }
868
869 /**
870 * Check if the WPR region has been indeed set by the ACR firmware, and
871 * matches where it should be.
872 */
873 static bool
acr_r352_wpr_is_set(const struct acr_r352 * acr,const struct nvkm_secboot * sb)874 acr_r352_wpr_is_set(const struct acr_r352 *acr, const struct nvkm_secboot *sb)
875 {
876 const struct nvkm_subdev *subdev = &sb->subdev;
877 const struct nvkm_device *device = subdev->device;
878 u64 wpr_lo, wpr_hi;
879 u64 wpr_range_lo, wpr_range_hi;
880
881 nvkm_wr32(device, 0x100cd4, 0x2);
882 wpr_lo = (nvkm_rd32(device, 0x100cd4) & ~0xff);
883 wpr_lo <<= 8;
884 nvkm_wr32(device, 0x100cd4, 0x3);
885 wpr_hi = (nvkm_rd32(device, 0x100cd4) & ~0xff);
886 wpr_hi <<= 8;
887
888 if (sb->wpr_size != 0) {
889 wpr_range_lo = sb->wpr_addr;
890 wpr_range_hi = wpr_range_lo + sb->wpr_size;
891 } else {
892 wpr_range_lo = acr->ls_blob->addr;
893 wpr_range_hi = wpr_range_lo + acr->ls_blob->size;
894 }
895
896 return (wpr_lo >= wpr_range_lo && wpr_lo < wpr_range_hi &&
897 wpr_hi > wpr_range_lo && wpr_hi <= wpr_range_hi);
898 }
899
900 static int
acr_r352_bootstrap(struct acr_r352 * acr,struct nvkm_secboot * sb)901 acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb)
902 {
903 const struct nvkm_subdev *subdev = &sb->subdev;
904 unsigned long managed_falcons = acr->base.managed_falcons;
905 int falcon_id;
906 int ret;
907
908 if (sb->wpr_set)
909 return 0;
910
911 /* Make sure all blobs are ready */
912 ret = acr_r352_load_blobs(acr, sb);
913 if (ret)
914 return ret;
915
916 nvkm_debug(subdev, "running HS load blob\n");
917 ret = sb->func->run_blob(sb, acr->load_blob, sb->boot_falcon);
918 /* clear halt interrupt */
919 nvkm_falcon_clear_interrupt(sb->boot_falcon, 0x10);
920 sb->wpr_set = acr_r352_wpr_is_set(acr, sb);
921 if (ret < 0) {
922 return ret;
923 } else if (ret > 0) {
924 nvkm_error(subdev, "HS load failed, ret 0x%08x", ret);
925 return -EINVAL;
926 }
927 nvkm_debug(subdev, "HS load blob completed\n");
928 /* WPR must be set at this point */
929 if (!sb->wpr_set) {
930 nvkm_error(subdev, "ACR blob completed but WPR not set!\n");
931 return -EINVAL;
932 }
933
934 /* Run LS firmwares post_run hooks */
935 for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) {
936 const struct acr_r352_ls_func *func =
937 acr->func->ls_func[falcon_id];
938
939 if (func->post_run) {
940 ret = func->post_run(&acr->base, sb);
941 if (ret)
942 return ret;
943 }
944 }
945
946 return 0;
947 }
948
949 /**
950 * acr_r352_reset_nopmu - dummy reset method when no PMU firmware is loaded
951 *
952 * Reset is done by re-executing secure boot from scratch, with lazy bootstrap
953 * disabled. This has the effect of making all managed falcons ready-to-run.
954 */
955 static int
acr_r352_reset_nopmu(struct acr_r352 * acr,struct nvkm_secboot * sb,unsigned long falcon_mask)956 acr_r352_reset_nopmu(struct acr_r352 *acr, struct nvkm_secboot *sb,
957 unsigned long falcon_mask)
958 {
959 int falcon;
960 int ret;
961
962 /*
963 * Perform secure boot each time we are called on FECS. Since only FECS
964 * and GPCCS are managed and started together, this ought to be safe.
965 */
966 if (!(falcon_mask & BIT(NVKM_SECBOOT_FALCON_FECS)))
967 goto end;
968
969 ret = acr_r352_shutdown(acr, sb);
970 if (ret)
971 return ret;
972
973 ret = acr_r352_bootstrap(acr, sb);
974 if (ret)
975 return ret;
976
977 end:
978 for_each_set_bit(falcon, &falcon_mask, NVKM_SECBOOT_FALCON_END) {
979 acr->falcon_state[falcon] = RESET;
980 }
981 return 0;
982 }
983
984 /*
985 * acr_r352_reset() - execute secure boot from the prepared state
986 *
987 * Load the HS bootloader and ask the falcon to run it. This will in turn
988 * load the HS firmware and run it, so once the falcon stops all the managed
989 * falcons should have their LS firmware loaded and be ready to run.
990 */
991 static int
acr_r352_reset(struct nvkm_acr * _acr,struct nvkm_secboot * sb,unsigned long falcon_mask)992 acr_r352_reset(struct nvkm_acr *_acr, struct nvkm_secboot *sb,
993 unsigned long falcon_mask)
994 {
995 struct acr_r352 *acr = acr_r352(_acr);
996 struct nvkm_msgqueue *queue;
997 int falcon;
998 bool wpr_already_set = sb->wpr_set;
999 int ret;
1000
1001 /* Make sure secure boot is performed */
1002 ret = acr_r352_bootstrap(acr, sb);
1003 if (ret)
1004 return ret;
1005
1006 /* No PMU interface? */
1007 if (!nvkm_secboot_is_managed(sb, _acr->boot_falcon)) {
1008 /* Redo secure boot entirely if it was already done */
1009 if (wpr_already_set)
1010 return acr_r352_reset_nopmu(acr, sb, falcon_mask);
1011 /* Else return the result of the initial invokation */
1012 else
1013 return ret;
1014 }
1015
1016 switch (_acr->boot_falcon) {
1017 case NVKM_SECBOOT_FALCON_PMU:
1018 queue = sb->subdev.device->pmu->queue;
1019 break;
1020 case NVKM_SECBOOT_FALCON_SEC2:
1021 queue = sb->subdev.device->sec2->queue;
1022 break;
1023 default:
1024 return -EINVAL;
1025 }
1026
1027 /* Otherwise just ask the LS firmware to reset the falcon */
1028 for_each_set_bit(falcon, &falcon_mask, NVKM_SECBOOT_FALCON_END)
1029 nvkm_debug(&sb->subdev, "resetting %s falcon\n",
1030 nvkm_secboot_falcon_name[falcon]);
1031 ret = nvkm_msgqueue_acr_boot_falcons(queue, falcon_mask);
1032 if (ret) {
1033 nvkm_error(&sb->subdev, "error during falcon reset: %d\n", ret);
1034 return ret;
1035 }
1036 nvkm_debug(&sb->subdev, "falcon reset done\n");
1037
1038 return 0;
1039 }
1040
1041 static int
acr_r352_fini(struct nvkm_acr * _acr,struct nvkm_secboot * sb,bool suspend)1042 acr_r352_fini(struct nvkm_acr *_acr, struct nvkm_secboot *sb, bool suspend)
1043 {
1044 struct acr_r352 *acr = acr_r352(_acr);
1045
1046 return acr_r352_shutdown(acr, sb);
1047 }
1048
1049 static void
acr_r352_dtor(struct nvkm_acr * _acr)1050 acr_r352_dtor(struct nvkm_acr *_acr)
1051 {
1052 struct acr_r352 *acr = acr_r352(_acr);
1053
1054 nvkm_gpuobj_del(&acr->unload_blob);
1055
1056 if (_acr->boot_falcon != NVKM_SECBOOT_FALCON_PMU)
1057 kfree(acr->hsbl_unload_blob);
1058 kfree(acr->hsbl_blob);
1059 nvkm_gpuobj_del(&acr->load_blob);
1060 nvkm_gpuobj_del(&acr->ls_blob);
1061
1062 kfree(acr);
1063 }
1064
1065 const struct acr_r352_ls_func
1066 acr_r352_ls_fecs_func = {
1067 .load = acr_ls_ucode_load_fecs,
1068 .generate_bl_desc = acr_r352_generate_flcn_bl_desc,
1069 .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc),
1070 };
1071
1072 const struct acr_r352_ls_func
1073 acr_r352_ls_gpccs_func = {
1074 .load = acr_ls_ucode_load_gpccs,
1075 .generate_bl_desc = acr_r352_generate_flcn_bl_desc,
1076 .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc),
1077 /* GPCCS will be loaded using PRI */
1078 .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD,
1079 };
1080
1081
1082
1083 /**
1084 * struct acr_r352_pmu_bl_desc - PMU DMEM bootloader descriptor
1085 * @dma_idx: DMA context to be used by BL while loading code/data
1086 * @code_dma_base: 256B-aligned Physical FB Address where code is located
1087 * @total_code_size: total size of the code part in the ucode
1088 * @code_size_to_load: size of the code part to load in PMU IMEM.
1089 * @code_entry_point: entry point in the code.
1090 * @data_dma_base: Physical FB address where data part of ucode is located
1091 * @data_size: Total size of the data portion.
1092 * @overlay_dma_base: Physical Fb address for resident code present in ucode
1093 * @argc: Total number of args
1094 * @argv: offset where args are copied into PMU's DMEM.
1095 *
1096 * Structure used by the PMU bootloader to load the rest of the code
1097 */
1098 struct acr_r352_pmu_bl_desc {
1099 u32 dma_idx;
1100 u32 code_dma_base;
1101 u32 code_size_total;
1102 u32 code_size_to_load;
1103 u32 code_entry_point;
1104 u32 data_dma_base;
1105 u32 data_size;
1106 u32 overlay_dma_base;
1107 u32 argc;
1108 u32 argv;
1109 u16 code_dma_base1;
1110 u16 data_dma_base1;
1111 u16 overlay_dma_base1;
1112 };
1113
1114 /**
1115 * acr_r352_generate_pmu_bl_desc() - populate a DMEM BL descriptor for PMU LS image
1116 *
1117 */
1118 static void
acr_r352_generate_pmu_bl_desc(const struct nvkm_acr * acr,const struct ls_ucode_img * img,u64 wpr_addr,void * _desc)1119 acr_r352_generate_pmu_bl_desc(const struct nvkm_acr *acr,
1120 const struct ls_ucode_img *img, u64 wpr_addr,
1121 void *_desc)
1122 {
1123 const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
1124 const struct nvkm_pmu *pmu = acr->subdev->device->pmu;
1125 struct acr_r352_pmu_bl_desc *desc = _desc;
1126 u64 base;
1127 u64 addr_code;
1128 u64 addr_data;
1129 u32 addr_args;
1130
1131 base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
1132 addr_code = (base + pdesc->app_resident_code_offset) >> 8;
1133 addr_data = (base + pdesc->app_resident_data_offset) >> 8;
1134 addr_args = pmu->falcon->data.limit;
1135 addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;
1136
1137 desc->dma_idx = FALCON_DMAIDX_UCODE;
1138 desc->code_dma_base = lower_32_bits(addr_code);
1139 desc->code_dma_base1 = upper_32_bits(addr_code);
1140 desc->code_size_total = pdesc->app_size;
1141 desc->code_size_to_load = pdesc->app_resident_code_size;
1142 desc->code_entry_point = pdesc->app_imem_entry;
1143 desc->data_dma_base = lower_32_bits(addr_data);
1144 desc->data_dma_base1 = upper_32_bits(addr_data);
1145 desc->data_size = pdesc->app_resident_data_size;
1146 desc->overlay_dma_base = lower_32_bits(addr_code);
1147 desc->overlay_dma_base1 = upper_32_bits(addr_code);
1148 desc->argc = 1;
1149 desc->argv = addr_args;
1150 }
1151
1152 static const struct acr_r352_ls_func
1153 acr_r352_ls_pmu_func = {
1154 .load = acr_ls_ucode_load_pmu,
1155 .generate_bl_desc = acr_r352_generate_pmu_bl_desc,
1156 .bl_desc_size = sizeof(struct acr_r352_pmu_bl_desc),
1157 .post_run = acr_ls_pmu_post_run,
1158 };
1159
1160 const struct acr_r352_func
1161 acr_r352_func = {
1162 .fixup_hs_desc = acr_r352_fixup_hs_desc,
1163 .generate_hs_bl_desc = acr_r352_generate_hs_bl_desc,
1164 .hs_bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc),
1165 .ls_ucode_img_load = acr_r352_ls_ucode_img_load,
1166 .ls_fill_headers = acr_r352_ls_fill_headers,
1167 .ls_write_wpr = acr_r352_ls_write_wpr,
1168 .ls_func = {
1169 [NVKM_SECBOOT_FALCON_FECS] = &acr_r352_ls_fecs_func,
1170 [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r352_ls_gpccs_func,
1171 [NVKM_SECBOOT_FALCON_PMU] = &acr_r352_ls_pmu_func,
1172 },
1173 };
1174
1175 static const struct nvkm_acr_func
1176 acr_r352_base_func = {
1177 .dtor = acr_r352_dtor,
1178 .fini = acr_r352_fini,
1179 .load = acr_r352_load,
1180 .reset = acr_r352_reset,
1181 };
1182
1183 struct nvkm_acr *
acr_r352_new_(const struct acr_r352_func * func,enum nvkm_secboot_falcon boot_falcon,unsigned long managed_falcons)1184 acr_r352_new_(const struct acr_r352_func *func,
1185 enum nvkm_secboot_falcon boot_falcon,
1186 unsigned long managed_falcons)
1187 {
1188 struct acr_r352 *acr;
1189 int i;
1190
1191 /* Check that all requested falcons are supported */
1192 for_each_set_bit(i, &managed_falcons, NVKM_SECBOOT_FALCON_END) {
1193 if (!func->ls_func[i])
1194 return ERR_PTR(-ENOTSUPP);
1195 }
1196
1197 acr = kzalloc(sizeof(*acr), GFP_KERNEL);
1198 if (!acr)
1199 return ERR_PTR(-ENOMEM);
1200
1201 acr->base.boot_falcon = boot_falcon;
1202 acr->base.managed_falcons = managed_falcons;
1203 acr->base.func = &acr_r352_base_func;
1204 acr->func = func;
1205
1206 return &acr->base;
1207 }
1208
1209 struct nvkm_acr *
acr_r352_new(unsigned long managed_falcons)1210 acr_r352_new(unsigned long managed_falcons)
1211 {
1212 return acr_r352_new_(&acr_r352_func, NVKM_SECBOOT_FALCON_PMU,
1213 managed_falcons);
1214 }
1215
