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/Linux-v4.19/drivers/clk/meson/
Daxg-audio.c24 #define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags) \ argument
39 #define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \ argument
56 #define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \ argument
104 #define AXG_MST_MCLK_MUX(_name, _reg) \ argument
119 #define AXG_MST_MCLK_DIV(_name, _reg) \ argument
134 #define AXG_MST_MCLK_GATE(_name, _reg) \ argument
150 #define AXG_MST_SCLK_PRE_EN(_name, _reg) \ argument
161 #define AXG_AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ argument
185 #define AXG_MST_SCLK_DIV(_name, _reg) \ argument
197 #define AXG_MST_SCLK_POST_EN(_name, _reg) \ argument
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/Linux-v4.19/arch/mips/include/asm/mach-pic32/
Dpic32.h22 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument
23 #define PIC32_SET(_reg) ((_reg) + 0x08) argument
24 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
/Linux-v4.19/drivers/regulator/
Dmc13xxx.h59 #define MC13xxx_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages, _ops) \ argument
77 #define MC13xxx_FIXED_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
92 #define MC13xxx_GPO_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
107 #define MC13xxx_DEFINE_SW(_name, _reg, _vsel_reg, _voltages, ops) \ argument
109 #define MC13xxx_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages, ops) \ argument
/Linux-v4.19/arch/arm/mach-mmp/
Dclock.h29 #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ argument
37 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ argument
45 #define APMU_CLK(_name, _reg, _eval, _rate) \ argument
53 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ argument
/Linux-v4.19/drivers/clk/zte/
Dclk.h40 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
55 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
63 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
101 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
117 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
125 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
150 #define AUDIO_DIV(_id, _name, _parent, _reg) \ argument
/Linux-v4.19/drivers/clk/sunxi-ng/
Dccu_div.h95 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
112 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
121 _reg, \ argument
138 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
147 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
157 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
172 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
Dccu_mp.h42 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
63 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
82 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
111 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
Dccu_nm.h45 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
68 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
93 _reg, _min_rate, \ argument
118 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
Dccu_mux.h51 _reg, _shift, _width, _gate, \ argument
65 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
71 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
/Linux-v4.19/drivers/clk/actions/
Dowl-gate.h27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
Dowl-pll.h38 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
51 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
66 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
38 #define OWL_DIVIDER(_struct, _name, _parent, _reg, \ argument
Dowl-factor.h35 #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ argument
44 #define OWL_FACTOR(_struct, _name, _parent, _reg, \ argument
/Linux-v4.19/drivers/reset/sti/
Dreset-stih407.c61 #define STIH407_SRST_CORE(_reg, _bit) \ argument
64 #define STIH407_SRST_SBC(_reg, _bit) \ argument
67 #define STIH407_SRST_LPM(_reg, _bit) \ argument
/Linux-v4.19/drivers/clk/sprd/
Dgate.h21 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
37 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
43 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
Dcomposite.h21 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
36 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
Dpll.h64 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
86 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
93 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
Dmux.h40 _reg, _shift, _width, \ argument
54 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
/Linux-v4.19/drivers/clk/pistachio/
Dclk.h22 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
42 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
62 #define DIV(_id, _name, _pname, _reg, _width) \ argument
72 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
122 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
133 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
/Linux-v4.19/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.h33 #define A6XX_PROTECT_RW(_reg, _len) \ argument
42 #define A6XX_PROTECT_RDONLY(_reg, _len) \ argument
/Linux-v4.19/include/linux/
Dbitfield.h52 #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ argument
101 #define FIELD_GET(_mask, _reg) \ argument
/Linux-v4.19/drivers/net/ethernet/amd/xgbe/
Dxgbe-common.h1442 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1445 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument
1450 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1453 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument
1466 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ argument
1470 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ argument
1475 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ argument
1479 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ argument
1492 #define XGMAC_DMA_IOREAD(_channel, _reg) \ argument
1495 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ argument
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/Linux-v4.19/drivers/i2c/busses/
Di2c-brcmstb.c180 #define __bsc_readl(_reg) ioread32be(_reg) argument
181 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) argument
183 #define __bsc_readl(_reg) ioread32(_reg) argument
184 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) argument
187 #define bsc_readl(_dev, _reg) \ argument
190 #define bsc_writel(_dev, _val, _reg) \ argument
/Linux-v4.19/drivers/net/ethernet/freescale/fs_enet/
Dmac-fec.c62 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) argument
65 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) argument
68 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) argument
71 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v)) argument

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