1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
3
4 #define _HCI_HAL_INIT_C_
5
6 #include "../include/osdep_service.h"
7 #include "../include/drv_types.h"
8 #include "../include/rtw_efuse.h"
9
10 #include "../include/rtl8188e_hal.h"
11 #include "../include/rtl8188e_led.h"
12 #include "../include/rtw_iol.h"
13 #include "../include/usb_ops.h"
14 #include "../include/usb_osintf.h"
15
16 #define HAL_MAC_ENABLE 1
17 #define HAL_BB_ENABLE 1
18 #define HAL_RF_ENABLE 1
19
_ConfigNormalChipOutEP_8188E(struct adapter * adapt,u8 NumOutPipe)20 static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
21 {
22 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
23
24 switch (NumOutPipe) {
25 case 3:
26 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
27 haldata->OutEpNumber = 3;
28 break;
29 case 2:
30 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
31 haldata->OutEpNumber = 2;
32 break;
33 case 1:
34 haldata->OutEpQueueSel = TX_SELE_HQ;
35 haldata->OutEpNumber = 1;
36 break;
37 default:
38 break;
39 }
40 DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
41 }
42
HalUsbSetQueuePipeMapping8188EUsb(struct adapter * adapt,u8 NumInPipe,u8 NumOutPipe)43 static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
44 {
45 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
46 bool result = false;
47
48 _ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
49
50 /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
51 if (1 == haldata->OutEpNumber) {
52 if (1 != NumInPipe)
53 return result;
54 }
55
56 /* All config other than above support one Bulk IN and one Interrupt IN. */
57
58 result = Hal_MappingOutPipe(adapt, NumOutPipe);
59
60 return result;
61 }
62
rtl8188eu_interface_configure(struct adapter * adapt)63 static void rtl8188eu_interface_configure(struct adapter *adapt)
64 {
65 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
66 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt);
67
68 if (pdvobjpriv->ishighspeed)
69 haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/* 512 bytes */
70 else
71 haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/* 64 bytes */
72
73 haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
74
75 haldata->UsbTxAggMode = 1;
76 haldata->UsbTxAggDescNum = 0x6; /* only 4 bits */
77
78 haldata->UsbRxAggMode = USB_RX_AGG_DMA;/* USB_RX_AGG_DMA; */
79 haldata->UsbRxAggBlockCount = 8; /* unit : 512b */
80 haldata->UsbRxAggBlockTimeout = 0x6;
81 haldata->UsbRxAggPageCount = 48; /* uint :128 b 0x0A; 10 = MAX_RX_DMA_BUFFER_SIZE/2/haldata->UsbBulkOutSize */
82 haldata->UsbRxAggPageTimeout = 0x4; /* 6, absolute time = 34ms/(2^6) */
83
84 HalUsbSetQueuePipeMapping8188EUsb(adapt,
85 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
86 }
87
rtl8188eu_InitPowerOn(struct adapter * adapt)88 static u32 rtl8188eu_InitPowerOn(struct adapter *adapt)
89 {
90 u16 value16;
91 /* HW Power on sequence */
92 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
93 if (haldata->bMacPwrCtrlOn)
94 return _SUCCESS;
95
96 if (!HalPwrSeqCmdParsing(adapt, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) {
97 DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
98 return _FAIL;
99 }
100
101 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
102 /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
103 rtw_write16(adapt, REG_CR, 0x00); /* suggseted by zhouzhou, by page, 20111230 */
104
105 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
106 value16 = rtw_read16(adapt, REG_CR);
107 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
108 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
109 /* for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
110
111 rtw_write16(adapt, REG_CR, value16);
112 haldata->bMacPwrCtrlOn = true;
113
114 return _SUCCESS;
115 }
116
117 /* Shall USB interface init this? */
_InitInterrupt(struct adapter * Adapter)118 static void _InitInterrupt(struct adapter *Adapter)
119 {
120 u32 imr, imr_ex;
121 u8 usb_opt;
122 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
123
124 /* HISR write one to clear */
125 rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
126 /* HIMR - */
127 imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
128 rtw_write32(Adapter, REG_HIMR_88E, imr);
129 haldata->IntrMask[0] = imr;
130
131 imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
132 rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
133 haldata->IntrMask[1] = imr_ex;
134
135 /* REG_USB_SPECIAL_OPTION - BIT(4) */
136 /* 0; Use interrupt endpoint to upload interrupt pkt */
137 /* 1; Use bulk endpoint to upload interrupt pkt, */
138 usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
139
140 if (!adapter_to_dvobj(Adapter)->ishighspeed)
141 usb_opt = usb_opt & (~INT_BULK_SEL);
142 else
143 usb_opt = usb_opt | (INT_BULK_SEL);
144
145 rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
146 }
147
_InitQueueReservedPage(struct adapter * Adapter)148 static void _InitQueueReservedPage(struct adapter *Adapter)
149 {
150 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
151 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
152 u32 numHQ = 0;
153 u32 numLQ = 0;
154 u32 numNQ = 0;
155 u32 numPubQ;
156 u32 value32;
157 u8 value8;
158 bool bWiFiConfig = pregistrypriv->wifi_spec;
159
160 if (bWiFiConfig) {
161 if (haldata->OutEpQueueSel & TX_SELE_HQ)
162 numHQ = 0x29;
163
164 if (haldata->OutEpQueueSel & TX_SELE_LQ)
165 numLQ = 0x1C;
166
167 /* NOTE: This step shall be proceed before writting REG_RQPN. */
168 if (haldata->OutEpQueueSel & TX_SELE_NQ)
169 numNQ = 0x1C;
170 value8 = (u8)_NPQ(numNQ);
171 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
172
173 numPubQ = 0xA8 - numHQ - numLQ - numNQ;
174
175 /* TX DMA */
176 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
177 rtw_write32(Adapter, REG_RQPN, value32);
178 } else {
179 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */
180 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0d);
181 rtw_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */
182 }
183 }
184
_InitTxBufferBoundary(struct adapter * Adapter,u8 txpktbuf_bndy)185 static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
186 {
187 rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
188 rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
189 rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
190 rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
191 rtw_write8(Adapter, REG_TDECTRL + 1, txpktbuf_bndy);
192 }
193
_InitPageBoundary(struct adapter * Adapter)194 static void _InitPageBoundary(struct adapter *Adapter)
195 {
196 /* RX Page Boundary */
197 /* */
198 u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E - 1;
199
200 rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
201 }
202
_InitNormalChipRegPriority(struct adapter * Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)203 static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
204 u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
205 u16 hiQ)
206 {
207 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
208
209 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
210 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
211 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
212
213 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
214 }
215
_InitNormalChipOneOutEpPriority(struct adapter * Adapter)216 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
217 {
218 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
219
220 u16 value = 0;
221 switch (haldata->OutEpQueueSel) {
222 case TX_SELE_HQ:
223 value = QUEUE_HIGH;
224 break;
225 case TX_SELE_LQ:
226 value = QUEUE_LOW;
227 break;
228 case TX_SELE_NQ:
229 value = QUEUE_NORMAL;
230 break;
231 default:
232 break;
233 }
234 _InitNormalChipRegPriority(Adapter, value, value, value, value,
235 value, value);
236 }
237
_InitNormalChipTwoOutEpPriority(struct adapter * Adapter)238 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
239 {
240 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
241 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
242 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
243 u16 valueHi = 0;
244 u16 valueLow = 0;
245
246 switch (haldata->OutEpQueueSel) {
247 case (TX_SELE_HQ | TX_SELE_LQ):
248 valueHi = QUEUE_HIGH;
249 valueLow = QUEUE_LOW;
250 break;
251 case (TX_SELE_NQ | TX_SELE_LQ):
252 valueHi = QUEUE_NORMAL;
253 valueLow = QUEUE_LOW;
254 break;
255 case (TX_SELE_HQ | TX_SELE_NQ):
256 valueHi = QUEUE_HIGH;
257 valueLow = QUEUE_NORMAL;
258 break;
259 default:
260 break;
261 }
262
263 if (!pregistrypriv->wifi_spec) {
264 beQ = valueLow;
265 bkQ = valueLow;
266 viQ = valueHi;
267 voQ = valueHi;
268 mgtQ = valueHi;
269 hiQ = valueHi;
270 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
271 beQ = valueLow;
272 bkQ = valueHi;
273 viQ = valueHi;
274 voQ = valueLow;
275 mgtQ = valueHi;
276 hiQ = valueHi;
277 }
278 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
279 }
280
_InitNormalChipThreeOutEpPriority(struct adapter * Adapter)281 static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
282 {
283 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
284 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
285
286 if (!pregistrypriv->wifi_spec) {/* typical setting */
287 beQ = QUEUE_LOW;
288 bkQ = QUEUE_LOW;
289 viQ = QUEUE_NORMAL;
290 voQ = QUEUE_HIGH;
291 mgtQ = QUEUE_HIGH;
292 hiQ = QUEUE_HIGH;
293 } else {/* for WMM */
294 beQ = QUEUE_LOW;
295 bkQ = QUEUE_NORMAL;
296 viQ = QUEUE_NORMAL;
297 voQ = QUEUE_HIGH;
298 mgtQ = QUEUE_HIGH;
299 hiQ = QUEUE_HIGH;
300 }
301 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
302 }
303
_InitQueuePriority(struct adapter * Adapter)304 static void _InitQueuePriority(struct adapter *Adapter)
305 {
306 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
307
308 switch (haldata->OutEpNumber) {
309 case 1:
310 _InitNormalChipOneOutEpPriority(Adapter);
311 break;
312 case 2:
313 _InitNormalChipTwoOutEpPriority(Adapter);
314 break;
315 case 3:
316 _InitNormalChipThreeOutEpPriority(Adapter);
317 break;
318 default:
319 break;
320 }
321 }
322
_InitNetworkType(struct adapter * Adapter)323 static void _InitNetworkType(struct adapter *Adapter)
324 {
325 u32 value32;
326
327 value32 = rtw_read32(Adapter, REG_CR);
328 /* TODO: use the other function to set network type */
329 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
330
331 rtw_write32(Adapter, REG_CR, value32);
332 }
333
_InitTransferPageSize(struct adapter * Adapter)334 static void _InitTransferPageSize(struct adapter *Adapter)
335 {
336 /* Tx page size is always 128. */
337
338 u8 value8;
339 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
340 rtw_write8(Adapter, REG_PBP, value8);
341 }
342
_InitDriverInfoSize(struct adapter * Adapter,u8 drvInfoSize)343 static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
344 {
345 rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
346 }
347
_InitWMACSetting(struct adapter * Adapter)348 static void _InitWMACSetting(struct adapter *Adapter)
349 {
350 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
351
352 haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
353 RCR_CBSSID_DATA | RCR_CBSSID_BCN |
354 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
355 RCR_APP_MIC | RCR_APP_PHYSTS;
356
357 /* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
358 rtw_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
359
360 /* Accept all multicast address */
361 rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
362 rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
363 }
364
_InitAdaptiveCtrl(struct adapter * Adapter)365 static void _InitAdaptiveCtrl(struct adapter *Adapter)
366 {
367 u16 value16;
368 u32 value32;
369
370 /* Response Rate Set */
371 value32 = rtw_read32(Adapter, REG_RRSR);
372 value32 &= ~RATE_BITMAP_ALL;
373 value32 |= RATE_RRSR_CCK_ONLY_1M;
374 rtw_write32(Adapter, REG_RRSR, value32);
375
376 /* CF-END Threshold */
377
378 /* SIFS (used in NAV) */
379 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
380 rtw_write16(Adapter, REG_SPEC_SIFS, value16);
381
382 /* Retry Limit */
383 value16 = _LRL(0x30) | _SRL(0x30);
384 rtw_write16(Adapter, REG_RL, value16);
385 }
386
_InitEDCA(struct adapter * Adapter)387 static void _InitEDCA(struct adapter *Adapter)
388 {
389 /* Set Spec SIFS (used in NAV) */
390 rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
391 rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
392
393 /* Set SIFS for CCK */
394 rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
395
396 /* Set SIFS for OFDM */
397 rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
398
399 /* TXOP */
400 rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
401 rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
402 rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
403 rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
404 }
405
_InitBeaconMaxError(struct adapter * Adapter,bool InfraMode)406 static void _InitBeaconMaxError(struct adapter *Adapter, bool InfraMode)
407 {
408 }
409
_InitHWLed(struct adapter * Adapter)410 static void _InitHWLed(struct adapter *Adapter)
411 {
412 struct led_priv *pledpriv = &Adapter->ledpriv;
413
414 if (pledpriv->LedStrategy != HW_LED)
415 return;
416
417 /* HW led control */
418 /* to do .... */
419 /* must consider cases of antenna diversity/ commbo card/solo card/mini card */
420 }
421
_InitRDGSetting(struct adapter * Adapter)422 static void _InitRDGSetting(struct adapter *Adapter)
423 {
424 rtw_write8(Adapter, REG_RD_CTRL, 0xFF);
425 rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
426 rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
427 }
428
_InitRxSetting(struct adapter * Adapter)429 static void _InitRxSetting(struct adapter *Adapter)
430 {
431 rtw_write32(Adapter, REG_MACID, 0x87654321);
432 rtw_write32(Adapter, 0x0700, 0x87654321);
433 }
434
_InitRetryFunction(struct adapter * Adapter)435 static void _InitRetryFunction(struct adapter *Adapter)
436 {
437 u8 value8;
438
439 value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
440 value8 |= EN_AMPDU_RTY_NEW;
441 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
442
443 /* Set ACK timeout */
444 rtw_write8(Adapter, REG_ACKTO, 0x40);
445 }
446
447 /*-----------------------------------------------------------------------------
448 * Function: usb_AggSettingTxUpdate()
449 *
450 * Overview: Separate TX/RX parameters update independent for TP detection and
451 * dynamic TX/RX aggreagtion parameters update.
452 *
453 * Input: struct adapter *
454 *
455 * Output/Return: NONE
456 *
457 * Revised History:
458 * When Who Remark
459 * 12/10/2010 MHC Separate to smaller function.
460 *
461 *---------------------------------------------------------------------------*/
usb_AggSettingTxUpdate(struct adapter * Adapter)462 static void usb_AggSettingTxUpdate(struct adapter *Adapter)
463 {
464 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
465 u32 value32;
466
467 if (Adapter->registrypriv.wifi_spec)
468 haldata->UsbTxAggMode = false;
469
470 if (haldata->UsbTxAggMode) {
471 value32 = rtw_read32(Adapter, REG_TDECTRL);
472 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
473 value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
474
475 rtw_write32(Adapter, REG_TDECTRL, value32);
476 }
477 } /* usb_AggSettingTxUpdate */
478
479 /*-----------------------------------------------------------------------------
480 * Function: usb_AggSettingRxUpdate()
481 *
482 * Overview: Separate TX/RX parameters update independent for TP detection and
483 * dynamic TX/RX aggreagtion parameters update.
484 *
485 * Input: struct adapter *
486 *
487 * Output/Return: NONE
488 *
489 * Revised History:
490 * When Who Remark
491 * 12/10/2010 MHC Separate to smaller function.
492 *
493 *---------------------------------------------------------------------------*/
494 static void
usb_AggSettingRxUpdate(struct adapter * Adapter)495 usb_AggSettingRxUpdate(
496 struct adapter *Adapter
497 )
498 {
499 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
500 u8 valueDMA;
501 u8 valueUSB;
502
503 valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
504 valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
505
506 switch (haldata->UsbRxAggMode) {
507 case USB_RX_AGG_DMA:
508 valueDMA |= RXDMA_AGG_EN;
509 valueUSB &= ~USB_AGG_EN;
510 break;
511 case USB_RX_AGG_USB:
512 valueDMA &= ~RXDMA_AGG_EN;
513 valueUSB |= USB_AGG_EN;
514 break;
515 case USB_RX_AGG_MIX:
516 valueDMA |= RXDMA_AGG_EN;
517 valueUSB |= USB_AGG_EN;
518 break;
519 case USB_RX_AGG_DISABLE:
520 default:
521 valueDMA &= ~RXDMA_AGG_EN;
522 valueUSB &= ~USB_AGG_EN;
523 break;
524 }
525
526 rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
527 rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
528
529 switch (haldata->UsbRxAggMode) {
530 case USB_RX_AGG_DMA:
531 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
532 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH + 1, haldata->UsbRxAggPageTimeout);
533 break;
534 case USB_RX_AGG_USB:
535 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
536 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
537 break;
538 case USB_RX_AGG_MIX:
539 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
540 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH + 1, (haldata->UsbRxAggPageTimeout & 0x1F));/* 0x280[12:8] */
541 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
542 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
543 break;
544 case USB_RX_AGG_DISABLE:
545 default:
546 /* TODO: */
547 break;
548 }
549
550 switch (PBP_128) {
551 case PBP_128:
552 haldata->HwRxPageSize = 128;
553 break;
554 case PBP_64:
555 haldata->HwRxPageSize = 64;
556 break;
557 case PBP_256:
558 haldata->HwRxPageSize = 256;
559 break;
560 case PBP_512:
561 haldata->HwRxPageSize = 512;
562 break;
563 case PBP_1024:
564 haldata->HwRxPageSize = 1024;
565 break;
566 default:
567 break;
568 }
569 } /* usb_AggSettingRxUpdate */
570
InitUsbAggregationSetting(struct adapter * Adapter)571 static void InitUsbAggregationSetting(struct adapter *Adapter)
572 {
573 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
574
575 /* Tx aggregation setting */
576 usb_AggSettingTxUpdate(Adapter);
577
578 /* Rx aggregation setting */
579 usb_AggSettingRxUpdate(Adapter);
580
581 /* 201/12/10 MH Add for USB agg mode dynamic switch. */
582 haldata->UsbRxHighSpeedMode = false;
583 }
584
_InitOperationMode(struct adapter * Adapter)585 static void _InitOperationMode(struct adapter *Adapter)
586 {
587 }
588
_InitBeaconParameters(struct adapter * Adapter)589 static void _InitBeaconParameters(struct adapter *Adapter)
590 {
591 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
592
593 rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
594
595 /* TODO: Remove these magic number */
596 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */
597 rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/* 5ms */
598 rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /* 2ms */
599
600 /* Suggested by designer timchen. Change beacon AIFS to the largest number */
601 /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
602 rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
603
604 haldata->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
605 haldata->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
606 haldata->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL + 2);
607 haldata->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT + 2);
608 haldata->RegCR_1 = rtw_read8(Adapter, REG_CR + 1);
609 }
610
_BeaconFunctionEnable(struct adapter * Adapter,bool Enable,bool Linked)611 static void _BeaconFunctionEnable(struct adapter *Adapter,
612 bool Enable, bool Linked)
613 {
614 rtw_write8(Adapter, REG_BCN_CTRL, (BIT(4) | BIT(3) | BIT(1)));
615
616 rtw_write8(Adapter, REG_RD_CTRL + 1, 0x6F);
617 }
618
619 /* Set CCK and OFDM Block "ON" */
_BBTurnOnBlock(struct adapter * Adapter)620 static void _BBTurnOnBlock(struct adapter *Adapter)
621 {
622 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
623 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
624 }
625
626 enum {
627 Antenna_Lfet = 1,
628 Antenna_Right = 2,
629 };
630
_InitAntenna_Selection(struct adapter * Adapter)631 static void _InitAntenna_Selection(struct adapter *Adapter)
632 {
633 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
634
635 if (haldata->AntDivCfg == 0)
636 return;
637 DBG_88E("==> %s ....\n", __func__);
638
639 rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0) | BIT(23));
640 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01);
641
642 if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
643 haldata->CurAntenna = Antenna_A;
644 else
645 haldata->CurAntenna = Antenna_B;
646 DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
647 }
648
649 /*-----------------------------------------------------------------------------
650 * Function: HwSuspendModeEnable92Cu()
651 *
652 * Overview: HW suspend mode switch.
653 *
654 * Input: NONE
655 *
656 * Output: NONE
657 *
658 * Return: NONE
659 *
660 * Revised History:
661 * When Who Remark
662 * 08/23/2010 MHC HW suspend mode switch test..
663 *---------------------------------------------------------------------------*/
RfOnOffDetect(struct adapter * adapt)664 enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
665 {
666 u8 val8;
667 enum rt_rf_power_state rfpowerstate = rf_off;
668
669 if (adapt->pwrctrlpriv.bHWPowerdown) {
670 val8 = rtw_read8(adapt, REG_HSISR);
671 DBG_88E("pwrdown, 0x5c(BIT(7))=%02x\n", val8);
672 rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on;
673 } else { /* rf on/off */
674 rtw_write8(adapt, REG_MAC_PINMUX_CFG, rtw_read8(adapt, REG_MAC_PINMUX_CFG) & ~(BIT(3)));
675 val8 = rtw_read8(adapt, REG_GPIO_IO_SEL);
676 DBG_88E("GPIO_IN=%02x\n", val8);
677 rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off;
678 }
679 return rfpowerstate;
680 } /* HalDetectPwrDownMode */
681
rtl8188eu_hal_init(struct adapter * Adapter)682 static u32 rtl8188eu_hal_init(struct adapter *Adapter)
683 {
684 u8 value8 = 0;
685 u16 value16;
686 u8 txpktbuf_bndy;
687 u32 status = _SUCCESS;
688 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
689 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
690 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
691 u32 init_start_time = jiffies;
692
693 #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
694
695 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
696
697 if (Adapter->pwrctrlpriv.bkeepfwalive) {
698 _ps_open_RF(Adapter);
699
700 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
701 PHY_IQCalibrate_8188E(Adapter, true);
702 } else {
703 PHY_IQCalibrate_8188E(Adapter, false);
704 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
705 }
706
707 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
708 PHY_LCCalibrate_8188E(Adapter);
709
710 goto exit;
711 }
712
713 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
714 status = rtl8188eu_InitPowerOn(Adapter);
715 if (status == _FAIL)
716 goto exit;
717
718 /* Save target channel */
719 haldata->CurrentChannel = 6;/* default set to 6 */
720
721 if (pwrctrlpriv->reg_rfoff) {
722 pwrctrlpriv->rf_pwrstate = rf_off;
723 }
724
725 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
726 /* HW GPIO pin. Before PHY_RFConfig8192C. */
727 /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
728
729 if (!pregistrypriv->wifi_spec) {
730 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
731 } else {
732 /* for WMM */
733 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
734 }
735
736 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
737 _InitQueueReservedPage(Adapter);
738 _InitQueuePriority(Adapter);
739 _InitPageBoundary(Adapter);
740 _InitTransferPageSize(Adapter);
741
742 _InitTxBufferBoundary(Adapter, 0);
743
744 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
745 if (Adapter->registrypriv.mp_mode == 1) {
746 _InitRxSetting(Adapter);
747 Adapter->bFWReady = false;
748 haldata->fw_ractrl = false;
749 } else {
750 status = rtl8188e_FirmwareDownload(Adapter);
751
752 if (status != _SUCCESS) {
753 DBG_88E("%s: Download Firmware failed!!\n", __func__);
754 Adapter->bFWReady = false;
755 haldata->fw_ractrl = false;
756 return status;
757 } else {
758 Adapter->bFWReady = true;
759 haldata->fw_ractrl = false;
760 }
761 }
762 rtl8188e_InitializeFirmwareVars(Adapter);
763
764 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
765 #if (HAL_MAC_ENABLE == 1)
766 status = PHY_MACConfig8188E(Adapter);
767 if (status == _FAIL) {
768 DBG_88E(" ### Failed to init MAC ......\n ");
769 goto exit;
770 }
771 #endif
772
773 /* */
774 /* d. Initialize BB related configurations. */
775 /* */
776 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
777 #if (HAL_BB_ENABLE == 1)
778 status = PHY_BBConfig8188E(Adapter);
779 if (status == _FAIL) {
780 DBG_88E(" ### Failed to init BB ......\n ");
781 goto exit;
782 }
783 #endif
784
785 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
786 #if (HAL_RF_ENABLE == 1)
787 status = PHY_RFConfig8188E(Adapter);
788 if (status == _FAIL) {
789 DBG_88E(" ### Failed to init RF ......\n ");
790 goto exit;
791 }
792 #endif
793
794 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
795 status = rtl8188e_iol_efuse_patch(Adapter);
796 if (status == _FAIL) {
797 DBG_88E("%s rtl8188e_iol_efuse_patch failed\n", __func__);
798 goto exit;
799 }
800
801 _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
802
803 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
804 status = InitLLTTable(Adapter, txpktbuf_bndy);
805 if (status == _FAIL)
806 goto exit;
807
808 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
809 /* Get Rx PHY status in order to report RSSI and others. */
810 _InitDriverInfoSize(Adapter, DRVINFO_SZ);
811
812 _InitInterrupt(Adapter);
813 hal_init_macaddr(Adapter);/* set mac_address */
814 _InitNetworkType(Adapter);/* set msr */
815 _InitWMACSetting(Adapter);
816 _InitAdaptiveCtrl(Adapter);
817 _InitEDCA(Adapter);
818 _InitRetryFunction(Adapter);
819 InitUsbAggregationSetting(Adapter);
820 _InitOperationMode(Adapter);/* todo */
821 _InitBeaconParameters(Adapter);
822 _InitBeaconMaxError(Adapter, true);
823
824 /* */
825 /* Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
826 /* Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */
827 /* */
828 /* Enable MACTXEN/MACRXEN block */
829 value16 = rtw_read16(Adapter, REG_CR);
830 value16 |= (MACTXEN | MACRXEN);
831 rtw_write8(Adapter, REG_CR, value16);
832
833 if (haldata->bRDGEnable)
834 _InitRDGSetting(Adapter);
835
836 /* Enable TX Report */
837 /* Enable Tx Report Timer */
838 value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
839 rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8 | BIT(1) | BIT(0)));
840 /* Set MAX RPT MACID */
841 rtw_write8(Adapter, REG_TX_RPT_CTRL + 1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
842 /* Tx RPT Timer. Unit: 32us */
843 rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
844
845 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
846
847 rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
848 rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
849
850 _InitHWLed(Adapter);
851
852 /* Keep RfRegChnlVal for later use. */
853 haldata->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
854 haldata->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
855
856 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
857 _BBTurnOnBlock(Adapter);
858
859 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
860 invalidate_cam_all(Adapter);
861
862 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
863 /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */
864 PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel);
865
866 /* Move by Neo for USB SS to below setp */
867 /* _RfPowerSave(Adapter); */
868
869 _InitAntenna_Selection(Adapter);
870
871 /* */
872 /* Disable BAR, suggested by Scott */
873 /* 2010.04.09 add by hpfan */
874 /* */
875 rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
876
877 /* HW SEQ CTRL */
878 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
879 rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
880
881 if (pregistrypriv->wifi_spec)
882 rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
883
884 /* Nav limit , suggest by scott */
885 rtw_write8(Adapter, 0x652, 0x0);
886
887 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
888 rtl8188e_InitHalDm(Adapter);
889
890 if (Adapter->registrypriv.mp_mode == 1) {
891 Adapter->mppriv.channel = haldata->CurrentChannel;
892 MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
893 } else {
894 /* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */
895 /* and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */
896 /* call initstruct adapter. May cause some problem?? */
897 /* Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */
898 /* in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */
899 /* is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */
900 /* Added by tynli. 2010.03.30. */
901 pwrctrlpriv->rf_pwrstate = rf_on;
902
903 /* enable Tx report. */
904 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL + 1, 0x0F);
905
906 /* Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
907 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL + 3, 0x01);/* Pretx_en, for WEP/TKIP SEC */
908
909 /* tynli_test_tx_report. */
910 rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
911
912 /* enable tx DMA to drop the redundate data of packet */
913 rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
914
915 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
916 /* 2010/08/26 MH Merge from 8192CE. */
917 if (pwrctrlpriv->rf_pwrstate == rf_on) {
918 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
919 PHY_IQCalibrate_8188E(Adapter, true);
920 } else {
921 PHY_IQCalibrate_8188E(Adapter, false);
922 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
923 }
924
925 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
926
927 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
928
929 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
930 PHY_LCCalibrate_8188E(Adapter);
931 }
932 }
933
934 /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
935 /* _InitPABias(Adapter); */
936 rtw_write8(Adapter, REG_USB_HRPWM, 0);
937
938 /* ack for xmit mgmt frames. */
939 rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL) | BIT(12));
940
941 exit:
942 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
943
944 DBG_88E("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time));
945
946 return status;
947 }
948
_ps_open_RF(struct adapter * adapt)949 void _ps_open_RF(struct adapter *adapt)
950 {
951 /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
952 /* phy_SsPwrSwitch92CU(adapt, rf_on, 1); */
953 }
954
_ps_close_RF(struct adapter * adapt)955 static void _ps_close_RF(struct adapter *adapt)
956 {
957 /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
958 /* phy_SsPwrSwitch92CU(adapt, rf_off, 1); */
959 }
960
CardDisableRTL8188EU(struct adapter * Adapter)961 static void CardDisableRTL8188EU(struct adapter *Adapter)
962 {
963 u8 val8;
964 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
965
966 /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
967 val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
968 rtw_write8(Adapter, REG_TX_RPT_CTRL, val8 & (~BIT(1)));
969
970 /* stop rx */
971 rtw_write8(Adapter, REG_CR, 0x0);
972
973 /* Run LPS WL RFOFF flow */
974 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
975
976 /* 2. 0x1F[7:0] = 0 turn off RF */
977
978 val8 = rtw_read8(Adapter, REG_MCUFWDL);
979 if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) { /* 8051 RAM code */
980 /* Reset MCU 0x2[10]=0. */
981 val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN + 1);
982 val8 &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
983 rtw_write8(Adapter, REG_SYS_FUNC_EN + 1, val8);
984 }
985
986 /* reset MCU ready status */
987 rtw_write8(Adapter, REG_MCUFWDL, 0);
988
989 /* YJ,add,111212 */
990 /* Disable 32k */
991 val8 = rtw_read8(Adapter, REG_32K_CTRL);
992 rtw_write8(Adapter, REG_32K_CTRL, val8 & (~BIT(0)));
993
994 /* Card disable power action flow */
995 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW);
996
997 /* Reset MCU IO Wrapper */
998 val8 = rtw_read8(Adapter, REG_RSV_CTRL + 1);
999 rtw_write8(Adapter, REG_RSV_CTRL + 1, (val8 & (~BIT(3))));
1000 val8 = rtw_read8(Adapter, REG_RSV_CTRL + 1);
1001 rtw_write8(Adapter, REG_RSV_CTRL + 1, val8 | BIT(3));
1002
1003 /* YJ,test add, 111207. For Power Consumption. */
1004 val8 = rtw_read8(Adapter, GPIO_IN);
1005 rtw_write8(Adapter, GPIO_OUT, val8);
1006 rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */
1007
1008 val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
1009 rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8 << 4));
1010 val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL + 1);
1011 rtw_write8(Adapter, REG_GPIO_IO_SEL + 1, val8 | 0x0F);/* Reg0x43 */
1012 rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */
1013 haldata->bMacPwrCtrlOn = false;
1014 Adapter->bFWReady = false;
1015 }
rtl8192cu_hw_power_down(struct adapter * adapt)1016 static void rtl8192cu_hw_power_down(struct adapter *adapt)
1017 {
1018 /* 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. */
1019 /* Then enable power down control bit of register 0x04 BIT(4) and BIT(15) as 1. */
1020
1021 /* Enable register area 0x0-0xc. */
1022 rtw_write8(adapt, REG_RSV_CTRL, 0x0);
1023 rtw_write16(adapt, REG_APS_FSMCO, 0x8812);
1024 }
1025
rtl8188eu_hal_deinit(struct adapter * Adapter)1026 static u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
1027 {
1028
1029 DBG_88E("==> %s\n", __func__);
1030
1031 rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
1032 rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
1033
1034 DBG_88E("bkeepfwalive(%x)\n", Adapter->pwrctrlpriv.bkeepfwalive);
1035 if (Adapter->pwrctrlpriv.bkeepfwalive) {
1036 _ps_close_RF(Adapter);
1037 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1038 rtl8192cu_hw_power_down(Adapter);
1039 } else {
1040 if (Adapter->hw_init_completed) {
1041 CardDisableRTL8188EU(Adapter);
1042
1043 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1044 rtl8192cu_hw_power_down(Adapter);
1045 }
1046 }
1047 return _SUCCESS;
1048 }
1049
rtl8188eu_inirp_init(struct adapter * Adapter)1050 static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
1051 {
1052 u8 i;
1053 struct recv_buf *precvbuf;
1054 uint status;
1055 struct intf_hdl *pintfhdl = &Adapter->iopriv.intf;
1056 struct recv_priv *precvpriv = &Adapter->recvpriv;
1057 u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
1058
1059 _read_port = pintfhdl->io_ops._read_port;
1060
1061 status = _SUCCESS;
1062
1063 precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1064
1065 /* issue Rx irp to receive data */
1066 precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1067 for (i = 0; i < NR_RECVBUFF; i++) {
1068 if (!_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf)) {
1069 status = _FAIL;
1070 goto exit;
1071 }
1072
1073 precvbuf++;
1074 precvpriv->free_recv_buf_queue_cnt--;
1075 }
1076
1077 exit:
1078 return status;
1079 }
1080
rtl8188eu_inirp_deinit(struct adapter * Adapter)1081 static unsigned int rtl8188eu_inirp_deinit(struct adapter *Adapter)
1082 {
1083 rtw_read_port_cancel(Adapter);
1084
1085 return _SUCCESS;
1086 }
1087
1088 /* */
1089 /* */
1090 /* EEPROM/EFUSE Content Parsing */
1091 /* */
1092 /* */
_ReadLEDSetting(struct adapter * Adapter,u8 * PROMContent,bool AutoloadFail)1093 static void _ReadLEDSetting(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
1094 {
1095 struct led_priv *pledpriv = &Adapter->ledpriv;
1096 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1097
1098 pledpriv->bRegUseLed = true;
1099 pledpriv->LedStrategy = SW_LED_MODE1;
1100 haldata->bLedOpenDrain = true;/* Support Open-drain arrangement for controlling the LED. */
1101 }
1102
Hal_EfuseParsePIDVID_8188EU(struct adapter * adapt,u8 * hwinfo,bool AutoLoadFail)1103 static void Hal_EfuseParsePIDVID_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1104 {
1105 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1106
1107 if (!AutoLoadFail) {
1108 /* VID, PID */
1109 haldata->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
1110 haldata->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]);
1111
1112 /* Customer ID, 0x00 and 0xff are reserved for Realtek. */
1113 haldata->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
1114 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1115 } else {
1116 haldata->EEPROMVID = EEPROM_Default_VID;
1117 haldata->EEPROMPID = EEPROM_Default_PID;
1118
1119 /* Customer ID, 0x00 and 0xff are reserved for Realtek. */
1120 haldata->EEPROMCustomerID = EEPROM_Default_CustomerID;
1121 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1122 }
1123
1124 DBG_88E("VID = 0x%04X, PID = 0x%04X\n", haldata->EEPROMVID, haldata->EEPROMPID);
1125 DBG_88E("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", haldata->EEPROMCustomerID, haldata->EEPROMSubCustomerID);
1126 }
1127
Hal_EfuseParseMACAddr_8188EU(struct adapter * adapt,u8 * hwinfo,bool AutoLoadFail)1128 static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1129 {
1130 u16 i;
1131 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
1132 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1133
1134 if (AutoLoadFail) {
1135 for (i = 0; i < 6; i++)
1136 eeprom->mac_addr[i] = sMacAddr[i];
1137 } else {
1138 /* Read Permanent MAC address */
1139 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
1140 }
1141 }
1142
Hal_CustomizeByCustomerID_8188EU(struct adapter * adapt)1143 static void Hal_CustomizeByCustomerID_8188EU(struct adapter *adapt)
1144 {
1145 }
1146
1147 static void
readAdapterInfo_8188EU(struct adapter * adapt)1148 readAdapterInfo_8188EU(
1149 struct adapter *adapt
1150 )
1151 {
1152 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1153
1154 /* parse the eeprom/efuse content */
1155 Hal_EfuseParseIDCode88E(adapt, eeprom->efuse_eeprom_data);
1156 Hal_EfuseParsePIDVID_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1157 Hal_EfuseParseMACAddr_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1158
1159 Hal_ReadPowerSavingMode88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1160 Hal_ReadTxPowerInfo88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1161 Hal_EfuseParseEEPROMVer88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1162 rtl8188e_EfuseParseChnlPlan(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1163 Hal_EfuseParseXtal_8188E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1164 Hal_EfuseParseCustomerID88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1165 Hal_ReadAntennaDiversity88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1166 Hal_EfuseParseBoardType88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1167 Hal_ReadThermalMeter_88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1168
1169 /* */
1170 /* The following part initialize some vars by PG info. */
1171 /* */
1172 Hal_InitChannelPlan(adapt);
1173 Hal_CustomizeByCustomerID_8188EU(adapt);
1174
1175 _ReadLEDSetting(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1176 }
1177
_ReadPROMContent(struct adapter * Adapter)1178 static void _ReadPROMContent(
1179 struct adapter *Adapter
1180 )
1181 {
1182 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(Adapter);
1183 u8 eeValue;
1184
1185 /* check system boot selection */
1186 eeValue = rtw_read8(Adapter, REG_9346CR);
1187 eeprom->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1188 eeprom->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1189
1190 DBG_88E("Boot from %s, Autoload %s !\n", (eeprom->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1191 (eeprom->bautoload_fail_flag ? "Fail" : "OK"));
1192
1193 Hal_InitPGData88E(Adapter);
1194 readAdapterInfo_8188EU(Adapter);
1195 }
1196
_ReadRFType(struct adapter * Adapter)1197 static void _ReadRFType(struct adapter *Adapter)
1198 {
1199 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1200
1201 haldata->rf_chip = RF_6052;
1202 }
1203
_ReadAdapterInfo8188EU(struct adapter * Adapter)1204 static int _ReadAdapterInfo8188EU(struct adapter *Adapter)
1205 {
1206 u32 start = jiffies;
1207
1208 MSG_88E("====> %s\n", __func__);
1209
1210 _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1211 _ReadPROMContent(Adapter);
1212
1213 MSG_88E("<==== %s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
1214
1215 return _SUCCESS;
1216 }
1217
ReadAdapterInfo8188EU(struct adapter * Adapter)1218 static void ReadAdapterInfo8188EU(struct adapter *Adapter)
1219 {
1220 /* Read EEPROM size before call any EEPROM function */
1221 Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter);
1222
1223 _ReadAdapterInfo8188EU(Adapter);
1224 }
1225
1226 #define GPIO_DEBUG_PORT_NUM 0
rtl8192cu_trigger_gpio_0(struct adapter * adapt)1227 static void rtl8192cu_trigger_gpio_0(struct adapter *adapt)
1228 {
1229 }
1230
ResumeTxBeacon(struct adapter * adapt)1231 static void ResumeTxBeacon(struct adapter *adapt)
1232 {
1233 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1234
1235 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1236 /* which should be read from register to a global variable. */
1237
1238 rtw_write8(adapt, REG_FWHW_TXQ_CTRL + 2, (haldata->RegFwHwTxQCtrl) | BIT(6));
1239 haldata->RegFwHwTxQCtrl |= BIT(6);
1240 rtw_write8(adapt, REG_TBTT_PROHIBIT + 1, 0xff);
1241 haldata->RegReg542 |= BIT(0);
1242 rtw_write8(adapt, REG_TBTT_PROHIBIT + 2, haldata->RegReg542);
1243 }
1244
StopTxBeacon(struct adapter * adapt)1245 static void StopTxBeacon(struct adapter *adapt)
1246 {
1247 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1248
1249 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1250 /* which should be read from register to a global variable. */
1251
1252 rtw_write8(adapt, REG_FWHW_TXQ_CTRL + 2, (haldata->RegFwHwTxQCtrl) & (~BIT(6)));
1253 haldata->RegFwHwTxQCtrl &= (~BIT(6));
1254 rtw_write8(adapt, REG_TBTT_PROHIBIT + 1, 0x64);
1255 haldata->RegReg542 &= ~(BIT(0));
1256 rtw_write8(adapt, REG_TBTT_PROHIBIT + 2, haldata->RegReg542);
1257
1258 /* todo: CheckFwRsvdPageContent(Adapter); 2010.06.23. Added by tynli. */
1259 }
1260
hw_var_set_opmode(struct adapter * Adapter,u8 variable,u8 * val)1261 static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
1262 {
1263 u8 val8;
1264 u8 mode = *((u8 *)val);
1265
1266 /* disable Port0 TSF update */
1267 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | BIT(4));
1268
1269 /* set net_type */
1270 val8 = rtw_read8(Adapter, MSR) & 0x0c;
1271 val8 |= mode;
1272 rtw_write8(Adapter, MSR, val8);
1273
1274 DBG_88E("%s()-%d mode = %d\n", __func__, __LINE__, mode);
1275
1276 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
1277 StopTxBeacon(Adapter);
1278
1279 rtw_write8(Adapter, REG_BCN_CTRL, 0x19);/* disable atim wnd */
1280 } else if (mode == _HW_STATE_ADHOC_) {
1281 ResumeTxBeacon(Adapter);
1282 rtw_write8(Adapter, REG_BCN_CTRL, 0x1a);
1283 } else if (mode == _HW_STATE_AP_) {
1284 ResumeTxBeacon(Adapter);
1285
1286 rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
1287
1288 /* Set RCR */
1289 rtw_write32(Adapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0,reject ICV_ERR packet */
1290 /* enable to rx data frame */
1291 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1292 /* enable to rx ps-poll */
1293 rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
1294
1295 /* Beacon Control related register for first time */
1296 rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */
1297
1298 rtw_write8(Adapter, REG_ATIMWND, 0x0a); /* 10ms */
1299 rtw_write16(Adapter, REG_BCNTCFG, 0x00);
1300 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
1301 rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
1302
1303 /* reset TSF */
1304 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
1305
1306 /* BIT(3) - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */
1307 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4));
1308
1309 /* enable BCN0 Function for if1 */
1310 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
1311 rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP | EN_BCN_FUNCTION | BIT(1)));
1312
1313 /* dis BCN1 ATIM WND if if2 is station */
1314 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1) | BIT(0));
1315 }
1316 }
1317
hw_var_set_macaddr(struct adapter * Adapter,u8 variable,u8 * val)1318 static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val)
1319 {
1320 u8 idx = 0;
1321 u32 reg_macid;
1322
1323 reg_macid = REG_MACID;
1324
1325 for (idx = 0; idx < 6; idx++)
1326 rtw_write8(Adapter, (reg_macid + idx), val[idx]);
1327 }
1328
hw_var_set_bssid(struct adapter * Adapter,u8 variable,u8 * val)1329 static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val)
1330 {
1331 u8 idx = 0;
1332 u32 reg_bssid;
1333
1334 reg_bssid = REG_BSSID;
1335
1336 for (idx = 0; idx < 6; idx++)
1337 rtw_write8(Adapter, (reg_bssid + idx), val[idx]);
1338 }
1339
hw_var_set_bcn_func(struct adapter * Adapter,u8 variable,u8 * val)1340 static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val)
1341 {
1342 u32 bcn_ctrl_reg;
1343
1344 bcn_ctrl_reg = REG_BCN_CTRL;
1345
1346 if (*((u8 *)val))
1347 rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
1348 else
1349 rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg) & (~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
1350 }
1351
SetHwReg8188EU(struct adapter * Adapter,u8 variable,u8 * val)1352 static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1353 {
1354 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1355 struct dm_priv *pdmpriv = &haldata->dmpriv;
1356 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1357
1358 switch (variable) {
1359 case HW_VAR_MEDIA_STATUS:
1360 {
1361 u8 val8;
1362
1363 val8 = rtw_read8(Adapter, MSR) & 0x0c;
1364 val8 |= *((u8 *)val);
1365 rtw_write8(Adapter, MSR, val8);
1366 }
1367 break;
1368 case HW_VAR_MEDIA_STATUS1:
1369 {
1370 u8 val8;
1371
1372 val8 = rtw_read8(Adapter, MSR) & 0x03;
1373 val8 |= *((u8 *)val) << 2;
1374 rtw_write8(Adapter, MSR, val8);
1375 }
1376 break;
1377 case HW_VAR_SET_OPMODE:
1378 hw_var_set_opmode(Adapter, variable, val);
1379 break;
1380 case HW_VAR_MAC_ADDR:
1381 hw_var_set_macaddr(Adapter, variable, val);
1382 break;
1383 case HW_VAR_BSSID:
1384 hw_var_set_bssid(Adapter, variable, val);
1385 break;
1386 case HW_VAR_BASIC_RATE:
1387 {
1388 u16 BrateCfg = 0;
1389 u8 RateIndex = 0;
1390
1391 /* 2007.01.16, by Emily */
1392 /* Select RRSR (in Legacy-OFDM and CCK) */
1393 /* For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */
1394 /* We do not use other rates. */
1395 HalSetBrateCfg(Adapter, val, &BrateCfg);
1396 DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
1397
1398 /* 2011.03.30 add by Luke Lee */
1399 /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
1400 /* because CCK 2M has poor TXEVM */
1401 /* CCK 5.5M & 11M ACK should be enabled for better performance */
1402
1403 BrateCfg = (BrateCfg | 0xd) & 0x15d;
1404 haldata->BasicRateSet = BrateCfg;
1405
1406 BrateCfg |= 0x01; /* default enable 1M ACK rate */
1407 /* Set RRSR rate table. */
1408 rtw_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
1409 rtw_write8(Adapter, REG_RRSR + 1, (BrateCfg >> 8) & 0xff);
1410 rtw_write8(Adapter, REG_RRSR + 2, rtw_read8(Adapter, REG_RRSR + 2) & 0xf0);
1411
1412 /* Set RTS initial rate */
1413 while (BrateCfg > 0x1) {
1414 BrateCfg = (BrateCfg >> 1);
1415 RateIndex++;
1416 }
1417 /* Ziv - Check */
1418 rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
1419 }
1420 break;
1421 case HW_VAR_TXPAUSE:
1422 rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
1423 break;
1424 case HW_VAR_BCN_FUNC:
1425 hw_var_set_bcn_func(Adapter, variable, val);
1426 break;
1427 case HW_VAR_CORRECT_TSF:
1428 {
1429 u64 tsf;
1430 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1431 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1432
1433 tsf = pmlmeext->TSFValue - do_div(pmlmeext->TSFValue,
1434 pmlmeinfo->bcn_interval * 1024) - 1024; /* us */
1435
1436 if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
1437 StopTxBeacon(Adapter);
1438
1439 /* disable related TSF function */
1440 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) & (~BIT(3)));
1441
1442 rtw_write32(Adapter, REG_TSFTR, tsf);
1443 rtw_write32(Adapter, REG_TSFTR + 4, tsf >> 32);
1444
1445 /* enable related TSF function */
1446 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | BIT(3));
1447
1448 if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
1449 ResumeTxBeacon(Adapter);
1450 }
1451 break;
1452 case HW_VAR_CHECK_BSSID:
1453 if (*((u8 *)val)) {
1454 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) | RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1455 } else {
1456 u32 val32;
1457
1458 val32 = rtw_read32(Adapter, REG_RCR);
1459
1460 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1461
1462 rtw_write32(Adapter, REG_RCR, val32);
1463 }
1464 break;
1465 case HW_VAR_MLME_DISCONNECT:
1466 /* Set RCR to not to receive data frame when NO LINK state */
1467 /* reject all data frames */
1468 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1469
1470 /* reset TSF */
1471 rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1472
1473 /* disable update TSF */
1474 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | BIT(4));
1475 break;
1476 case HW_VAR_MLME_SITESURVEY:
1477 if (*((u8 *)val)) { /* under sitesurvey */
1478 /* config RCR to receive different BSSID & not to receive data frame */
1479 u32 v = rtw_read32(Adapter, REG_RCR);
1480 v &= ~(RCR_CBSSID_BCN);
1481 rtw_write32(Adapter, REG_RCR, v);
1482 /* reject all data frame */
1483 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1484
1485 /* disable update TSF */
1486 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | BIT(4));
1487 } else { /* sitesurvey done */
1488 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1489 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1490
1491 if ((is_client_associated_to_ap(Adapter)) ||
1492 ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
1493 /* enable to rx data frame */
1494 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1495
1496 /* enable update TSF */
1497 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) & (~BIT(4)));
1498 } else if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
1499 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1500 /* enable update TSF */
1501 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) & (~BIT(4)));
1502 }
1503 if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
1504 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) | RCR_CBSSID_BCN);
1505 } else {
1506 if (Adapter->in_cta_test) {
1507 u32 v = rtw_read32(Adapter, REG_RCR);
1508 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */
1509 rtw_write32(Adapter, REG_RCR, v);
1510 } else {
1511 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) | RCR_CBSSID_BCN);
1512 }
1513 }
1514 }
1515 break;
1516 case HW_VAR_MLME_JOIN:
1517 {
1518 u8 RetryLimit = 0x30;
1519 u8 type = *((u8 *)val);
1520 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1521
1522 if (type == 0) { /* prepare to join */
1523 /* enable to rx data frame.Accept all data frame */
1524 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1525
1526 if (Adapter->in_cta_test) {
1527 u32 v = rtw_read32(Adapter, REG_RCR);
1528 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */
1529 rtw_write32(Adapter, REG_RCR, v);
1530 } else {
1531 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) | RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1532 }
1533
1534 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
1535 RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
1536 else /* Ad-hoc Mode */
1537 RetryLimit = 0x7;
1538 } else if (type == 1) {
1539 /* joinbss_event call back when join res < 0 */
1540 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1541 } else if (type == 2) {
1542 /* sta add event call back */
1543 /* enable update TSF */
1544 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) & (~BIT(4)));
1545
1546 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))
1547 RetryLimit = 0x7;
1548 }
1549 rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
1550 }
1551 break;
1552 case HW_VAR_BEACON_INTERVAL:
1553 rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
1554 break;
1555 case HW_VAR_SLOT_TIME:
1556 {
1557 u8 u1bAIFS, aSifsTime;
1558 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1559 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1560
1561 rtw_write8(Adapter, REG_SLOT, val[0]);
1562
1563 if (pmlmeinfo->WMM_enable == 0) {
1564 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
1565 aSifsTime = 10;
1566 else
1567 aSifsTime = 16;
1568
1569 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
1570
1571 /* <Roger_EXP> Temporary removed, 2008.06.20. */
1572 rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
1573 rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
1574 rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
1575 rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
1576 }
1577 }
1578 break;
1579 case HW_VAR_RESP_SIFS:
1580 /* RESP_SIFS for CCK */
1581 rtw_write8(Adapter, REG_R2T_SIFS, val[0]); /* SIFS_T2T_CCK (0x08) */
1582 rtw_write8(Adapter, REG_R2T_SIFS + 1, val[1]); /* SIFS_R2T_CCK(0x08) */
1583 /* RESP_SIFS for OFDM */
1584 rtw_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */
1585 rtw_write8(Adapter, REG_T2T_SIFS + 1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
1586 break;
1587 case HW_VAR_ACK_PREAMBLE:
1588 {
1589 u8 regTmp;
1590 u8 bShortPreamble = *((bool *)val);
1591 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
1592 regTmp = (haldata->nCur40MhzPrimeSC) << 5;
1593 if (bShortPreamble)
1594 regTmp |= 0x80;
1595
1596 rtw_write8(Adapter, REG_RRSR + 2, regTmp);
1597 }
1598 break;
1599 case HW_VAR_SEC_CFG:
1600 rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
1601 break;
1602 case HW_VAR_DM_FLAG:
1603 podmpriv->SupportAbility = *((u8 *)val);
1604 break;
1605 case HW_VAR_DM_FUNC_OP:
1606 if (val[0])
1607 podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
1608 else
1609 podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
1610 break;
1611 case HW_VAR_DM_FUNC_SET:
1612 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1613 pdmpriv->DMFlag = pdmpriv->InitDMFlag;
1614 podmpriv->SupportAbility = pdmpriv->InitODMFlag;
1615 } else {
1616 podmpriv->SupportAbility |= *((u32 *)val);
1617 }
1618 break;
1619 case HW_VAR_DM_FUNC_CLR:
1620 podmpriv->SupportAbility &= *((u32 *)val);
1621 break;
1622 case HW_VAR_CAM_EMPTY_ENTRY:
1623 {
1624 u8 ucIndex = *((u8 *)val);
1625 u8 i;
1626 u32 ulCommand = 0;
1627 u32 ulContent = 0;
1628 u32 ulEncAlgo = CAM_AES;
1629
1630 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
1631 /* filled id in CAM config 2 byte */
1632 if (i == 0)
1633 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2);
1634 else
1635 ulContent = 0;
1636 /* polling bit, and No Write enable, and address */
1637 ulCommand = CAM_CONTENT_COUNT * ucIndex + i;
1638 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
1639 /* write content 0 is equall to mark invalid */
1640 rtw_write32(Adapter, WCAMI, ulContent); /* delay_ms(40); */
1641 rtw_write32(Adapter, RWCAM, ulCommand); /* delay_ms(40); */
1642 }
1643 }
1644 break;
1645 case HW_VAR_CAM_INVALID_ALL:
1646 rtw_write32(Adapter, RWCAM, BIT(31) | BIT(30));
1647 break;
1648 case HW_VAR_CAM_WRITE:
1649 {
1650 u32 cmd;
1651 u32 *cam_val = (u32 *)val;
1652 rtw_write32(Adapter, WCAMI, cam_val[0]);
1653
1654 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
1655 rtw_write32(Adapter, RWCAM, cmd);
1656 }
1657 break;
1658 case HW_VAR_AC_PARAM_VO:
1659 rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
1660 break;
1661 case HW_VAR_AC_PARAM_VI:
1662 rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
1663 break;
1664 case HW_VAR_AC_PARAM_BE:
1665 haldata->AcParam_BE = ((u32 *)(val))[0];
1666 rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
1667 break;
1668 case HW_VAR_AC_PARAM_BK:
1669 rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
1670 break;
1671 case HW_VAR_ACM_CTRL:
1672 {
1673 u8 acm_ctrl = *((u8 *)val);
1674 u8 AcmCtrl = rtw_read8(Adapter, REG_ACMHWCTRL);
1675
1676 if (acm_ctrl > 1)
1677 AcmCtrl = AcmCtrl | 0x1;
1678
1679 if (acm_ctrl & BIT(3))
1680 AcmCtrl |= AcmHw_VoqEn;
1681 else
1682 AcmCtrl &= (~AcmHw_VoqEn);
1683
1684 if (acm_ctrl & BIT(2))
1685 AcmCtrl |= AcmHw_ViqEn;
1686 else
1687 AcmCtrl &= (~AcmHw_ViqEn);
1688
1689 if (acm_ctrl & BIT(1))
1690 AcmCtrl |= AcmHw_BeqEn;
1691 else
1692 AcmCtrl &= (~AcmHw_BeqEn);
1693
1694 DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1695 rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
1696 }
1697 break;
1698 case HW_VAR_AMPDU_MIN_SPACE:
1699 {
1700 u8 MinSpacingToSet;
1701 u8 SecMinSpace;
1702
1703 MinSpacingToSet = *((u8 *)val);
1704 if (MinSpacingToSet <= 7) {
1705 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
1706 case _NO_PRIVACY_:
1707 case _AES_:
1708 SecMinSpace = 0;
1709 break;
1710 case _WEP40_:
1711 case _WEP104_:
1712 case _TKIP_:
1713 case _TKIP_WTMIC_:
1714 SecMinSpace = 6;
1715 break;
1716 default:
1717 SecMinSpace = 7;
1718 break;
1719 }
1720 if (MinSpacingToSet < SecMinSpace)
1721 MinSpacingToSet = SecMinSpace;
1722 rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
1723 }
1724 }
1725 break;
1726 case HW_VAR_AMPDU_FACTOR:
1727 {
1728 u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1729 u8 FactorToSet;
1730 u8 *pRegToSet;
1731 u8 index = 0;
1732
1733 pRegToSet = RegToSet_Normal; /* 0xb972a841; */
1734 FactorToSet = *((u8 *)val);
1735 if (FactorToSet <= 3) {
1736 FactorToSet = (1 << (FactorToSet + 2));
1737 if (FactorToSet > 0xf)
1738 FactorToSet = 0xf;
1739
1740 for (index = 0; index < 4; index++) {
1741 if ((pRegToSet[index] & 0xf0) > (FactorToSet << 4))
1742 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet << 4);
1743
1744 if ((pRegToSet[index] & 0x0f) > FactorToSet)
1745 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
1746
1747 rtw_write8(Adapter, (REG_AGGLEN_LMT + index), pRegToSet[index]);
1748 }
1749 }
1750 }
1751 break;
1752 case HW_VAR_RXDMA_AGG_PG_TH:
1753 {
1754 u8 threshold = *((u8 *)val);
1755 if (threshold == 0)
1756 threshold = haldata->UsbRxAggPageCount;
1757 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
1758 }
1759 break;
1760 case HW_VAR_SET_RPWM:
1761 break;
1762 case HW_VAR_H2C_FW_PWRMODE:
1763 {
1764 u8 psmode = (*(u8 *)val);
1765
1766 /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
1767 /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
1768 if ((psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(haldata->VersionID)))
1769 ODM_RF_Saving(podmpriv, true);
1770 rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
1771 }
1772 break;
1773 case HW_VAR_H2C_FW_JOINBSSRPT:
1774 {
1775 u8 mstatus = (*(u8 *)val);
1776 rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
1777 }
1778 break;
1779 #ifdef CONFIG_88EU_P2P
1780 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
1781 {
1782 u8 p2p_ps_state = (*(u8 *)val);
1783 rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
1784 }
1785 break;
1786 #endif
1787 case HW_VAR_INITIAL_GAIN:
1788 {
1789 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1790 u32 rx_gain = ((u32 *)(val))[0];
1791
1792 if (rx_gain == 0xff) {/* restore rx gain */
1793 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
1794 } else {
1795 pDigTable->BackupIGValue = pDigTable->CurIGValue;
1796 ODM_Write_DIG(podmpriv, rx_gain);
1797 }
1798 }
1799 break;
1800 case HW_VAR_TRIGGER_GPIO_0:
1801 rtl8192cu_trigger_gpio_0(Adapter);
1802 break;
1803 case HW_VAR_RPT_TIMER_SETTING:
1804 {
1805 u16 min_rpt_time = (*(u16 *)val);
1806 ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
1807 }
1808 break;
1809 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
1810 {
1811 u8 Optimum_antenna = (*(u8 *)val);
1812 u8 Ant;
1813 /* switch antenna to Optimum_antenna */
1814 if (haldata->CurAntenna != Optimum_antenna) {
1815 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
1816 ODM_UpdateRxIdleAnt_88E(&haldata->odmpriv, Ant);
1817
1818 haldata->CurAntenna = Optimum_antenna;
1819 }
1820 }
1821 break;
1822 case HW_VAR_EFUSE_BYTES: /* To set EFUE total used bytes, added by Roger, 2008.12.22. */
1823 haldata->EfuseUsedBytes = *((u16 *)val);
1824 break;
1825 case HW_VAR_FIFO_CLEARN_UP:
1826 {
1827 struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
1828 u8 trycnt = 100;
1829
1830 /* pause tx */
1831 rtw_write8(Adapter, REG_TXPAUSE, 0xff);
1832
1833 /* keep sn */
1834 Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter, REG_NQOS_SEQ);
1835
1836 if (!pwrpriv->bkeepfwalive) {
1837 /* RX DMA stop */
1838 rtw_write32(Adapter, REG_RXPKT_NUM, (rtw_read32(Adapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
1839 do {
1840 if (!(rtw_read32(Adapter, REG_RXPKT_NUM) & RXDMA_IDLE))
1841 break;
1842 } while (trycnt--);
1843 if (trycnt == 0)
1844 DBG_88E("Stop RX DMA failed......\n");
1845
1846 /* RQPN Load 0 */
1847 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0);
1848 rtw_write32(Adapter, REG_RQPN, 0x80000000);
1849 mdelay(10);
1850 }
1851 }
1852 break;
1853 case HW_VAR_CHECK_TXBUF:
1854 break;
1855 case HW_VAR_APFM_ON_MAC:
1856 haldata->bMacPwrCtrlOn = *val;
1857 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
1858 break;
1859 case HW_VAR_TX_RPT_MAX_MACID:
1860 {
1861 u8 maxMacid = *val;
1862 DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid + 1);
1863 rtw_write8(Adapter, REG_TX_RPT_CTRL + 1, maxMacid + 1);
1864 }
1865 break;
1866 case HW_VAR_H2C_MEDIA_STATUS_RPT:
1867 rtl8188e_set_FwMediaStatus_cmd(Adapter, (*(__le16 *)val));
1868 break;
1869 case HW_VAR_BCN_VALID:
1870 /* BCN_VALID, BIT(16) of REG_TDECTRL = BIT(0) of REG_TDECTRL+2, write 1 to clear, Clear by sw */
1871 rtw_write8(Adapter, REG_TDECTRL + 2, rtw_read8(Adapter, REG_TDECTRL + 2) | BIT(0));
1872 break;
1873 default:
1874 break;
1875 }
1876
1877 }
1878
GetHwReg8188EU(struct adapter * Adapter,u8 variable,u8 * val)1879 static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1880 {
1881 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1882 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1883
1884 switch (variable) {
1885 case HW_VAR_BASIC_RATE:
1886 *((u16 *)(val)) = haldata->BasicRateSet;
1887 fallthrough;
1888 case HW_VAR_TXPAUSE:
1889 val[0] = rtw_read8(Adapter, REG_TXPAUSE);
1890 break;
1891 case HW_VAR_BCN_VALID:
1892 /* BCN_VALID, BIT(16) of REG_TDECTRL = BIT(0) of REG_TDECTRL+2 */
1893 val[0] = (BIT(0) & rtw_read8(Adapter, REG_TDECTRL + 2)) ? true : false;
1894 break;
1895 case HW_VAR_DM_FLAG:
1896 val[0] = podmpriv->SupportAbility;
1897 break;
1898 case HW_VAR_RF_TYPE:
1899 val[0] = haldata->rf_type;
1900 break;
1901 case HW_VAR_FWLPS_RF_ON:
1902 {
1903 /* When we halt NIC, we should check if FW LPS is leave. */
1904 if (Adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
1905 /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
1906 /* because Fw is unload. */
1907 val[0] = true;
1908 } else {
1909 u32 valRCR;
1910 valRCR = rtw_read32(Adapter, REG_RCR);
1911 valRCR &= 0x00070000;
1912 if (valRCR)
1913 val[0] = false;
1914 else
1915 val[0] = true;
1916 }
1917 }
1918 break;
1919 case HW_VAR_CURRENT_ANTENNA:
1920 val[0] = haldata->CurAntenna;
1921 break;
1922 case HW_VAR_EFUSE_BYTES: /* To get EFUE total used bytes, added by Roger, 2008.12.22. */
1923 *((u16 *)(val)) = haldata->EfuseUsedBytes;
1924 break;
1925 case HW_VAR_APFM_ON_MAC:
1926 *val = haldata->bMacPwrCtrlOn;
1927 break;
1928 case HW_VAR_CHK_HI_QUEUE_EMPTY:
1929 *val = ((rtw_read32(Adapter, REG_HGQ_INFORMATION) & 0x0000ff00) == 0) ? true : false;
1930 break;
1931 default:
1932 break;
1933 }
1934
1935 }
1936
1937 /* */
1938 /* Description: */
1939 /* Query setting of specified variable. */
1940 /* */
1941 static u8
GetHalDefVar8188EUsb(struct adapter * Adapter,enum hal_def_variable eVariable,void * pValue)1942 GetHalDefVar8188EUsb(
1943 struct adapter *Adapter,
1944 enum hal_def_variable eVariable,
1945 void *pValue
1946 )
1947 {
1948 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1949 u8 bResult = _SUCCESS;
1950
1951 switch (eVariable) {
1952 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1953 {
1954 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1955 struct sta_priv *pstapriv = &Adapter->stapriv;
1956 struct sta_info *psta;
1957 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1958 if (psta)
1959 *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1960 }
1961 break;
1962 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1963 *((u8 *)pValue) = (haldata->AntDivCfg == 0) ? false : true;
1964 break;
1965 case HAL_DEF_CURRENT_ANTENNA:
1966 *((u8 *)pValue) = haldata->CurAntenna;
1967 break;
1968 case HAL_DEF_DRVINFO_SZ:
1969 *((u32 *)pValue) = DRVINFO_SZ;
1970 break;
1971 case HAL_DEF_MAX_RECVBUF_SZ:
1972 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1973 break;
1974 case HAL_DEF_RX_PACKET_OFFSET:
1975 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1976 break;
1977 case HAL_DEF_DBG_DM_FUNC:
1978 *((u32 *)pValue) = haldata->odmpriv.SupportAbility;
1979 break;
1980 case HAL_DEF_RA_DECISION_RATE:
1981 {
1982 u8 MacID = *((u8 *)pValue);
1983 *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, MacID);
1984 }
1985 break;
1986 case HAL_DEF_RA_SGI:
1987 {
1988 u8 MacID = *((u8 *)pValue);
1989 *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&haldata->odmpriv, MacID);
1990 }
1991 break;
1992 case HAL_DEF_PT_PWR_STATUS:
1993 {
1994 u8 MacID = *((u8 *)pValue);
1995 *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, MacID);
1996 }
1997 break;
1998 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1999 *((u32 *)pValue) = MAX_AMPDU_FACTOR_64K;
2000 break;
2001 case HW_DEF_RA_INFO_DUMP:
2002 {
2003 u8 entry_id = *((u8 *)pValue);
2004 if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
2005 DBG_88E("============ RA status check ===================\n");
2006 DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
2007 entry_id,
2008 haldata->odmpriv.RAInfo[entry_id].RateID,
2009 haldata->odmpriv.RAInfo[entry_id].RAUseRate,
2010 haldata->odmpriv.RAInfo[entry_id].RateSGI,
2011 haldata->odmpriv.RAInfo[entry_id].DecisionRate,
2012 haldata->odmpriv.RAInfo[entry_id].PTStage);
2013 }
2014 }
2015 break;
2016 case HAL_DEF_DBG_DUMP_RXPKT:
2017 *((u8 *)pValue) = haldata->bDumpRxPkt;
2018 break;
2019 case HAL_DEF_DBG_DUMP_TXPKT:
2020 *((u8 *)pValue) = haldata->bDumpTxPkt;
2021 break;
2022 default:
2023 bResult = _FAIL;
2024 break;
2025 }
2026
2027 return bResult;
2028 }
2029
2030 /* */
2031 /* Description: */
2032 /* Change default setting of specified variable. */
2033 /* */
SetHalDefVar8188EUsb(struct adapter * Adapter,enum hal_def_variable eVariable,void * pValue)2034 static u8 SetHalDefVar8188EUsb(struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue)
2035 {
2036 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
2037 u8 bResult = _SUCCESS;
2038
2039 switch (eVariable) {
2040 case HAL_DEF_DBG_DM_FUNC:
2041 {
2042 u8 dm_func = *((u8 *)pValue);
2043 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
2044
2045 if (dm_func == 0) { /* disable all dynamic func */
2046 podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
2047 DBG_88E("==> Disable all dynamic function...\n");
2048 } else if (dm_func == 1) {/* disable DIG */
2049 podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG);
2050 DBG_88E("==> Disable DIG...\n");
2051 } else if (dm_func == 2) {/* disable High power */
2052 podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
2053 } else if (dm_func == 3) {/* disable tx power tracking */
2054 podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION);
2055 DBG_88E("==> Disable tx power tracking...\n");
2056 } else if (dm_func == 5) {/* disable antenna diversity */
2057 podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV);
2058 } else if (dm_func == 6) {/* turn on all dynamic func */
2059 if (!(podmpriv->SupportAbility & DYNAMIC_BB_DIG)) {
2060 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
2061 pDigTable->CurIGValue = rtw_read8(Adapter, 0xc50);
2062 }
2063 podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
2064 DBG_88E("==> Turn on all dynamic function...\n");
2065 }
2066 }
2067 break;
2068 case HAL_DEF_DBG_DUMP_RXPKT:
2069 haldata->bDumpRxPkt = *((u8 *)pValue);
2070 break;
2071 case HAL_DEF_DBG_DUMP_TXPKT:
2072 haldata->bDumpTxPkt = *((u8 *)pValue);
2073 break;
2074 default:
2075 bResult = _FAIL;
2076 break;
2077 }
2078
2079 return bResult;
2080 }
2081
UpdateHalRAMask8188EUsb(struct adapter * adapt,u32 mac_id,u8 rssi_level)2082 static void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
2083 {
2084 u8 init_rate = 0;
2085 u8 networkType, raid;
2086 u32 mask, rate_bitmap;
2087 u8 shortGIrate = false;
2088 int supportRateNum = 0;
2089 struct sta_info *psta;
2090 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
2091 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
2092 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2093 struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
2094
2095 if (mac_id >= NUM_STA) /* CAM_SIZE */
2096 return;
2097 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2098 if (!psta)
2099 return;
2100 switch (mac_id) {
2101 case 0:/* for infra mode */
2102 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
2103 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
2104 raid = networktype_to_raid(networkType);
2105 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2106 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&pmlmeinfo->HT_caps) : 0;
2107 if (support_short_GI(adapt, &pmlmeinfo->HT_caps))
2108 shortGIrate = true;
2109 break;
2110 case 1:/* for broadcast/multicast */
2111 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2112 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
2113 networkType = WIRELESS_11B;
2114 else
2115 networkType = WIRELESS_11G;
2116 raid = networktype_to_raid(networkType);
2117 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
2118 break;
2119 default: /* for each sta in IBSS */
2120 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2121 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
2122 raid = networktype_to_raid(networkType);
2123 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2124
2125 /* todo: support HT in IBSS */
2126 break;
2127 }
2128
2129 rate_bitmap = 0x0fffffff;
2130 rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level);
2131 DBG_88E("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2132 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
2133
2134 mask &= rate_bitmap;
2135
2136 init_rate = get_highest_rate_idx(mask) & 0x3f;
2137
2138 if (haldata->fw_ractrl) {
2139 u8 arg;
2140
2141 arg = mac_id & 0x1f;/* MACID */
2142 arg |= BIT(7);
2143 if (shortGIrate)
2144 arg |= BIT(5);
2145 mask |= ((raid << 28) & 0xf0000000);
2146 DBG_88E("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
2147 psta->ra_mask = mask;
2148 mask |= ((raid << 28) & 0xf0000000);
2149
2150 /* to do ,for 8188E-SMIC */
2151 rtl8188e_set_raid_cmd(adapt, mask);
2152 } else {
2153 ODM_RA_UpdateRateInfo_8188E(&haldata->odmpriv,
2154 mac_id,
2155 raid,
2156 mask,
2157 shortGIrate
2158 );
2159 }
2160 /* set ra_id */
2161 psta->raid = raid;
2162 psta->init_rate = init_rate;
2163 }
2164
SetBeaconRelatedRegisters8188EUsb(struct adapter * adapt)2165 static void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt)
2166 {
2167 u32 value32;
2168 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
2169 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2170 u32 bcn_ctrl_reg = REG_BCN_CTRL;
2171 /* reset TSF, enable update TSF, correcting TSF On Beacon */
2172
2173 /* BCN interval */
2174 rtw_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2175 rtw_write8(adapt, REG_ATIMWND, 0x02);/* 2ms */
2176
2177 _InitBeaconParameters(adapt);
2178
2179 rtw_write8(adapt, REG_SLOT, 0x09);
2180
2181 value32 = rtw_read32(adapt, REG_TCR);
2182 value32 &= ~TSFRST;
2183 rtw_write32(adapt, REG_TCR, value32);
2184
2185 value32 |= TSFRST;
2186 rtw_write32(adapt, REG_TCR, value32);
2187
2188 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
2189 rtw_write8(adapt, REG_RXTSF_OFFSET_CCK, 0x50);
2190 rtw_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
2191
2192 _BeaconFunctionEnable(adapt, true, true);
2193
2194 ResumeTxBeacon(adapt);
2195
2196 rtw_write8(adapt, bcn_ctrl_reg, rtw_read8(adapt, bcn_ctrl_reg) | BIT(1));
2197 }
2198
rtl8188eu_init_default_value(struct adapter * adapt)2199 static void rtl8188eu_init_default_value(struct adapter *adapt)
2200 {
2201 struct hal_data_8188e *haldata;
2202 struct pwrctrl_priv *pwrctrlpriv;
2203 u8 i;
2204
2205 haldata = GET_HAL_DATA(adapt);
2206 pwrctrlpriv = &adapt->pwrctrlpriv;
2207
2208 /* init default value */
2209 haldata->fw_ractrl = false;
2210 if (!pwrctrlpriv->bkeepfwalive)
2211 haldata->LastHMEBoxNum = 0;
2212
2213 /* init dm default value */
2214 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
2215 haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */
2216 haldata->pwrGroupCnt = 0;
2217 haldata->PGMaxGroup = 13;
2218 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
2219 for (i = 0; i < HP_THERMAL_NUM; i++)
2220 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
2221 }
2222
rtl8188eu_ps_func(struct adapter * Adapter,enum hal_intf_ps_func efunc_id,u8 * val)2223 static u8 rtl8188eu_ps_func(struct adapter *Adapter, enum hal_intf_ps_func efunc_id, u8 *val)
2224 {
2225 u8 bResult = true;
2226 return bResult;
2227 }
2228
rtl8188eu_set_hal_ops(struct adapter * adapt)2229 void rtl8188eu_set_hal_ops(struct adapter *adapt)
2230 {
2231 struct hal_ops *halfunc = &adapt->HalFunc;
2232
2233 adapt->HalData = kzalloc(sizeof(struct hal_data_8188e), GFP_KERNEL);
2234 if (!adapt->HalData)
2235 DBG_88E("cant not alloc memory for HAL DATA\n");
2236 adapt->hal_data_sz = sizeof(struct hal_data_8188e);
2237
2238 halfunc->hal_power_on = rtl8188eu_InitPowerOn;
2239 halfunc->hal_init = &rtl8188eu_hal_init;
2240 halfunc->hal_deinit = &rtl8188eu_hal_deinit;
2241
2242 halfunc->inirp_init = &rtl8188eu_inirp_init;
2243 halfunc->inirp_deinit = &rtl8188eu_inirp_deinit;
2244
2245 halfunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
2246
2247 halfunc->init_recv_priv = &rtl8188eu_init_recv_priv;
2248 halfunc->free_recv_priv = &rtl8188eu_free_recv_priv;
2249 halfunc->InitSwLeds = &rtl8188eu_InitSwLeds;
2250 halfunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
2251
2252 halfunc->init_default_value = &rtl8188eu_init_default_value;
2253 halfunc->intf_chip_configure = &rtl8188eu_interface_configure;
2254 halfunc->read_adapter_info = &ReadAdapterInfo8188EU;
2255
2256 halfunc->SetHwRegHandler = &SetHwReg8188EU;
2257 halfunc->GetHwRegHandler = &GetHwReg8188EU;
2258 halfunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
2259 halfunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
2260
2261 halfunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb;
2262 halfunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
2263
2264 halfunc->hal_xmit = &rtl8188eu_hal_xmit;
2265 halfunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
2266
2267 halfunc->interface_ps_func = &rtl8188eu_ps_func;
2268
2269 rtl8188e_set_hal_ops(halfunc);
2270
2271 }
2272
