1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 * Copyright(c) 2018 - 2019 Intel Corporation
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
22 * Copyright(c) 2017 Intel Deutschland GmbH
23 * Copyright(c) 2018 - 2019 Intel Corporation
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 *
30 * * Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * * Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in
34 * the documentation and/or other materials provided with the
35 * distribution.
36 * * Neither the name Intel Corporation nor the names of its
37 * contributors may be used to endorse or promote products derived
38 * from this software without specific prior written permission.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 *
52 *****************************************************************************/
53 #include "iwl-trans.h"
54 #include "iwl-prph.h"
55 #include "iwl-context-info.h"
56 #include "iwl-context-info-gen3.h"
57 #include "internal.h"
58 #include "fw/dbg.h"
59
iwl_pcie_gen2_force_power_gating(struct iwl_trans * trans)60 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
61 {
62 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
63 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
64 udelay(20);
65 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
66 HPM_HIPM_GEN_CFG_CR_PG_EN |
67 HPM_HIPM_GEN_CFG_CR_SLP_EN);
68 udelay(20);
69 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
70 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
71
72 iwl_trans_sw_reset(trans);
73 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
74
75 return 0;
76 }
77
78 /*
79 * Start up NIC's basic functionality after it has been reset
80 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
81 * NOTE: This does not load uCode nor start the embedded processor
82 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)83 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
84 {
85 int ret = 0;
86
87 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
88
89 /*
90 * Use "set_bit" below rather than "write", to preserve any hardware
91 * bits already set by default after reset.
92 */
93
94 /*
95 * Disable L0s without affecting L1;
96 * don't wait for ICH L0s (ICH bug W/A)
97 */
98 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
99 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
100
101 /* Set FH wait threshold to maximum (HW error during stress W/A) */
102 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
103
104 /*
105 * Enable HAP INTA (interrupt from management bus) to
106 * wake device's PCI Express link L1a -> L0s
107 */
108 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
109 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
110
111 iwl_pcie_apm_config(trans);
112
113 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
114 trans->cfg->integrated) {
115 ret = iwl_pcie_gen2_force_power_gating(trans);
116 if (ret)
117 return ret;
118 }
119
120 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
121 if (ret)
122 return ret;
123
124 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
125
126 return 0;
127 }
128
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)129 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
130 {
131 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
132
133 if (op_mode_leave) {
134 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
135 iwl_pcie_gen2_apm_init(trans);
136
137 /* inform ME that we are leaving */
138 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
139 CSR_RESET_LINK_PWR_MGMT_DISABLED);
140 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
141 CSR_HW_IF_CONFIG_REG_PREPARE |
142 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
143 mdelay(1);
144 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
145 CSR_RESET_LINK_PWR_MGMT_DISABLED);
146 mdelay(5);
147 }
148
149 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
150
151 /* Stop device's DMA activity */
152 iwl_pcie_apm_stop_master(trans);
153
154 iwl_trans_sw_reset(trans);
155
156 /*
157 * Clear "initialization complete" bit to move adapter from
158 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
159 */
160 iwl_clear_bit(trans, CSR_GP_CNTRL,
161 BIT(trans->trans_cfg->csr->flag_init_done));
162 }
163
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)164 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
165 {
166 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
167
168 lockdep_assert_held(&trans_pcie->mutex);
169
170 if (trans_pcie->is_down)
171 return;
172
173 trans_pcie->is_down = true;
174
175 /* tell the device to stop sending interrupts */
176 iwl_disable_interrupts(trans);
177
178 /* device going down, Stop using ICT table */
179 iwl_pcie_disable_ict(trans);
180
181 /*
182 * If a HW restart happens during firmware loading,
183 * then the firmware loading might call this function
184 * and later it might be called again due to the
185 * restart. So don't process again if the device is
186 * already dead.
187 */
188 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
189 IWL_DEBUG_INFO(trans,
190 "DEVICE_ENABLED bit was set and is now cleared\n");
191 iwl_pcie_gen2_tx_stop(trans);
192 iwl_pcie_rx_stop(trans);
193 }
194
195 iwl_pcie_ctxt_info_free_paging(trans);
196 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560)
197 iwl_pcie_ctxt_info_gen3_free(trans);
198 else
199 iwl_pcie_ctxt_info_free(trans);
200
201 /* Make sure (redundant) we've released our request to stay awake */
202 iwl_clear_bit(trans, CSR_GP_CNTRL,
203 BIT(trans->trans_cfg->csr->flag_mac_access_req));
204
205 /* Stop the device, and put it in low power state */
206 iwl_pcie_gen2_apm_stop(trans, false);
207
208 iwl_trans_sw_reset(trans);
209
210 /*
211 * Upon stop, the IVAR table gets erased, so msi-x won't
212 * work. This causes a bug in RF-KILL flows, since the interrupt
213 * that enables radio won't fire on the correct irq, and the
214 * driver won't be able to handle the interrupt.
215 * Configure the IVAR table again after reset.
216 */
217 iwl_pcie_conf_msix_hw(trans_pcie);
218
219 /*
220 * Upon stop, the APM issues an interrupt if HW RF kill is set.
221 * This is a bug in certain verions of the hardware.
222 * Certain devices also keep sending HW RF kill interrupt all
223 * the time, unless the interrupt is ACKed even if the interrupt
224 * should be masked. Re-ACK all the interrupts here.
225 */
226 iwl_disable_interrupts(trans);
227
228 /* clear all status bits */
229 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
230 clear_bit(STATUS_INT_ENABLED, &trans->status);
231 clear_bit(STATUS_TPOWER_PMI, &trans->status);
232
233 /*
234 * Even if we stop the HW, we still want the RF kill
235 * interrupt
236 */
237 iwl_enable_rfkill_int(trans);
238
239 /* re-take ownership to prevent other users from stealing the device */
240 iwl_pcie_prepare_card_hw(trans);
241 }
242
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)243 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
244 {
245 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
246 bool was_in_rfkill;
247
248 mutex_lock(&trans_pcie->mutex);
249 trans_pcie->opmode_down = true;
250 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
251 _iwl_trans_pcie_gen2_stop_device(trans);
252 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
253 mutex_unlock(&trans_pcie->mutex);
254 }
255
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)256 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
257 {
258 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
259 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
260 trans->cfg->min_txq_size);
261
262 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
263 spin_lock(&trans_pcie->irq_lock);
264 iwl_pcie_gen2_apm_init(trans);
265 spin_unlock(&trans_pcie->irq_lock);
266
267 iwl_op_mode_nic_config(trans->op_mode);
268
269 /* Allocate the RX queue, or reset if it is already allocated */
270 if (iwl_pcie_gen2_rx_init(trans))
271 return -ENOMEM;
272
273 /* Allocate or reset and init all Tx and Command queues */
274 if (iwl_pcie_gen2_tx_init(trans, trans_pcie->cmd_queue, queue_size))
275 return -ENOMEM;
276
277 /* enable shadow regs in HW */
278 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
279 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
280
281 return 0;
282 }
283
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans,u32 scd_addr)284 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
285 {
286 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
287
288 iwl_pcie_reset_ict(trans);
289
290 /* make sure all queue are not stopped/used */
291 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
292 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
293
294 /* now that we got alive we can free the fw image & the context info.
295 * paging memory cannot be freed included since FW will still use it
296 */
297 iwl_pcie_ctxt_info_free(trans);
298
299 /*
300 * Re-enable all the interrupts, including the RF-Kill one, now that
301 * the firmware is alive.
302 */
303 iwl_enable_interrupts(trans);
304 mutex_lock(&trans_pcie->mutex);
305 iwl_pcie_check_hw_rf_kill(trans);
306 mutex_unlock(&trans_pcie->mutex);
307 }
308
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)309 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
310 const struct fw_img *fw, bool run_in_rfkill)
311 {
312 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
313 bool hw_rfkill;
314 int ret;
315
316 /* This may fail if AMT took ownership of the device */
317 if (iwl_pcie_prepare_card_hw(trans)) {
318 IWL_WARN(trans, "Exit HW not ready\n");
319 ret = -EIO;
320 goto out;
321 }
322
323 iwl_enable_rfkill_int(trans);
324
325 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
326
327 /*
328 * We enabled the RF-Kill interrupt and the handler may very
329 * well be running. Disable the interrupts to make sure no other
330 * interrupt can be fired.
331 */
332 iwl_disable_interrupts(trans);
333
334 /* Make sure it finished running */
335 iwl_pcie_synchronize_irqs(trans);
336
337 mutex_lock(&trans_pcie->mutex);
338
339 /* If platform's RF_KILL switch is NOT set to KILL */
340 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
341 if (hw_rfkill && !run_in_rfkill) {
342 ret = -ERFKILL;
343 goto out;
344 }
345
346 /* Someone called stop_device, don't try to start_fw */
347 if (trans_pcie->is_down) {
348 IWL_WARN(trans,
349 "Can't start_fw since the HW hasn't been started\n");
350 ret = -EIO;
351 goto out;
352 }
353
354 /* make sure rfkill handshake bits are cleared */
355 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
356 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
357 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
358
359 /* clear (again), then enable host interrupts */
360 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
361
362 ret = iwl_pcie_gen2_nic_init(trans);
363 if (ret) {
364 IWL_ERR(trans, "Unable to init nic\n");
365 goto out;
366 }
367
368 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560)
369 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
370 else
371 ret = iwl_pcie_ctxt_info_init(trans, fw);
372 if (ret)
373 goto out;
374
375 /* re-check RF-Kill state since we may have missed the interrupt */
376 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
377 if (hw_rfkill && !run_in_rfkill)
378 ret = -ERFKILL;
379
380 out:
381 mutex_unlock(&trans_pcie->mutex);
382 return ret;
383 }
384
