1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_LAPIC_H
3 #define __KVM_X86_LAPIC_H
4
5 #include <kvm/iodev.h>
6
7 #include <linux/kvm_host.h>
8
9 #define KVM_APIC_INIT 0
10 #define KVM_APIC_SIPI 1
11 #define KVM_APIC_LVT_NUM 6
12
13 #define APIC_SHORT_MASK 0xc0000
14 #define APIC_DEST_NOSHORT 0x0
15 #define APIC_DEST_MASK 0x800
16
17 #define APIC_BUS_CYCLE_NS 1
18 #define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
19
20 #define APIC_BROADCAST 0xFF
21 #define X2APIC_BROADCAST 0xFFFFFFFFul
22
23 enum lapic_mode {
24 LAPIC_MODE_DISABLED = 0,
25 LAPIC_MODE_INVALID = X2APIC_ENABLE,
26 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
27 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
28 };
29
30 struct kvm_timer {
31 struct hrtimer timer;
32 s64 period; /* unit: ns */
33 ktime_t target_expiration;
34 u32 timer_mode;
35 u32 timer_mode_mask;
36 u64 tscdeadline;
37 u64 expired_tscdeadline;
38 u32 timer_advance_ns;
39 s64 advance_expire_delta;
40 atomic_t pending; /* accumulated triggered timers */
41 bool hv_timer_in_use;
42 };
43
44 struct kvm_lapic {
45 unsigned long base_address;
46 struct kvm_io_device dev;
47 struct kvm_timer lapic_timer;
48 u32 divide_count;
49 struct kvm_vcpu *vcpu;
50 bool sw_enabled;
51 bool irr_pending;
52 bool lvt0_in_nmi_mode;
53 /* Number of bits set in ISR. */
54 s16 isr_count;
55 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
56 int highest_isr_cache;
57 /**
58 * APIC register page. The layout matches the register layout seen by
59 * the guest 1:1, because it is accessed by the vmx microcode.
60 * Note: Only one register, the TPR, is used by the microcode.
61 */
62 void *regs;
63 gpa_t vapic_addr;
64 struct gfn_to_hva_cache vapic_cache;
65 unsigned long pending_events;
66 unsigned int sipi_vector;
67 };
68
69 struct dest_map;
70
71 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
72 void kvm_free_lapic(struct kvm_vcpu *vcpu);
73
74 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
75 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
76 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
77 void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
78 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
79 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
80 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
81 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
82 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
83 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
84 void kvm_recalculate_apic_map(struct kvm *kvm);
85 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
86 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
87 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
88 void *data);
89 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
90 int shorthand, unsigned int dest, int dest_mode);
91 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
92 void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
93 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
94 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
95 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
96 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
97 struct dest_map *dest_map);
98 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
99 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
100
101 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
102 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
103 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
104
105 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
106 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
107 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
108 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
109 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
110 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
111
112 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
113 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
114
115 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
116 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
117
118 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
119 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
120 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
121
122 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
123 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
124
125 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
126 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
127
kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu * vcpu)128 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
129 {
130 return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
131 }
132
133 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
134 void kvm_lapic_init(void);
135 void kvm_lapic_exit(void);
136
137 #define VEC_POS(v) ((v) & (32 - 1))
138 #define REG_POS(v) (((v) >> 5) << 4)
139
kvm_lapic_clear_vector(int vec,void * bitmap)140 static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
141 {
142 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
143 }
144
kvm_lapic_set_vector(int vec,void * bitmap)145 static inline void kvm_lapic_set_vector(int vec, void *bitmap)
146 {
147 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
148 }
149
kvm_lapic_set_irr(int vec,struct kvm_lapic * apic)150 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
151 {
152 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
153 /*
154 * irr_pending must be true if any interrupt is pending; set it after
155 * APIC_IRR to avoid race with apic_clear_irr
156 */
157 apic->irr_pending = true;
158 }
159
kvm_lapic_get_reg(struct kvm_lapic * apic,int reg_off)160 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
161 {
162 return *((u32 *) (apic->regs + reg_off));
163 }
164
__kvm_lapic_set_reg(char * regs,int reg_off,u32 val)165 static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
166 {
167 *((u32 *) (regs + reg_off)) = val;
168 }
169
kvm_lapic_set_reg(struct kvm_lapic * apic,int reg_off,u32 val)170 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
171 {
172 __kvm_lapic_set_reg(apic->regs, reg_off, val);
173 }
174
175 extern struct static_key kvm_no_apic_vcpu;
176
lapic_in_kernel(struct kvm_vcpu * vcpu)177 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
178 {
179 if (static_key_false(&kvm_no_apic_vcpu))
180 return vcpu->arch.apic;
181 return true;
182 }
183
184 extern struct static_key_deferred apic_hw_disabled;
185
kvm_apic_hw_enabled(struct kvm_lapic * apic)186 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
187 {
188 if (static_key_false(&apic_hw_disabled.key))
189 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
190 return MSR_IA32_APICBASE_ENABLE;
191 }
192
193 extern struct static_key_deferred apic_sw_disabled;
194
kvm_apic_sw_enabled(struct kvm_lapic * apic)195 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
196 {
197 if (static_key_false(&apic_sw_disabled.key))
198 return apic->sw_enabled;
199 return true;
200 }
201
kvm_apic_present(struct kvm_vcpu * vcpu)202 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
203 {
204 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
205 }
206
kvm_lapic_enabled(struct kvm_vcpu * vcpu)207 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
208 {
209 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
210 }
211
apic_x2apic_mode(struct kvm_lapic * apic)212 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
213 {
214 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
215 }
216
kvm_vcpu_apicv_active(struct kvm_vcpu * vcpu)217 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
218 {
219 return vcpu->arch.apic && vcpu->arch.apicv_active;
220 }
221
kvm_apic_has_events(struct kvm_vcpu * vcpu)222 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
223 {
224 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
225 }
226
kvm_lowest_prio_delivery(struct kvm_lapic_irq * irq)227 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
228 {
229 return (irq->delivery_mode == APIC_DM_LOWEST ||
230 irq->msi_redir_hint);
231 }
232
kvm_lapic_latched_init(struct kvm_vcpu * vcpu)233 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
234 {
235 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
236 }
237
238 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
239
240 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
241
242 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
243 unsigned long *vcpu_bitmap);
244
245 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
246 struct kvm_vcpu **dest_vcpu);
247 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
248 const unsigned long *bitmap, u32 bitmap_size);
249 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
250 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
251 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
252 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
253 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
254 bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
255
kvm_apic_mode(u64 apic_base)256 static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
257 {
258 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
259 }
260
kvm_xapic_id(struct kvm_lapic * apic)261 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
262 {
263 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
264 }
265
266 #endif
267
