1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later)
4 *
5 * Copyright (C) 2003 David Gibson, IBM Corporation.
6 *
7 * Based on the IA-32 version:
8 * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
9 */
10
11 #include <linux/mm.h>
12 #include <linux/hugetlb.h>
13 #include <asm/pgtable.h>
14 #include <asm/pgalloc.h>
15 #include <asm/cacheflush.h>
16 #include <asm/machdep.h>
17
18 extern long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
19 unsigned long pa, unsigned long rlags,
20 unsigned long vflags, int psize, int ssize);
21
__hash_page_huge(unsigned long ea,unsigned long access,unsigned long vsid,pte_t * ptep,unsigned long trap,unsigned long flags,int ssize,unsigned int shift,unsigned int mmu_psize)22 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
23 pte_t *ptep, unsigned long trap, unsigned long flags,
24 int ssize, unsigned int shift, unsigned int mmu_psize)
25 {
26 real_pte_t rpte;
27 unsigned long vpn;
28 unsigned long old_pte, new_pte;
29 unsigned long rflags, pa, sz;
30 long slot, offset;
31
32 BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
33
34 /* Search the Linux page table for a match with va */
35 vpn = hpt_vpn(ea, vsid, ssize);
36
37 /* At this point, we have a pte (old_pte) which can be used to build
38 * or update an HPTE. There are 2 cases:
39 *
40 * 1. There is a valid (present) pte with no associated HPTE (this is
41 * the most common case)
42 * 2. There is a valid (present) pte with an associated HPTE. The
43 * current values of the pp bits in the HPTE prevent access
44 * because we are doing software DIRTY bit management and the
45 * page is currently not DIRTY.
46 */
47
48
49 do {
50 old_pte = pte_val(*ptep);
51 /* If PTE busy, retry the access */
52 if (unlikely(old_pte & H_PAGE_BUSY))
53 return 0;
54 /* If PTE permissions don't match, take page fault */
55 if (unlikely(!check_pte_access(access, old_pte)))
56 return 1;
57
58 /* Try to lock the PTE, add ACCESSED and DIRTY if it was
59 * a write access */
60 new_pte = old_pte | H_PAGE_BUSY | _PAGE_ACCESSED;
61 if (access & _PAGE_WRITE)
62 new_pte |= _PAGE_DIRTY;
63 } while(!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
64
65 rflags = htab_convert_pte_flags(new_pte);
66 if (unlikely(mmu_psize == MMU_PAGE_16G))
67 offset = PTRS_PER_PUD;
68 else
69 offset = PTRS_PER_PMD;
70 rpte = __real_pte(__pte(old_pte), ptep, offset);
71
72 sz = ((1UL) << shift);
73 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
74 /* No CPU has hugepages but lacks no execute, so we
75 * don't need to worry about that case */
76 rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
77
78 /* Check if pte already has an hpte (case 2) */
79 if (unlikely(old_pte & H_PAGE_HASHPTE)) {
80 /* There MIGHT be an HPTE for this pte */
81 unsigned long gslot;
82
83 gslot = pte_get_hash_gslot(vpn, shift, ssize, rpte, 0);
84 if (mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn, mmu_psize,
85 mmu_psize, ssize, flags) == -1)
86 old_pte &= ~_PAGE_HPTEFLAGS;
87 }
88
89 if (likely(!(old_pte & H_PAGE_HASHPTE))) {
90 unsigned long hash = hpt_hash(vpn, shift, ssize);
91
92 pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
93
94 /* clear HPTE slot informations in new PTE */
95 new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;
96
97 slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0,
98 mmu_psize, ssize);
99
100 /*
101 * Hypervisor failure. Restore old pte and return -1
102 * similar to __hash_page_*
103 */
104 if (unlikely(slot == -2)) {
105 *ptep = __pte(old_pte);
106 hash_failure_debug(ea, access, vsid, trap, ssize,
107 mmu_psize, mmu_psize, old_pte);
108 return -1;
109 }
110
111 new_pte |= pte_set_hidx(ptep, rpte, 0, slot, offset);
112 }
113
114 /*
115 * No need to use ldarx/stdcx here
116 */
117 *ptep = __pte(new_pte & ~H_PAGE_BUSY);
118 return 0;
119 }
120
