1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PARAVIRT_H
3 #define _ASM_X86_PARAVIRT_H
4 /* Various instructions on x86 need to be replaced for
5 * para-virtualization: those hooks are defined here. */
6
7 #ifdef CONFIG_PARAVIRT
8 #include <asm/pgtable_types.h>
9 #include <asm/asm.h>
10 #include <asm/nospec-branch.h>
11
12 #include <asm/paravirt_types.h>
13
14 #ifndef __ASSEMBLY__
15 #include <linux/bug.h>
16 #include <linux/types.h>
17 #include <linux/cpumask.h>
18 #include <asm/frame.h>
19
load_sp0(unsigned long sp0)20 static inline void load_sp0(unsigned long sp0)
21 {
22 PVOP_VCALL1(pv_cpu_ops.load_sp0, sp0);
23 }
24
25 /* The paravirtualized CPUID instruction. */
__cpuid(unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)26 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
27 unsigned int *ecx, unsigned int *edx)
28 {
29 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
30 }
31
32 /*
33 * These special macros can be used to get or set a debugging register
34 */
paravirt_get_debugreg(int reg)35 static inline unsigned long paravirt_get_debugreg(int reg)
36 {
37 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
38 }
39 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
set_debugreg(unsigned long val,int reg)40 static inline void set_debugreg(unsigned long val, int reg)
41 {
42 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
43 }
44
read_cr0(void)45 static inline unsigned long read_cr0(void)
46 {
47 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
48 }
49
write_cr0(unsigned long x)50 static inline void write_cr0(unsigned long x)
51 {
52 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
53 }
54
read_cr2(void)55 static inline unsigned long read_cr2(void)
56 {
57 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
58 }
59
write_cr2(unsigned long x)60 static inline void write_cr2(unsigned long x)
61 {
62 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
63 }
64
__read_cr3(void)65 static inline unsigned long __read_cr3(void)
66 {
67 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
68 }
69
write_cr3(unsigned long x)70 static inline void write_cr3(unsigned long x)
71 {
72 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
73 }
74
__write_cr4(unsigned long x)75 static inline void __write_cr4(unsigned long x)
76 {
77 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
78 }
79
80 #ifdef CONFIG_X86_64
read_cr8(void)81 static inline unsigned long read_cr8(void)
82 {
83 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
84 }
85
write_cr8(unsigned long x)86 static inline void write_cr8(unsigned long x)
87 {
88 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
89 }
90 #endif
91
arch_safe_halt(void)92 static inline void arch_safe_halt(void)
93 {
94 PVOP_VCALL0(pv_irq_ops.safe_halt);
95 }
96
halt(void)97 static inline void halt(void)
98 {
99 PVOP_VCALL0(pv_irq_ops.halt);
100 }
101
wbinvd(void)102 static inline void wbinvd(void)
103 {
104 PVOP_VCALL0(pv_cpu_ops.wbinvd);
105 }
106
107 #define get_kernel_rpl() (pv_info.kernel_rpl)
108
paravirt_read_msr(unsigned msr)109 static inline u64 paravirt_read_msr(unsigned msr)
110 {
111 return PVOP_CALL1(u64, pv_cpu_ops.read_msr, msr);
112 }
113
paravirt_write_msr(unsigned msr,unsigned low,unsigned high)114 static inline void paravirt_write_msr(unsigned msr,
115 unsigned low, unsigned high)
116 {
117 PVOP_VCALL3(pv_cpu_ops.write_msr, msr, low, high);
118 }
119
paravirt_read_msr_safe(unsigned msr,int * err)120 static inline u64 paravirt_read_msr_safe(unsigned msr, int *err)
121 {
122 return PVOP_CALL2(u64, pv_cpu_ops.read_msr_safe, msr, err);
123 }
124
paravirt_write_msr_safe(unsigned msr,unsigned low,unsigned high)125 static inline int paravirt_write_msr_safe(unsigned msr,
126 unsigned low, unsigned high)
127 {
128 return PVOP_CALL3(int, pv_cpu_ops.write_msr_safe, msr, low, high);
129 }
130
131 #define rdmsr(msr, val1, val2) \
132 do { \
133 u64 _l = paravirt_read_msr(msr); \
134 val1 = (u32)_l; \
135 val2 = _l >> 32; \
136 } while (0)
137
138 #define wrmsr(msr, val1, val2) \
139 do { \
140 paravirt_write_msr(msr, val1, val2); \
141 } while (0)
142
143 #define rdmsrl(msr, val) \
144 do { \
145 val = paravirt_read_msr(msr); \
146 } while (0)
147
wrmsrl(unsigned msr,u64 val)148 static inline void wrmsrl(unsigned msr, u64 val)
149 {
150 wrmsr(msr, (u32)val, (u32)(val>>32));
151 }
152
153 #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b)
154
155 /* rdmsr with exception handling */
156 #define rdmsr_safe(msr, a, b) \
157 ({ \
158 int _err; \
159 u64 _l = paravirt_read_msr_safe(msr, &_err); \
160 (*a) = (u32)_l; \
161 (*b) = _l >> 32; \
162 _err; \
163 })
164
rdmsrl_safe(unsigned msr,unsigned long long * p)165 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
166 {
167 int err;
168
169 *p = paravirt_read_msr_safe(msr, &err);
170 return err;
171 }
172
paravirt_sched_clock(void)173 static inline unsigned long long paravirt_sched_clock(void)
174 {
175 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
176 }
177
178 struct static_key;
179 extern struct static_key paravirt_steal_enabled;
180 extern struct static_key paravirt_steal_rq_enabled;
181
paravirt_steal_clock(int cpu)182 static inline u64 paravirt_steal_clock(int cpu)
183 {
184 return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu);
185 }
186
paravirt_read_pmc(int counter)187 static inline unsigned long long paravirt_read_pmc(int counter)
188 {
189 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
190 }
191
192 #define rdpmc(counter, low, high) \
193 do { \
194 u64 _l = paravirt_read_pmc(counter); \
195 low = (u32)_l; \
196 high = _l >> 32; \
197 } while (0)
198
199 #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
200
paravirt_alloc_ldt(struct desc_struct * ldt,unsigned entries)201 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
202 {
203 PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries);
204 }
205
paravirt_free_ldt(struct desc_struct * ldt,unsigned entries)206 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
207 {
208 PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries);
209 }
210
load_TR_desc(void)211 static inline void load_TR_desc(void)
212 {
213 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
214 }
load_gdt(const struct desc_ptr * dtr)215 static inline void load_gdt(const struct desc_ptr *dtr)
216 {
217 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
218 }
load_idt(const struct desc_ptr * dtr)219 static inline void load_idt(const struct desc_ptr *dtr)
220 {
221 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
222 }
set_ldt(const void * addr,unsigned entries)223 static inline void set_ldt(const void *addr, unsigned entries)
224 {
225 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
226 }
paravirt_store_tr(void)227 static inline unsigned long paravirt_store_tr(void)
228 {
229 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
230 }
231 #define store_tr(tr) ((tr) = paravirt_store_tr())
load_TLS(struct thread_struct * t,unsigned cpu)232 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
233 {
234 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
235 }
236
237 #ifdef CONFIG_X86_64
load_gs_index(unsigned int gs)238 static inline void load_gs_index(unsigned int gs)
239 {
240 PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs);
241 }
242 #endif
243
write_ldt_entry(struct desc_struct * dt,int entry,const void * desc)244 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
245 const void *desc)
246 {
247 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
248 }
249
write_gdt_entry(struct desc_struct * dt,int entry,void * desc,int type)250 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
251 void *desc, int type)
252 {
253 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
254 }
255
write_idt_entry(gate_desc * dt,int entry,const gate_desc * g)256 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
257 {
258 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
259 }
set_iopl_mask(unsigned mask)260 static inline void set_iopl_mask(unsigned mask)
261 {
262 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
263 }
264
265 /* The paravirtualized I/O functions */
slow_down_io(void)266 static inline void slow_down_io(void)
267 {
268 pv_cpu_ops.io_delay();
269 #ifdef REALLY_SLOW_IO
270 pv_cpu_ops.io_delay();
271 pv_cpu_ops.io_delay();
272 pv_cpu_ops.io_delay();
273 #endif
274 }
275
paravirt_activate_mm(struct mm_struct * prev,struct mm_struct * next)276 static inline void paravirt_activate_mm(struct mm_struct *prev,
277 struct mm_struct *next)
278 {
279 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
280 }
281
paravirt_arch_dup_mmap(struct mm_struct * oldmm,struct mm_struct * mm)282 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
283 struct mm_struct *mm)
284 {
285 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
286 }
287
paravirt_arch_exit_mmap(struct mm_struct * mm)288 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
289 {
290 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
291 }
292
__flush_tlb(void)293 static inline void __flush_tlb(void)
294 {
295 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
296 }
__flush_tlb_global(void)297 static inline void __flush_tlb_global(void)
298 {
299 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
300 }
__flush_tlb_one_user(unsigned long addr)301 static inline void __flush_tlb_one_user(unsigned long addr)
302 {
303 PVOP_VCALL1(pv_mmu_ops.flush_tlb_one_user, addr);
304 }
305
flush_tlb_others(const struct cpumask * cpumask,const struct flush_tlb_info * info)306 static inline void flush_tlb_others(const struct cpumask *cpumask,
307 const struct flush_tlb_info *info)
308 {
309 PVOP_VCALL2(pv_mmu_ops.flush_tlb_others, cpumask, info);
310 }
311
paravirt_tlb_remove_table(struct mmu_gather * tlb,void * table)312 static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table)
313 {
314 PVOP_VCALL2(pv_mmu_ops.tlb_remove_table, tlb, table);
315 }
316
paravirt_pgd_alloc(struct mm_struct * mm)317 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
318 {
319 return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm);
320 }
321
paravirt_pgd_free(struct mm_struct * mm,pgd_t * pgd)322 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
323 {
324 PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
325 }
326
paravirt_alloc_pte(struct mm_struct * mm,unsigned long pfn)327 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
328 {
329 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
330 }
paravirt_release_pte(unsigned long pfn)331 static inline void paravirt_release_pte(unsigned long pfn)
332 {
333 PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
334 }
335
paravirt_alloc_pmd(struct mm_struct * mm,unsigned long pfn)336 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
337 {
338 PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
339 }
340
paravirt_release_pmd(unsigned long pfn)341 static inline void paravirt_release_pmd(unsigned long pfn)
342 {
343 PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
344 }
345
paravirt_alloc_pud(struct mm_struct * mm,unsigned long pfn)346 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
347 {
348 PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
349 }
paravirt_release_pud(unsigned long pfn)350 static inline void paravirt_release_pud(unsigned long pfn)
351 {
352 PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
353 }
354
paravirt_alloc_p4d(struct mm_struct * mm,unsigned long pfn)355 static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn)
356 {
357 PVOP_VCALL2(pv_mmu_ops.alloc_p4d, mm, pfn);
358 }
359
paravirt_release_p4d(unsigned long pfn)360 static inline void paravirt_release_p4d(unsigned long pfn)
361 {
362 PVOP_VCALL1(pv_mmu_ops.release_p4d, pfn);
363 }
364
__pte(pteval_t val)365 static inline pte_t __pte(pteval_t val)
366 {
367 pteval_t ret;
368
369 if (sizeof(pteval_t) > sizeof(long))
370 ret = PVOP_CALLEE2(pteval_t,
371 pv_mmu_ops.make_pte,
372 val, (u64)val >> 32);
373 else
374 ret = PVOP_CALLEE1(pteval_t,
375 pv_mmu_ops.make_pte,
376 val);
377
378 return (pte_t) { .pte = ret };
379 }
380
pte_val(pte_t pte)381 static inline pteval_t pte_val(pte_t pte)
382 {
383 pteval_t ret;
384
385 if (sizeof(pteval_t) > sizeof(long))
386 ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val,
387 pte.pte, (u64)pte.pte >> 32);
388 else
389 ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val,
390 pte.pte);
391
392 return ret;
393 }
394
__pgd(pgdval_t val)395 static inline pgd_t __pgd(pgdval_t val)
396 {
397 pgdval_t ret;
398
399 if (sizeof(pgdval_t) > sizeof(long))
400 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd,
401 val, (u64)val >> 32);
402 else
403 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd,
404 val);
405
406 return (pgd_t) { ret };
407 }
408
pgd_val(pgd_t pgd)409 static inline pgdval_t pgd_val(pgd_t pgd)
410 {
411 pgdval_t ret;
412
413 if (sizeof(pgdval_t) > sizeof(long))
414 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val,
415 pgd.pgd, (u64)pgd.pgd >> 32);
416 else
417 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val,
418 pgd.pgd);
419
420 return ret;
421 }
422
423 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
ptep_modify_prot_start(struct mm_struct * mm,unsigned long addr,pte_t * ptep)424 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
425 pte_t *ptep)
426 {
427 pteval_t ret;
428
429 ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
430 mm, addr, ptep);
431
432 return (pte_t) { .pte = ret };
433 }
434
ptep_modify_prot_commit(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)435 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
436 pte_t *ptep, pte_t pte)
437 {
438 if (sizeof(pteval_t) > sizeof(long))
439 /* 5 arg words */
440 pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
441 else
442 PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
443 mm, addr, ptep, pte.pte);
444 }
445
set_pte(pte_t * ptep,pte_t pte)446 static inline void set_pte(pte_t *ptep, pte_t pte)
447 {
448 if (sizeof(pteval_t) > sizeof(long))
449 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
450 pte.pte, (u64)pte.pte >> 32);
451 else
452 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
453 pte.pte);
454 }
455
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)456 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
457 pte_t *ptep, pte_t pte)
458 {
459 if (sizeof(pteval_t) > sizeof(long))
460 /* 5 arg words */
461 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
462 else
463 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
464 }
465
set_pmd(pmd_t * pmdp,pmd_t pmd)466 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
467 {
468 pmdval_t val = native_pmd_val(pmd);
469
470 if (sizeof(pmdval_t) > sizeof(long))
471 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
472 else
473 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
474 }
475
476 #if CONFIG_PGTABLE_LEVELS >= 3
__pmd(pmdval_t val)477 static inline pmd_t __pmd(pmdval_t val)
478 {
479 pmdval_t ret;
480
481 if (sizeof(pmdval_t) > sizeof(long))
482 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd,
483 val, (u64)val >> 32);
484 else
485 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd,
486 val);
487
488 return (pmd_t) { ret };
489 }
490
pmd_val(pmd_t pmd)491 static inline pmdval_t pmd_val(pmd_t pmd)
492 {
493 pmdval_t ret;
494
495 if (sizeof(pmdval_t) > sizeof(long))
496 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val,
497 pmd.pmd, (u64)pmd.pmd >> 32);
498 else
499 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val,
500 pmd.pmd);
501
502 return ret;
503 }
504
set_pud(pud_t * pudp,pud_t pud)505 static inline void set_pud(pud_t *pudp, pud_t pud)
506 {
507 pudval_t val = native_pud_val(pud);
508
509 if (sizeof(pudval_t) > sizeof(long))
510 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
511 val, (u64)val >> 32);
512 else
513 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
514 val);
515 }
516 #if CONFIG_PGTABLE_LEVELS >= 4
__pud(pudval_t val)517 static inline pud_t __pud(pudval_t val)
518 {
519 pudval_t ret;
520
521 if (sizeof(pudval_t) > sizeof(long))
522 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud,
523 val, (u64)val >> 32);
524 else
525 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud,
526 val);
527
528 return (pud_t) { ret };
529 }
530
pud_val(pud_t pud)531 static inline pudval_t pud_val(pud_t pud)
532 {
533 pudval_t ret;
534
535 if (sizeof(pudval_t) > sizeof(long))
536 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val,
537 pud.pud, (u64)pud.pud >> 32);
538 else
539 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val,
540 pud.pud);
541
542 return ret;
543 }
544
pud_clear(pud_t * pudp)545 static inline void pud_clear(pud_t *pudp)
546 {
547 set_pud(pudp, __pud(0));
548 }
549
set_p4d(p4d_t * p4dp,p4d_t p4d)550 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
551 {
552 p4dval_t val = native_p4d_val(p4d);
553
554 if (sizeof(p4dval_t) > sizeof(long))
555 PVOP_VCALL3(pv_mmu_ops.set_p4d, p4dp,
556 val, (u64)val >> 32);
557 else
558 PVOP_VCALL2(pv_mmu_ops.set_p4d, p4dp,
559 val);
560 }
561
562 #if CONFIG_PGTABLE_LEVELS >= 5
563
__p4d(p4dval_t val)564 static inline p4d_t __p4d(p4dval_t val)
565 {
566 p4dval_t ret = PVOP_CALLEE1(p4dval_t, pv_mmu_ops.make_p4d, val);
567
568 return (p4d_t) { ret };
569 }
570
p4d_val(p4d_t p4d)571 static inline p4dval_t p4d_val(p4d_t p4d)
572 {
573 return PVOP_CALLEE1(p4dval_t, pv_mmu_ops.p4d_val, p4d.p4d);
574 }
575
__set_pgd(pgd_t * pgdp,pgd_t pgd)576 static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd)
577 {
578 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, native_pgd_val(pgd));
579 }
580
581 #define set_pgd(pgdp, pgdval) do { \
582 if (pgtable_l5_enabled()) \
583 __set_pgd(pgdp, pgdval); \
584 else \
585 set_p4d((p4d_t *)(pgdp), (p4d_t) { (pgdval).pgd }); \
586 } while (0)
587
588 #define pgd_clear(pgdp) do { \
589 if (pgtable_l5_enabled()) \
590 set_pgd(pgdp, __pgd(0)); \
591 } while (0)
592
593 #endif /* CONFIG_PGTABLE_LEVELS == 5 */
594
p4d_clear(p4d_t * p4dp)595 static inline void p4d_clear(p4d_t *p4dp)
596 {
597 set_p4d(p4dp, __p4d(0));
598 }
599
600 #endif /* CONFIG_PGTABLE_LEVELS == 4 */
601
602 #endif /* CONFIG_PGTABLE_LEVELS >= 3 */
603
604 #ifdef CONFIG_X86_PAE
605 /* Special-case pte-setting operations for PAE, which can't update a
606 64-bit pte atomically */
set_pte_atomic(pte_t * ptep,pte_t pte)607 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
608 {
609 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
610 pte.pte, pte.pte >> 32);
611 }
612
pte_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)613 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
614 pte_t *ptep)
615 {
616 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
617 }
618
pmd_clear(pmd_t * pmdp)619 static inline void pmd_clear(pmd_t *pmdp)
620 {
621 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
622 }
623 #else /* !CONFIG_X86_PAE */
set_pte_atomic(pte_t * ptep,pte_t pte)624 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
625 {
626 set_pte(ptep, pte);
627 }
628
pte_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)629 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
630 pte_t *ptep)
631 {
632 set_pte_at(mm, addr, ptep, __pte(0));
633 }
634
pmd_clear(pmd_t * pmdp)635 static inline void pmd_clear(pmd_t *pmdp)
636 {
637 set_pmd(pmdp, __pmd(0));
638 }
639 #endif /* CONFIG_X86_PAE */
640
641 #define __HAVE_ARCH_START_CONTEXT_SWITCH
arch_start_context_switch(struct task_struct * prev)642 static inline void arch_start_context_switch(struct task_struct *prev)
643 {
644 PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev);
645 }
646
arch_end_context_switch(struct task_struct * next)647 static inline void arch_end_context_switch(struct task_struct *next)
648 {
649 PVOP_VCALL1(pv_cpu_ops.end_context_switch, next);
650 }
651
652 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
arch_enter_lazy_mmu_mode(void)653 static inline void arch_enter_lazy_mmu_mode(void)
654 {
655 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
656 }
657
arch_leave_lazy_mmu_mode(void)658 static inline void arch_leave_lazy_mmu_mode(void)
659 {
660 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
661 }
662
arch_flush_lazy_mmu_mode(void)663 static inline void arch_flush_lazy_mmu_mode(void)
664 {
665 PVOP_VCALL0(pv_mmu_ops.lazy_mode.flush);
666 }
667
__set_fixmap(unsigned idx,phys_addr_t phys,pgprot_t flags)668 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
669 phys_addr_t phys, pgprot_t flags)
670 {
671 pv_mmu_ops.set_fixmap(idx, phys, flags);
672 }
673
674 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
675
pv_queued_spin_lock_slowpath(struct qspinlock * lock,u32 val)676 static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
677 u32 val)
678 {
679 PVOP_VCALL2(pv_lock_ops.queued_spin_lock_slowpath, lock, val);
680 }
681
pv_queued_spin_unlock(struct qspinlock * lock)682 static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
683 {
684 PVOP_VCALLEE1(pv_lock_ops.queued_spin_unlock, lock);
685 }
686
pv_wait(u8 * ptr,u8 val)687 static __always_inline void pv_wait(u8 *ptr, u8 val)
688 {
689 PVOP_VCALL2(pv_lock_ops.wait, ptr, val);
690 }
691
pv_kick(int cpu)692 static __always_inline void pv_kick(int cpu)
693 {
694 PVOP_VCALL1(pv_lock_ops.kick, cpu);
695 }
696
pv_vcpu_is_preempted(long cpu)697 static __always_inline bool pv_vcpu_is_preempted(long cpu)
698 {
699 return PVOP_CALLEE1(bool, pv_lock_ops.vcpu_is_preempted, cpu);
700 }
701
702 #endif /* SMP && PARAVIRT_SPINLOCKS */
703
704 #ifdef CONFIG_X86_32
705 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
706 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
707
708 /* save and restore all caller-save registers, except return value */
709 #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
710 #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
711
712 #define PV_FLAGS_ARG "0"
713 #define PV_EXTRA_CLOBBERS
714 #define PV_VEXTRA_CLOBBERS
715 #else
716 /* save and restore all caller-save registers, except return value */
717 #define PV_SAVE_ALL_CALLER_REGS \
718 "push %rcx;" \
719 "push %rdx;" \
720 "push %rsi;" \
721 "push %rdi;" \
722 "push %r8;" \
723 "push %r9;" \
724 "push %r10;" \
725 "push %r11;"
726 #define PV_RESTORE_ALL_CALLER_REGS \
727 "pop %r11;" \
728 "pop %r10;" \
729 "pop %r9;" \
730 "pop %r8;" \
731 "pop %rdi;" \
732 "pop %rsi;" \
733 "pop %rdx;" \
734 "pop %rcx;"
735
736 /* We save some registers, but all of them, that's too much. We clobber all
737 * caller saved registers but the argument parameter */
738 #define PV_SAVE_REGS "pushq %%rdi;"
739 #define PV_RESTORE_REGS "popq %%rdi;"
740 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
741 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
742 #define PV_FLAGS_ARG "D"
743 #endif
744
745 /*
746 * Generate a thunk around a function which saves all caller-save
747 * registers except for the return value. This allows C functions to
748 * be called from assembler code where fewer than normal registers are
749 * available. It may also help code generation around calls from C
750 * code if the common case doesn't use many registers.
751 *
752 * When a callee is wrapped in a thunk, the caller can assume that all
753 * arg regs and all scratch registers are preserved across the
754 * call. The return value in rax/eax will not be saved, even for void
755 * functions.
756 */
757 #define PV_THUNK_NAME(func) "__raw_callee_save_" #func
758 #define PV_CALLEE_SAVE_REGS_THUNK(func) \
759 extern typeof(func) __raw_callee_save_##func; \
760 \
761 asm(".pushsection .text;" \
762 ".globl " PV_THUNK_NAME(func) ";" \
763 ".type " PV_THUNK_NAME(func) ", @function;" \
764 PV_THUNK_NAME(func) ":" \
765 FRAME_BEGIN \
766 PV_SAVE_ALL_CALLER_REGS \
767 "call " #func ";" \
768 PV_RESTORE_ALL_CALLER_REGS \
769 FRAME_END \
770 "ret;" \
771 ".popsection")
772
773 /* Get a reference to a callee-save function */
774 #define PV_CALLEE_SAVE(func) \
775 ((struct paravirt_callee_save) { __raw_callee_save_##func })
776
777 /* Promise that "func" already uses the right calling convention */
778 #define __PV_IS_CALLEE_SAVE(func) \
779 ((struct paravirt_callee_save) { func })
780
arch_local_save_flags(void)781 static inline notrace unsigned long arch_local_save_flags(void)
782 {
783 return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl);
784 }
785
arch_local_irq_restore(unsigned long f)786 static inline notrace void arch_local_irq_restore(unsigned long f)
787 {
788 PVOP_VCALLEE1(pv_irq_ops.restore_fl, f);
789 }
790
arch_local_irq_disable(void)791 static inline notrace void arch_local_irq_disable(void)
792 {
793 PVOP_VCALLEE0(pv_irq_ops.irq_disable);
794 }
795
arch_local_irq_enable(void)796 static inline notrace void arch_local_irq_enable(void)
797 {
798 PVOP_VCALLEE0(pv_irq_ops.irq_enable);
799 }
800
arch_local_irq_save(void)801 static inline notrace unsigned long arch_local_irq_save(void)
802 {
803 unsigned long f;
804
805 f = arch_local_save_flags();
806 arch_local_irq_disable();
807 return f;
808 }
809
810
811 /* Make sure as little as possible of this mess escapes. */
812 #undef PARAVIRT_CALL
813 #undef __PVOP_CALL
814 #undef __PVOP_VCALL
815 #undef PVOP_VCALL0
816 #undef PVOP_CALL0
817 #undef PVOP_VCALL1
818 #undef PVOP_CALL1
819 #undef PVOP_VCALL2
820 #undef PVOP_CALL2
821 #undef PVOP_VCALL3
822 #undef PVOP_CALL3
823 #undef PVOP_VCALL4
824 #undef PVOP_CALL4
825
826 extern void default_banner(void);
827
828 #else /* __ASSEMBLY__ */
829
830 #define _PVSITE(ptype, clobbers, ops, word, algn) \
831 771:; \
832 ops; \
833 772:; \
834 .pushsection .parainstructions,"a"; \
835 .align algn; \
836 word 771b; \
837 .byte ptype; \
838 .byte 772b-771b; \
839 .short clobbers; \
840 .popsection
841
842
843 #define COND_PUSH(set, mask, reg) \
844 .if ((~(set)) & mask); push %reg; .endif
845 #define COND_POP(set, mask, reg) \
846 .if ((~(set)) & mask); pop %reg; .endif
847
848 #ifdef CONFIG_X86_64
849
850 #define PV_SAVE_REGS(set) \
851 COND_PUSH(set, CLBR_RAX, rax); \
852 COND_PUSH(set, CLBR_RCX, rcx); \
853 COND_PUSH(set, CLBR_RDX, rdx); \
854 COND_PUSH(set, CLBR_RSI, rsi); \
855 COND_PUSH(set, CLBR_RDI, rdi); \
856 COND_PUSH(set, CLBR_R8, r8); \
857 COND_PUSH(set, CLBR_R9, r9); \
858 COND_PUSH(set, CLBR_R10, r10); \
859 COND_PUSH(set, CLBR_R11, r11)
860 #define PV_RESTORE_REGS(set) \
861 COND_POP(set, CLBR_R11, r11); \
862 COND_POP(set, CLBR_R10, r10); \
863 COND_POP(set, CLBR_R9, r9); \
864 COND_POP(set, CLBR_R8, r8); \
865 COND_POP(set, CLBR_RDI, rdi); \
866 COND_POP(set, CLBR_RSI, rsi); \
867 COND_POP(set, CLBR_RDX, rdx); \
868 COND_POP(set, CLBR_RCX, rcx); \
869 COND_POP(set, CLBR_RAX, rax)
870
871 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
872 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
873 #define PARA_INDIRECT(addr) *addr(%rip)
874 #else
875 #define PV_SAVE_REGS(set) \
876 COND_PUSH(set, CLBR_EAX, eax); \
877 COND_PUSH(set, CLBR_EDI, edi); \
878 COND_PUSH(set, CLBR_ECX, ecx); \
879 COND_PUSH(set, CLBR_EDX, edx)
880 #define PV_RESTORE_REGS(set) \
881 COND_POP(set, CLBR_EDX, edx); \
882 COND_POP(set, CLBR_ECX, ecx); \
883 COND_POP(set, CLBR_EDI, edi); \
884 COND_POP(set, CLBR_EAX, eax)
885
886 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
887 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
888 #define PARA_INDIRECT(addr) *%cs:addr
889 #endif
890
891 #define INTERRUPT_RETURN \
892 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
893 ANNOTATE_RETPOLINE_SAFE; \
894 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret);)
895
896 #define DISABLE_INTERRUPTS(clobbers) \
897 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
898 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
899 ANNOTATE_RETPOLINE_SAFE; \
900 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \
901 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
902
903 #define ENABLE_INTERRUPTS(clobbers) \
904 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
905 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
906 ANNOTATE_RETPOLINE_SAFE; \
907 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \
908 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
909
910 #ifdef CONFIG_X86_32
911 #define GET_CR0_INTO_EAX \
912 push %ecx; push %edx; \
913 ANNOTATE_RETPOLINE_SAFE; \
914 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
915 pop %edx; pop %ecx
916 #else /* !CONFIG_X86_32 */
917
918 /*
919 * If swapgs is used while the userspace stack is still current,
920 * there's no way to call a pvop. The PV replacement *must* be
921 * inlined, or the swapgs instruction must be trapped and emulated.
922 */
923 #define SWAPGS_UNSAFE_STACK \
924 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
925 swapgs)
926
927 /*
928 * Note: swapgs is very special, and in practise is either going to be
929 * implemented with a single "swapgs" instruction or something very
930 * special. Either way, we don't need to save any registers for
931 * it.
932 */
933 #define SWAPGS \
934 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
935 ANNOTATE_RETPOLINE_SAFE; \
936 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs); \
937 )
938
939 #define GET_CR2_INTO_RAX \
940 ANNOTATE_RETPOLINE_SAFE; \
941 call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2);
942
943 #define USERGS_SYSRET64 \
944 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \
945 CLBR_NONE, \
946 ANNOTATE_RETPOLINE_SAFE; \
947 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64);)
948
949 #ifdef CONFIG_DEBUG_ENTRY
950 #define SAVE_FLAGS(clobbers) \
951 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_save_fl), clobbers, \
952 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
953 ANNOTATE_RETPOLINE_SAFE; \
954 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_save_fl); \
955 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
956 #endif
957
958 #endif /* CONFIG_X86_32 */
959
960 #endif /* __ASSEMBLY__ */
961 #else /* CONFIG_PARAVIRT */
962 # define default_banner x86_init_noop
963 #ifndef __ASSEMBLY__
paravirt_arch_dup_mmap(struct mm_struct * oldmm,struct mm_struct * mm)964 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
965 struct mm_struct *mm)
966 {
967 }
968
paravirt_arch_exit_mmap(struct mm_struct * mm)969 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
970 {
971 }
972 #endif /* __ASSEMBLY__ */
973 #endif /* !CONFIG_PARAVIRT */
974 #endif /* _ASM_X86_PARAVIRT_H */
975
