1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2018 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
15
16 #define ZYNQMP_PM_VERSION_MAJOR 1
17 #define ZYNQMP_PM_VERSION_MINOR 0
18
19 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
21
22 #define ZYNQMP_TZ_VERSION_MAJOR 1
23 #define ZYNQMP_TZ_VERSION_MINOR 0
24
25 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
27
28 /* SMC SIP service Call Function Identifier Prefix */
29 #define PM_SIP_SVC 0xC2000000
30 #define PM_GET_TRUSTZONE_VERSION 0xa03
31 #define PM_SET_SUSPEND_MODE 0xa02
32 #define GET_CALLBACK_DATA 0xa01
33
34 /* Number of 32bits values in payload */
35 #define PAYLOAD_ARG_CNT 4U
36
37 /* Number of arguments for a callback */
38 #define CB_ARG_CNT 4
39
40 /* Payload size (consists of callback API ID + arguments) */
41 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
42
43 #define ZYNQMP_PM_MAX_QOS 100U
44
45 /* Node capabilities */
46 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
47 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
48 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
49
50 /*
51 * Firmware FPGA Manager flags
52 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
53 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
54 */
55 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
56 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
57
58 enum pm_api_id {
59 PM_GET_API_VERSION = 1,
60 PM_REQUEST_NODE = 13,
61 PM_RELEASE_NODE,
62 PM_SET_REQUIREMENT,
63 PM_RESET_ASSERT = 17,
64 PM_RESET_GET_STATUS,
65 PM_PM_INIT_FINALIZE = 21,
66 PM_FPGA_LOAD,
67 PM_FPGA_GET_STATUS,
68 PM_GET_CHIPID = 24,
69 PM_IOCTL = 34,
70 PM_QUERY_DATA,
71 PM_CLOCK_ENABLE,
72 PM_CLOCK_DISABLE,
73 PM_CLOCK_GETSTATE,
74 PM_CLOCK_SETDIVIDER,
75 PM_CLOCK_GETDIVIDER,
76 PM_CLOCK_SETRATE,
77 PM_CLOCK_GETRATE,
78 PM_CLOCK_SETPARENT,
79 PM_CLOCK_GETPARENT,
80 };
81
82 /* PMU-FW return status codes */
83 enum pm_ret_status {
84 XST_PM_SUCCESS = 0,
85 XST_PM_INTERNAL = 2000,
86 XST_PM_CONFLICT,
87 XST_PM_NO_ACCESS,
88 XST_PM_INVALID_NODE,
89 XST_PM_DOUBLE_REQ,
90 XST_PM_ABORT_SUSPEND,
91 };
92
93 enum pm_ioctl_id {
94 IOCTL_SET_PLL_FRAC_MODE = 8,
95 IOCTL_GET_PLL_FRAC_MODE,
96 IOCTL_SET_PLL_FRAC_DATA,
97 IOCTL_GET_PLL_FRAC_DATA,
98 };
99
100 enum pm_query_id {
101 PM_QID_INVALID,
102 PM_QID_CLOCK_GET_NAME,
103 PM_QID_CLOCK_GET_TOPOLOGY,
104 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
105 PM_QID_CLOCK_GET_PARENTS,
106 PM_QID_CLOCK_GET_ATTRIBUTES,
107 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
108 };
109
110 enum zynqmp_pm_reset_action {
111 PM_RESET_ACTION_RELEASE,
112 PM_RESET_ACTION_ASSERT,
113 PM_RESET_ACTION_PULSE,
114 };
115
116 enum zynqmp_pm_reset {
117 ZYNQMP_PM_RESET_START = 1000,
118 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
119 ZYNQMP_PM_RESET_PCIE_BRIDGE,
120 ZYNQMP_PM_RESET_PCIE_CTRL,
121 ZYNQMP_PM_RESET_DP,
122 ZYNQMP_PM_RESET_SWDT_CRF,
123 ZYNQMP_PM_RESET_AFI_FM5,
124 ZYNQMP_PM_RESET_AFI_FM4,
125 ZYNQMP_PM_RESET_AFI_FM3,
126 ZYNQMP_PM_RESET_AFI_FM2,
127 ZYNQMP_PM_RESET_AFI_FM1,
128 ZYNQMP_PM_RESET_AFI_FM0,
129 ZYNQMP_PM_RESET_GDMA,
130 ZYNQMP_PM_RESET_GPU_PP1,
131 ZYNQMP_PM_RESET_GPU_PP0,
132 ZYNQMP_PM_RESET_GPU,
133 ZYNQMP_PM_RESET_GT,
134 ZYNQMP_PM_RESET_SATA,
135 ZYNQMP_PM_RESET_ACPU3_PWRON,
136 ZYNQMP_PM_RESET_ACPU2_PWRON,
137 ZYNQMP_PM_RESET_ACPU1_PWRON,
138 ZYNQMP_PM_RESET_ACPU0_PWRON,
139 ZYNQMP_PM_RESET_APU_L2,
140 ZYNQMP_PM_RESET_ACPU3,
141 ZYNQMP_PM_RESET_ACPU2,
142 ZYNQMP_PM_RESET_ACPU1,
143 ZYNQMP_PM_RESET_ACPU0,
144 ZYNQMP_PM_RESET_DDR,
145 ZYNQMP_PM_RESET_APM_FPD,
146 ZYNQMP_PM_RESET_SOFT,
147 ZYNQMP_PM_RESET_GEM0,
148 ZYNQMP_PM_RESET_GEM1,
149 ZYNQMP_PM_RESET_GEM2,
150 ZYNQMP_PM_RESET_GEM3,
151 ZYNQMP_PM_RESET_QSPI,
152 ZYNQMP_PM_RESET_UART0,
153 ZYNQMP_PM_RESET_UART1,
154 ZYNQMP_PM_RESET_SPI0,
155 ZYNQMP_PM_RESET_SPI1,
156 ZYNQMP_PM_RESET_SDIO0,
157 ZYNQMP_PM_RESET_SDIO1,
158 ZYNQMP_PM_RESET_CAN0,
159 ZYNQMP_PM_RESET_CAN1,
160 ZYNQMP_PM_RESET_I2C0,
161 ZYNQMP_PM_RESET_I2C1,
162 ZYNQMP_PM_RESET_TTC0,
163 ZYNQMP_PM_RESET_TTC1,
164 ZYNQMP_PM_RESET_TTC2,
165 ZYNQMP_PM_RESET_TTC3,
166 ZYNQMP_PM_RESET_SWDT_CRL,
167 ZYNQMP_PM_RESET_NAND,
168 ZYNQMP_PM_RESET_ADMA,
169 ZYNQMP_PM_RESET_GPIO,
170 ZYNQMP_PM_RESET_IOU_CC,
171 ZYNQMP_PM_RESET_TIMESTAMP,
172 ZYNQMP_PM_RESET_RPU_R50,
173 ZYNQMP_PM_RESET_RPU_R51,
174 ZYNQMP_PM_RESET_RPU_AMBA,
175 ZYNQMP_PM_RESET_OCM,
176 ZYNQMP_PM_RESET_RPU_PGE,
177 ZYNQMP_PM_RESET_USB0_CORERESET,
178 ZYNQMP_PM_RESET_USB1_CORERESET,
179 ZYNQMP_PM_RESET_USB0_HIBERRESET,
180 ZYNQMP_PM_RESET_USB1_HIBERRESET,
181 ZYNQMP_PM_RESET_USB0_APB,
182 ZYNQMP_PM_RESET_USB1_APB,
183 ZYNQMP_PM_RESET_IPI,
184 ZYNQMP_PM_RESET_APM_LPD,
185 ZYNQMP_PM_RESET_RTC,
186 ZYNQMP_PM_RESET_SYSMON,
187 ZYNQMP_PM_RESET_AFI_FM6,
188 ZYNQMP_PM_RESET_LPD_SWDT,
189 ZYNQMP_PM_RESET_FPD,
190 ZYNQMP_PM_RESET_RPU_DBG1,
191 ZYNQMP_PM_RESET_RPU_DBG0,
192 ZYNQMP_PM_RESET_DBG_LPD,
193 ZYNQMP_PM_RESET_DBG_FPD,
194 ZYNQMP_PM_RESET_APLL,
195 ZYNQMP_PM_RESET_DPLL,
196 ZYNQMP_PM_RESET_VPLL,
197 ZYNQMP_PM_RESET_IOPLL,
198 ZYNQMP_PM_RESET_RPLL,
199 ZYNQMP_PM_RESET_GPO3_PL_0,
200 ZYNQMP_PM_RESET_GPO3_PL_1,
201 ZYNQMP_PM_RESET_GPO3_PL_2,
202 ZYNQMP_PM_RESET_GPO3_PL_3,
203 ZYNQMP_PM_RESET_GPO3_PL_4,
204 ZYNQMP_PM_RESET_GPO3_PL_5,
205 ZYNQMP_PM_RESET_GPO3_PL_6,
206 ZYNQMP_PM_RESET_GPO3_PL_7,
207 ZYNQMP_PM_RESET_GPO3_PL_8,
208 ZYNQMP_PM_RESET_GPO3_PL_9,
209 ZYNQMP_PM_RESET_GPO3_PL_10,
210 ZYNQMP_PM_RESET_GPO3_PL_11,
211 ZYNQMP_PM_RESET_GPO3_PL_12,
212 ZYNQMP_PM_RESET_GPO3_PL_13,
213 ZYNQMP_PM_RESET_GPO3_PL_14,
214 ZYNQMP_PM_RESET_GPO3_PL_15,
215 ZYNQMP_PM_RESET_GPO3_PL_16,
216 ZYNQMP_PM_RESET_GPO3_PL_17,
217 ZYNQMP_PM_RESET_GPO3_PL_18,
218 ZYNQMP_PM_RESET_GPO3_PL_19,
219 ZYNQMP_PM_RESET_GPO3_PL_20,
220 ZYNQMP_PM_RESET_GPO3_PL_21,
221 ZYNQMP_PM_RESET_GPO3_PL_22,
222 ZYNQMP_PM_RESET_GPO3_PL_23,
223 ZYNQMP_PM_RESET_GPO3_PL_24,
224 ZYNQMP_PM_RESET_GPO3_PL_25,
225 ZYNQMP_PM_RESET_GPO3_PL_26,
226 ZYNQMP_PM_RESET_GPO3_PL_27,
227 ZYNQMP_PM_RESET_GPO3_PL_28,
228 ZYNQMP_PM_RESET_GPO3_PL_29,
229 ZYNQMP_PM_RESET_GPO3_PL_30,
230 ZYNQMP_PM_RESET_GPO3_PL_31,
231 ZYNQMP_PM_RESET_RPU_LS,
232 ZYNQMP_PM_RESET_PS_ONLY,
233 ZYNQMP_PM_RESET_PL,
234 ZYNQMP_PM_RESET_PS_PL0,
235 ZYNQMP_PM_RESET_PS_PL1,
236 ZYNQMP_PM_RESET_PS_PL2,
237 ZYNQMP_PM_RESET_PS_PL3,
238 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
239 };
240
241 enum zynqmp_pm_suspend_reason {
242 SUSPEND_POWER_REQUEST = 201,
243 SUSPEND_ALERT,
244 SUSPEND_SYSTEM_SHUTDOWN,
245 };
246
247 enum zynqmp_pm_request_ack {
248 ZYNQMP_PM_REQUEST_ACK_NO = 1,
249 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
250 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
251 };
252
253 /**
254 * struct zynqmp_pm_query_data - PM query data
255 * @qid: query ID
256 * @arg1: Argument 1 of query data
257 * @arg2: Argument 2 of query data
258 * @arg3: Argument 3 of query data
259 */
260 struct zynqmp_pm_query_data {
261 u32 qid;
262 u32 arg1;
263 u32 arg2;
264 u32 arg3;
265 };
266
267 struct zynqmp_eemi_ops {
268 int (*get_api_version)(u32 *version);
269 int (*get_chipid)(u32 *idcode, u32 *version);
270 int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
271 int (*fpga_get_status)(u32 *value);
272 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
273 int (*clock_enable)(u32 clock_id);
274 int (*clock_disable)(u32 clock_id);
275 int (*clock_getstate)(u32 clock_id, u32 *state);
276 int (*clock_setdivider)(u32 clock_id, u32 divider);
277 int (*clock_getdivider)(u32 clock_id, u32 *divider);
278 int (*clock_setrate)(u32 clock_id, u64 rate);
279 int (*clock_getrate)(u32 clock_id, u64 *rate);
280 int (*clock_setparent)(u32 clock_id, u32 parent_id);
281 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
282 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
283 int (*reset_assert)(const enum zynqmp_pm_reset reset,
284 const enum zynqmp_pm_reset_action assert_flag);
285 int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
286 int (*init_finalize)(void);
287 int (*set_suspend_mode)(u32 mode);
288 int (*request_node)(const u32 node,
289 const u32 capabilities,
290 const u32 qos,
291 const enum zynqmp_pm_request_ack ack);
292 int (*release_node)(const u32 node);
293 int (*set_requirement)(const u32 node,
294 const u32 capabilities,
295 const u32 qos,
296 const enum zynqmp_pm_request_ack ack);
297 };
298
299 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
300 u32 arg2, u32 arg3, u32 *ret_payload);
301
302 #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
303 const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
304 #else
zynqmp_pm_get_eemi_ops(void)305 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
306 {
307 return ERR_PTR(-ENODEV);
308 }
309 #endif
310
311 #endif /* __FIRMWARE_ZYNQMP_H__ */
312
