1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __SOC15_COMMON_H__ 25 #define __SOC15_COMMON_H__ 26 27 /* Register Access Macros */ 28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 29 30 #define WREG32_FIELD15(ip, idx, reg, field, val) \ 31 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 32 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ 33 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 34 35 #define RREG32_SOC15(ip, inst, reg) \ 36 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 37 38 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ 39 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) 40 41 #define WREG32_SOC15(ip, inst, reg, value) \ 42 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) 43 44 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ 45 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) 46 47 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ 48 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) 49 50 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \ 51 do { \ 52 uint32_t old_ = 0; \ 53 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 54 uint32_t loop = adev->usec_timeout; \ 55 while ((tmp_ & (mask)) != (expected_value)) { \ 56 if (old_ != tmp_) { \ 57 loop = adev->usec_timeout; \ 58 old_ = tmp_; \ 59 } else \ 60 udelay(1); \ 61 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 62 loop--; \ 63 if (!loop) { \ 64 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \ 65 inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \ 66 ret = -ETIMEDOUT; \ 67 break; \ 68 } \ 69 } \ 70 } while (0) 71 72 #define AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(a) (amdgpu_sriov_vf((a)) && !amdgpu_sriov_runtime((a))) 73 #define WREG32_RLC(reg, value) \ 74 do { \ 75 if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) { \ 76 uint32_t i = 0; \ 77 uint32_t retries = 50000; \ 78 uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \ 79 uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \ 80 uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \ 81 WREG32(r0, value); \ 82 WREG32(r1, (reg | 0x80000000)); \ 83 WREG32(spare_int, 0x1); \ 84 for (i = 0; i < retries; i++) { \ 85 u32 tmp = RREG32(r1); \ 86 if (!(tmp & 0x80000000)) \ 87 break; \ 88 udelay(10); \ 89 } \ 90 if (i >= retries) \ 91 pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ 92 } else { \ 93 WREG32(reg, value); \ 94 } \ 95 } while (0) 96 97 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ 98 do { \ 99 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ 100 if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) { \ 101 uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \ 102 uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \ 103 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \ 104 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \ 105 if (target_reg == grbm_cntl) \ 106 WREG32(r2, value); \ 107 else if (target_reg == grbm_idx) \ 108 WREG32(r3, value); \ 109 WREG32(target_reg, value); \ 110 } else { \ 111 WREG32(target_reg, value); \ 112 } \ 113 } while (0) 114 115 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ 116 do { \ 117 uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ 118 WREG32_RLC(target_reg, value); \ 119 } while (0) 120 121 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ 122 WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ 123 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ 124 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 125 126 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ 127 WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value) 128 129 #endif 130
