1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 * Microsemi Ocelot Switch driver 3 * Copyright (c) 2019 Microsemi Corporation 4 */ 5 6 #ifndef _OCELOT_VCAP_H_ 7 #define _OCELOT_VCAP_H_ 8 9 #include <soc/mscc/ocelot.h> 10 11 /* ================================================================= 12 * VCAP Common 13 * ================================================================= 14 */ 15 16 enum { 17 VCAP_ES0, 18 VCAP_IS1, 19 VCAP_IS2, 20 __VCAP_COUNT, 21 }; 22 23 #define OCELOT_NUM_VCAP_BLOCKS __VCAP_COUNT 24 25 struct vcap_props { 26 u16 tg_width; /* Type-group width (in bits) */ 27 u16 sw_count; /* Sub word count */ 28 u16 entry_count; /* Entry count */ 29 u16 entry_words; /* Number of entry words */ 30 u16 entry_width; /* Entry width (in bits) */ 31 u16 action_count; /* Action count */ 32 u16 action_words; /* Number of action words */ 33 u16 action_width; /* Action width (in bits) */ 34 u16 action_type_width; /* Action type width (in bits) */ 35 struct { 36 u16 width; /* Action type width (in bits) */ 37 u16 count; /* Action type sub word count */ 38 } action_table[2]; 39 u16 counter_words; /* Number of counter words */ 40 u16 counter_width; /* Counter width (in bits) */ 41 42 enum ocelot_target target; 43 44 const struct vcap_field *keys; 45 const struct vcap_field *actions; 46 }; 47 48 /* VCAP Type-Group values */ 49 #define VCAP_TG_NONE 0 /* Entry is invalid */ 50 #define VCAP_TG_FULL 1 /* Full entry */ 51 #define VCAP_TG_HALF 2 /* Half entry */ 52 #define VCAP_TG_QUARTER 3 /* Quarter entry */ 53 54 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22)) 55 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22) 56 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22) 57 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 58 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 59 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 60 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3)) 61 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3) 62 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3) 63 #define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2) 64 #define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1) 65 #define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) 66 67 #define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16)) 68 #define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16) 69 #define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16) 70 #define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0)) 71 #define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0) 72 73 #define VCAP_CACHE_ENTRY_DAT_RSZ 0x4 74 75 #define VCAP_CACHE_MASK_DAT_RSZ 0x4 76 77 #define VCAP_CACHE_ACTION_DAT_RSZ 0x4 78 79 #define VCAP_CACHE_CNT_DAT_RSZ 0x4 80 81 #define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 82 83 #define TCAM_BIST_CTRL_TCAM_BIST BIT(1) 84 #define TCAM_BIST_CTRL_TCAM_INIT BIT(0) 85 86 #define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8) 87 #define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7) 88 #define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6) 89 #define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0)) 90 #define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0) 91 92 #define TCAM_BIST_STAT_BIST_RT_ERR BIT(15) 93 #define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14) 94 #define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13) 95 #define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12) 96 #define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11) 97 #define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10) 98 #define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9) 99 #define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8) 100 #define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7) 101 #define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6) 102 #define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5) 103 #define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4) 104 #define TCAM_BIST_STAT_BIST_RUN BIT(3) 105 #define TCAM_BIST_STAT_BIST_ERR BIT(2) 106 #define TCAM_BIST_STAT_BIST_BUSY BIT(1) 107 #define TCAM_BIST_STAT_TCAM_RDY BIT(0) 108 109 /* ================================================================= 110 * VCAP IS2 111 * ================================================================= 112 */ 113 114 /* IS2 half key types */ 115 #define IS2_TYPE_ETYPE 0 116 #define IS2_TYPE_LLC 1 117 #define IS2_TYPE_SNAP 2 118 #define IS2_TYPE_ARP 3 119 #define IS2_TYPE_IP_UDP_TCP 4 120 #define IS2_TYPE_IP_OTHER 5 121 #define IS2_TYPE_IPV6 6 122 #define IS2_TYPE_OAM 7 123 #define IS2_TYPE_SMAC_SIP6 8 124 #define IS2_TYPE_ANY 100 /* Pseudo type */ 125 126 /* IS2 half key type mask for matching any IP */ 127 #define IS2_TYPE_MASK_IP_ANY 0xe 128 129 enum { 130 IS2_ACTION_TYPE_NORMAL, 131 IS2_ACTION_TYPE_SMAC_SIP, 132 IS2_ACTION_TYPE_MAX, 133 }; 134 135 /* IS2 MASK_MODE values */ 136 #define IS2_ACT_MASK_MODE_NONE 0 137 #define IS2_ACT_MASK_MODE_FILTER 1 138 #define IS2_ACT_MASK_MODE_POLICY 2 139 #define IS2_ACT_MASK_MODE_REDIR 3 140 141 /* IS2 REW_OP values */ 142 #define IS2_ACT_REW_OP_NONE 0 143 #define IS2_ACT_REW_OP_PTP_ONE 2 144 #define IS2_ACT_REW_OP_PTP_TWO 3 145 #define IS2_ACT_REW_OP_SPECIAL 8 146 #define IS2_ACT_REW_OP_PTP_ORG 9 147 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3)) 148 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3)) 149 #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5)) 150 #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7) 151 152 #define VCAP_PORT_WIDTH 4 153 154 /* IS2 quarter key - SMAC_SIP4 */ 155 #define IS2_QKO_IGR_PORT 0 156 #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH 157 #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT) 158 #define IS2_QKL_L2_SMAC 48 159 #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC) 160 #define IS2_QKL_L3_IP4_SIP 32 161 162 enum vcap_is2_half_key_field { 163 /* Common */ 164 VCAP_IS2_TYPE, 165 VCAP_IS2_HK_FIRST, 166 VCAP_IS2_HK_PAG, 167 VCAP_IS2_HK_RSV1, 168 VCAP_IS2_HK_IGR_PORT_MASK, 169 VCAP_IS2_HK_RSV2, 170 VCAP_IS2_HK_HOST_MATCH, 171 VCAP_IS2_HK_L2_MC, 172 VCAP_IS2_HK_L2_BC, 173 VCAP_IS2_HK_VLAN_TAGGED, 174 VCAP_IS2_HK_VID, 175 VCAP_IS2_HK_DEI, 176 VCAP_IS2_HK_PCP, 177 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 178 VCAP_IS2_HK_L2_DMAC, 179 VCAP_IS2_HK_L2_SMAC, 180 /* MAC_ETYPE (TYPE=000) */ 181 VCAP_IS2_HK_MAC_ETYPE_ETYPE, 182 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 183 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1, 184 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2, 185 /* MAC_LLC (TYPE=001) */ 186 VCAP_IS2_HK_MAC_LLC_DMAC, 187 VCAP_IS2_HK_MAC_LLC_SMAC, 188 VCAP_IS2_HK_MAC_LLC_L2_LLC, 189 /* MAC_SNAP (TYPE=010) */ 190 VCAP_IS2_HK_MAC_SNAP_SMAC, 191 VCAP_IS2_HK_MAC_SNAP_DMAC, 192 VCAP_IS2_HK_MAC_SNAP_L2_SNAP, 193 /* MAC_ARP (TYPE=011) */ 194 VCAP_IS2_HK_MAC_ARP_SMAC, 195 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK, 196 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK, 197 VCAP_IS2_HK_MAC_ARP_LEN_OK, 198 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH, 199 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH, 200 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN, 201 VCAP_IS2_HK_MAC_ARP_OPCODE, 202 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP, 203 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP, 204 VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP, 205 /* IP4_TCP_UDP / IP4_OTHER common */ 206 VCAP_IS2_HK_IP4, 207 VCAP_IS2_HK_L3_FRAGMENT, 208 VCAP_IS2_HK_L3_FRAG_OFS_GT0, 209 VCAP_IS2_HK_L3_OPTIONS, 210 VCAP_IS2_HK_IP4_L3_TTL_GT0, 211 VCAP_IS2_HK_L3_TOS, 212 VCAP_IS2_HK_L3_IP4_DIP, 213 VCAP_IS2_HK_L3_IP4_SIP, 214 VCAP_IS2_HK_DIP_EQ_SIP, 215 /* IP4_TCP_UDP (TYPE=100) */ 216 VCAP_IS2_HK_TCP, 217 VCAP_IS2_HK_L4_SPORT, 218 VCAP_IS2_HK_L4_DPORT, 219 VCAP_IS2_HK_L4_RNG, 220 VCAP_IS2_HK_L4_SPORT_EQ_DPORT, 221 VCAP_IS2_HK_L4_SEQUENCE_EQ0, 222 VCAP_IS2_HK_L4_URG, 223 VCAP_IS2_HK_L4_ACK, 224 VCAP_IS2_HK_L4_PSH, 225 VCAP_IS2_HK_L4_RST, 226 VCAP_IS2_HK_L4_SYN, 227 VCAP_IS2_HK_L4_FIN, 228 VCAP_IS2_HK_L4_1588_DOM, 229 VCAP_IS2_HK_L4_1588_VER, 230 /* IP4_OTHER (TYPE=101) */ 231 VCAP_IS2_HK_IP4_L3_PROTO, 232 VCAP_IS2_HK_L3_PAYLOAD, 233 /* IP6_STD (TYPE=110) */ 234 VCAP_IS2_HK_IP6_L3_TTL_GT0, 235 VCAP_IS2_HK_IP6_L3_PROTO, 236 VCAP_IS2_HK_L3_IP6_SIP, 237 /* OAM (TYPE=111) */ 238 VCAP_IS2_HK_OAM_MEL_FLAGS, 239 VCAP_IS2_HK_OAM_VER, 240 VCAP_IS2_HK_OAM_OPCODE, 241 VCAP_IS2_HK_OAM_FLAGS, 242 VCAP_IS2_HK_OAM_MEPID, 243 VCAP_IS2_HK_OAM_CCM_CNTS_EQ0, 244 VCAP_IS2_HK_OAM_IS_Y1731, 245 }; 246 247 struct vcap_field { 248 int offset; 249 int length; 250 }; 251 252 enum vcap_is2_action_field { 253 VCAP_IS2_ACT_HIT_ME_ONCE, 254 VCAP_IS2_ACT_CPU_COPY_ENA, 255 VCAP_IS2_ACT_CPU_QU_NUM, 256 VCAP_IS2_ACT_MASK_MODE, 257 VCAP_IS2_ACT_MIRROR_ENA, 258 VCAP_IS2_ACT_LRN_DIS, 259 VCAP_IS2_ACT_POLICE_ENA, 260 VCAP_IS2_ACT_POLICE_IDX, 261 VCAP_IS2_ACT_POLICE_VCAP_ONLY, 262 VCAP_IS2_ACT_PORT_MASK, 263 VCAP_IS2_ACT_REW_OP, 264 VCAP_IS2_ACT_SMAC_REPLACE_ENA, 265 VCAP_IS2_ACT_RSV, 266 VCAP_IS2_ACT_ACL_ID, 267 VCAP_IS2_ACT_HIT_CNT, 268 }; 269 270 /* ================================================================= 271 * VCAP IS1 272 * ================================================================= 273 */ 274 275 /* IS1 half key types */ 276 #define IS1_TYPE_S1_NORMAL 0 277 #define IS1_TYPE_S1_5TUPLE_IP4 1 278 279 /* IS1 full key types */ 280 #define IS1_TYPE_S1_NORMAL_IP6 0 281 #define IS1_TYPE_S1_7TUPLE 1 282 #define IS2_TYPE_S1_5TUPLE_IP6 2 283 284 enum { 285 IS1_ACTION_TYPE_NORMAL, 286 IS1_ACTION_TYPE_MAX, 287 }; 288 289 enum vcap_is1_half_key_field { 290 VCAP_IS1_HK_TYPE, 291 VCAP_IS1_HK_LOOKUP, 292 VCAP_IS1_HK_IGR_PORT_MASK, 293 VCAP_IS1_HK_RSV, 294 VCAP_IS1_HK_OAM_Y1731, 295 VCAP_IS1_HK_L2_MC, 296 VCAP_IS1_HK_L2_BC, 297 VCAP_IS1_HK_IP_MC, 298 VCAP_IS1_HK_VLAN_TAGGED, 299 VCAP_IS1_HK_VLAN_DBL_TAGGED, 300 VCAP_IS1_HK_TPID, 301 VCAP_IS1_HK_VID, 302 VCAP_IS1_HK_DEI, 303 VCAP_IS1_HK_PCP, 304 /* Specific Fields for IS1 Half Key S1_NORMAL */ 305 VCAP_IS1_HK_L2_SMAC, 306 VCAP_IS1_HK_ETYPE_LEN, 307 VCAP_IS1_HK_ETYPE, 308 VCAP_IS1_HK_IP_SNAP, 309 VCAP_IS1_HK_IP4, 310 VCAP_IS1_HK_L3_FRAGMENT, 311 VCAP_IS1_HK_L3_FRAG_OFS_GT0, 312 VCAP_IS1_HK_L3_OPTIONS, 313 VCAP_IS1_HK_L3_DSCP, 314 VCAP_IS1_HK_L3_IP4_SIP, 315 VCAP_IS1_HK_TCP_UDP, 316 VCAP_IS1_HK_TCP, 317 VCAP_IS1_HK_L4_SPORT, 318 VCAP_IS1_HK_L4_RNG, 319 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 320 VCAP_IS1_HK_IP4_INNER_TPID, 321 VCAP_IS1_HK_IP4_INNER_VID, 322 VCAP_IS1_HK_IP4_INNER_DEI, 323 VCAP_IS1_HK_IP4_INNER_PCP, 324 VCAP_IS1_HK_IP4_IP4, 325 VCAP_IS1_HK_IP4_L3_FRAGMENT, 326 VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0, 327 VCAP_IS1_HK_IP4_L3_OPTIONS, 328 VCAP_IS1_HK_IP4_L3_DSCP, 329 VCAP_IS1_HK_IP4_L3_IP4_DIP, 330 VCAP_IS1_HK_IP4_L3_IP4_SIP, 331 VCAP_IS1_HK_IP4_L3_PROTO, 332 VCAP_IS1_HK_IP4_TCP_UDP, 333 VCAP_IS1_HK_IP4_TCP, 334 VCAP_IS1_HK_IP4_L4_RNG, 335 VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE, 336 }; 337 338 enum vcap_is1_action_field { 339 VCAP_IS1_ACT_DSCP_ENA, 340 VCAP_IS1_ACT_DSCP_VAL, 341 VCAP_IS1_ACT_QOS_ENA, 342 VCAP_IS1_ACT_QOS_VAL, 343 VCAP_IS1_ACT_DP_ENA, 344 VCAP_IS1_ACT_DP_VAL, 345 VCAP_IS1_ACT_PAG_OVERRIDE_MASK, 346 VCAP_IS1_ACT_PAG_VAL, 347 VCAP_IS1_ACT_RSV, 348 VCAP_IS1_ACT_VID_REPLACE_ENA, 349 VCAP_IS1_ACT_VID_ADD_VAL, 350 VCAP_IS1_ACT_FID_SEL, 351 VCAP_IS1_ACT_FID_VAL, 352 VCAP_IS1_ACT_PCP_DEI_ENA, 353 VCAP_IS1_ACT_PCP_VAL, 354 VCAP_IS1_ACT_DEI_VAL, 355 VCAP_IS1_ACT_VLAN_POP_CNT_ENA, 356 VCAP_IS1_ACT_VLAN_POP_CNT, 357 VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA, 358 VCAP_IS1_ACT_HIT_STICKY, 359 }; 360 361 /* ================================================================= 362 * VCAP ES0 363 * ================================================================= 364 */ 365 366 enum { 367 ES0_ACTION_TYPE_NORMAL, 368 ES0_ACTION_TYPE_MAX, 369 }; 370 371 enum vcap_es0_key_field { 372 VCAP_ES0_EGR_PORT, 373 VCAP_ES0_IGR_PORT, 374 VCAP_ES0_RSV, 375 VCAP_ES0_L2_MC, 376 VCAP_ES0_L2_BC, 377 VCAP_ES0_VID, 378 VCAP_ES0_DP, 379 VCAP_ES0_PCP, 380 }; 381 382 enum vcap_es0_action_field { 383 VCAP_ES0_ACT_PUSH_OUTER_TAG, 384 VCAP_ES0_ACT_PUSH_INNER_TAG, 385 VCAP_ES0_ACT_TAG_A_TPID_SEL, 386 VCAP_ES0_ACT_TAG_A_VID_SEL, 387 VCAP_ES0_ACT_TAG_A_PCP_SEL, 388 VCAP_ES0_ACT_TAG_A_DEI_SEL, 389 VCAP_ES0_ACT_TAG_B_TPID_SEL, 390 VCAP_ES0_ACT_TAG_B_VID_SEL, 391 VCAP_ES0_ACT_TAG_B_PCP_SEL, 392 VCAP_ES0_ACT_TAG_B_DEI_SEL, 393 VCAP_ES0_ACT_VID_A_VAL, 394 VCAP_ES0_ACT_PCP_A_VAL, 395 VCAP_ES0_ACT_DEI_A_VAL, 396 VCAP_ES0_ACT_VID_B_VAL, 397 VCAP_ES0_ACT_PCP_B_VAL, 398 VCAP_ES0_ACT_DEI_B_VAL, 399 VCAP_ES0_ACT_RSV, 400 VCAP_ES0_ACT_HIT_STICKY, 401 }; 402 403 #endif /* _OCELOT_VCAP_H_ */ 404
