1 /*
2 * linux/include/mfd/ucb1x00.h
3 *
4 * Copyright (C) 2001 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10 #ifndef UCB1200_H
11 #define UCB1200_H
12
13 #include <linux/device.h>
14 #include <linux/mfd/mcp.h>
15 #include <linux/gpio.h>
16 #include <linux/mutex.h>
17
18 #define UCB_IO_DATA 0x00
19 #define UCB_IO_DIR 0x01
20
21 #define UCB_IO_0 (1 << 0)
22 #define UCB_IO_1 (1 << 1)
23 #define UCB_IO_2 (1 << 2)
24 #define UCB_IO_3 (1 << 3)
25 #define UCB_IO_4 (1 << 4)
26 #define UCB_IO_5 (1 << 5)
27 #define UCB_IO_6 (1 << 6)
28 #define UCB_IO_7 (1 << 7)
29 #define UCB_IO_8 (1 << 8)
30 #define UCB_IO_9 (1 << 9)
31
32 #define UCB_IE_RIS 0x02
33 #define UCB_IE_FAL 0x03
34 #define UCB_IE_STATUS 0x04
35 #define UCB_IE_CLEAR 0x04
36 #define UCB_IE_ADC (1 << 11)
37 #define UCB_IE_TSPX (1 << 12)
38 #define UCB_IE_TSMX (1 << 13)
39 #define UCB_IE_TCLIP (1 << 14)
40 #define UCB_IE_ACLIP (1 << 15)
41
42 #define UCB_IRQ_TSPX 12
43
44 #define UCB_TC_A 0x05
45 #define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
46 #define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
47
48 #define UCB_TC_B 0x06
49 #define UCB_TC_B_VOICE_ENA (1 << 3)
50 #define UCB_TC_B_CLIP (1 << 4)
51 #define UCB_TC_B_ATT (1 << 6)
52 #define UCB_TC_B_SIDE_ENA (1 << 11)
53 #define UCB_TC_B_MUTE (1 << 13)
54 #define UCB_TC_B_IN_ENA (1 << 14)
55 #define UCB_TC_B_OUT_ENA (1 << 15)
56
57 #define UCB_AC_A 0x07
58 #define UCB_AC_B 0x08
59 #define UCB_AC_B_LOOP (1 << 8)
60 #define UCB_AC_B_MUTE (1 << 13)
61 #define UCB_AC_B_IN_ENA (1 << 14)
62 #define UCB_AC_B_OUT_ENA (1 << 15)
63
64 #define UCB_TS_CR 0x09
65 #define UCB_TS_CR_TSMX_POW (1 << 0)
66 #define UCB_TS_CR_TSPX_POW (1 << 1)
67 #define UCB_TS_CR_TSMY_POW (1 << 2)
68 #define UCB_TS_CR_TSPY_POW (1 << 3)
69 #define UCB_TS_CR_TSMX_GND (1 << 4)
70 #define UCB_TS_CR_TSPX_GND (1 << 5)
71 #define UCB_TS_CR_TSMY_GND (1 << 6)
72 #define UCB_TS_CR_TSPY_GND (1 << 7)
73 #define UCB_TS_CR_MODE_INT (0 << 8)
74 #define UCB_TS_CR_MODE_PRES (1 << 8)
75 #define UCB_TS_CR_MODE_POS (2 << 8)
76 #define UCB_TS_CR_BIAS_ENA (1 << 11)
77 #define UCB_TS_CR_TSPX_LOW (1 << 12)
78 #define UCB_TS_CR_TSMX_LOW (1 << 13)
79
80 #define UCB_ADC_CR 0x0a
81 #define UCB_ADC_SYNC_ENA (1 << 0)
82 #define UCB_ADC_VREFBYP_CON (1 << 1)
83 #define UCB_ADC_INP_TSPX (0 << 2)
84 #define UCB_ADC_INP_TSMX (1 << 2)
85 #define UCB_ADC_INP_TSPY (2 << 2)
86 #define UCB_ADC_INP_TSMY (3 << 2)
87 #define UCB_ADC_INP_AD0 (4 << 2)
88 #define UCB_ADC_INP_AD1 (5 << 2)
89 #define UCB_ADC_INP_AD2 (6 << 2)
90 #define UCB_ADC_INP_AD3 (7 << 2)
91 #define UCB_ADC_EXT_REF (1 << 5)
92 #define UCB_ADC_START (1 << 7)
93 #define UCB_ADC_ENA (1 << 15)
94
95 #define UCB_ADC_DATA 0x0b
96 #define UCB_ADC_DAT_VAL (1 << 15)
97 #define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
98
99 #define UCB_ID 0x0c
100 #define UCB_ID_1200 0x1004
101 #define UCB_ID_1300 0x1005
102 #define UCB_ID_TC35143 0x9712
103
104 #define UCB_MODE 0x0d
105 #define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
106 #define UCB_MODE_AUD_OFF_CAN (1 << 13)
107
108 enum ucb1x00_reset {
109 UCB_RST_PROBE,
110 UCB_RST_RESUME,
111 UCB_RST_SUSPEND,
112 UCB_RST_REMOVE,
113 UCB_RST_PROBE_FAIL,
114 };
115
116 struct ucb1x00_plat_data {
117 void (*reset)(enum ucb1x00_reset);
118 unsigned irq_base;
119 int gpio_base;
120 unsigned can_wakeup;
121 };
122
123 struct ucb1x00 {
124 raw_spinlock_t irq_lock;
125 struct mcp *mcp;
126 unsigned int irq;
127 int irq_base;
128 struct mutex adc_mutex;
129 spinlock_t io_lock;
130 u16 id;
131 u16 io_dir;
132 u16 io_out;
133 u16 adc_cr;
134 u16 irq_fal_enbl;
135 u16 irq_ris_enbl;
136 u16 irq_mask;
137 u16 irq_wake;
138 struct device dev;
139 struct list_head node;
140 struct list_head devs;
141 struct gpio_chip gpio;
142 };
143
144 struct ucb1x00_driver;
145
146 struct ucb1x00_dev {
147 struct list_head dev_node;
148 struct list_head drv_node;
149 struct ucb1x00 *ucb;
150 struct ucb1x00_driver *drv;
151 void *priv;
152 };
153
154 struct ucb1x00_driver {
155 struct list_head node;
156 struct list_head devs;
157 int (*add)(struct ucb1x00_dev *dev);
158 void (*remove)(struct ucb1x00_dev *dev);
159 int (*suspend)(struct ucb1x00_dev *dev);
160 int (*resume)(struct ucb1x00_dev *dev);
161 };
162
163 #define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
164
165 int ucb1x00_register_driver(struct ucb1x00_driver *);
166 void ucb1x00_unregister_driver(struct ucb1x00_driver *);
167
168 /**
169 * ucb1x00_clkrate - return the UCB1x00 SIB clock rate
170 * @ucb: UCB1x00 structure describing chip
171 *
172 * Return the SIB clock rate in Hz.
173 */
ucb1x00_clkrate(struct ucb1x00 * ucb)174 static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
175 {
176 return mcp_get_sclk_rate(ucb->mcp);
177 }
178
179 /**
180 * ucb1x00_enable - enable the UCB1x00 SIB clock
181 * @ucb: UCB1x00 structure describing chip
182 *
183 * Enable the SIB clock. This can be called multiple times.
184 */
ucb1x00_enable(struct ucb1x00 * ucb)185 static inline void ucb1x00_enable(struct ucb1x00 *ucb)
186 {
187 mcp_enable(ucb->mcp);
188 }
189
190 /**
191 * ucb1x00_disable - disable the UCB1x00 SIB clock
192 * @ucb: UCB1x00 structure describing chip
193 *
194 * Disable the SIB clock. The SIB clock will only be disabled
195 * when the number of ucb1x00_enable calls match the number of
196 * ucb1x00_disable calls.
197 */
ucb1x00_disable(struct ucb1x00 * ucb)198 static inline void ucb1x00_disable(struct ucb1x00 *ucb)
199 {
200 mcp_disable(ucb->mcp);
201 }
202
203 /**
204 * ucb1x00_reg_write - write a UCB1x00 register
205 * @ucb: UCB1x00 structure describing chip
206 * @reg: UCB1x00 4-bit register index to write
207 * @val: UCB1x00 16-bit value to write
208 *
209 * Write the UCB1x00 register @reg with value @val. The SIB
210 * clock must be running for this function to return.
211 */
ucb1x00_reg_write(struct ucb1x00 * ucb,unsigned int reg,unsigned int val)212 static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
213 {
214 mcp_reg_write(ucb->mcp, reg, val);
215 }
216
217 /**
218 * ucb1x00_reg_read - read a UCB1x00 register
219 * @ucb: UCB1x00 structure describing chip
220 * @reg: UCB1x00 4-bit register index to write
221 *
222 * Read the UCB1x00 register @reg and return its value. The SIB
223 * clock must be running for this function to return.
224 */
ucb1x00_reg_read(struct ucb1x00 * ucb,unsigned int reg)225 static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
226 {
227 return mcp_reg_read(ucb->mcp, reg);
228 }
229 /**
230 * ucb1x00_set_audio_divisor -
231 * @ucb: UCB1x00 structure describing chip
232 * @div: SIB clock divisor
233 */
ucb1x00_set_audio_divisor(struct ucb1x00 * ucb,unsigned int div)234 static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
235 {
236 mcp_set_audio_divisor(ucb->mcp, div);
237 }
238
239 /**
240 * ucb1x00_set_telecom_divisor -
241 * @ucb: UCB1x00 structure describing chip
242 * @div: SIB clock divisor
243 */
ucb1x00_set_telecom_divisor(struct ucb1x00 * ucb,unsigned int div)244 static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
245 {
246 mcp_set_telecom_divisor(ucb->mcp, div);
247 }
248
249 void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
250 void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
251 unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
252
253 #define UCB_NOSYNC (0)
254 #define UCB_SYNC (1)
255
256 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
257 void ucb1x00_adc_enable(struct ucb1x00 *ucb);
258 void ucb1x00_adc_disable(struct ucb1x00 *ucb);
259
260 #endif
261
