1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #ifndef __QLA_DEF_H 7 #define __QLA_DEF_H 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/list.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/dmapool.h> 19 #include <linux/mempool.h> 20 #include <linux/spinlock.h> 21 #include <linux/completion.h> 22 #include <linux/interrupt.h> 23 #include <linux/workqueue.h> 24 #include <linux/firmware.h> 25 #include <linux/mutex.h> 26 #include <linux/btree.h> 27 28 #include <scsi/scsi.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_device.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <scsi/scsi_transport_fc.h> 33 #include <scsi/scsi_bsg_fc.h> 34 35 #include <uapi/scsi/fc/fc_els.h> 36 37 #define QLA_DFS_DEFINE_DENTRY(_debugfs_file_name) \ 38 struct dentry *dfs_##_debugfs_file_name 39 #define QLA_DFS_ROOT_DEFINE_DENTRY(_debugfs_file_name) \ 40 struct dentry *qla_dfs_##_debugfs_file_name 41 42 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 43 typedef struct { 44 uint8_t domain; 45 uint8_t area; 46 uint8_t al_pa; 47 } be_id_t; 48 49 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 50 typedef struct { 51 uint8_t al_pa; 52 uint8_t area; 53 uint8_t domain; 54 } le_id_t; 55 56 /* 57 * 24 bit port ID type definition. 58 */ 59 typedef union { 60 uint32_t b24 : 24; 61 struct { 62 #ifdef __BIG_ENDIAN 63 uint8_t domain; 64 uint8_t area; 65 uint8_t al_pa; 66 #elif defined(__LITTLE_ENDIAN) 67 uint8_t al_pa; 68 uint8_t area; 69 uint8_t domain; 70 #else 71 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 72 #endif 73 uint8_t rsvd_1; 74 } b; 75 } port_id_t; 76 #define INVALID_PORT_ID 0xFFFFFF 77 78 #include "qla_bsg.h" 79 #include "qla_dsd.h" 80 #include "qla_nx.h" 81 #include "qla_nx2.h" 82 #include "qla_nvme.h" 83 #define QLA2XXX_DRIVER_NAME "qla2xxx" 84 #define QLA2XXX_APIDEV "ql2xapidev" 85 #define QLA2XXX_MANUFACTURER "Marvell Semiconductor, Inc." 86 87 /* 88 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 89 * but that's fine as we don't look at the last 24 ones for 90 * ISP2100 HBAs. 91 */ 92 #define MAILBOX_REGISTER_COUNT_2100 8 93 #define MAILBOX_REGISTER_COUNT_2200 24 94 #define MAILBOX_REGISTER_COUNT 32 95 96 #define QLA2200A_RISC_ROM_VER 4 97 #define FPM_2300 6 98 #define FPM_2310 7 99 100 #include "qla_settings.h" 101 102 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 103 104 /* 105 * Data bit definitions 106 */ 107 #define BIT_0 0x1 108 #define BIT_1 0x2 109 #define BIT_2 0x4 110 #define BIT_3 0x8 111 #define BIT_4 0x10 112 #define BIT_5 0x20 113 #define BIT_6 0x40 114 #define BIT_7 0x80 115 #define BIT_8 0x100 116 #define BIT_9 0x200 117 #define BIT_10 0x400 118 #define BIT_11 0x800 119 #define BIT_12 0x1000 120 #define BIT_13 0x2000 121 #define BIT_14 0x4000 122 #define BIT_15 0x8000 123 #define BIT_16 0x10000 124 #define BIT_17 0x20000 125 #define BIT_18 0x40000 126 #define BIT_19 0x80000 127 #define BIT_20 0x100000 128 #define BIT_21 0x200000 129 #define BIT_22 0x400000 130 #define BIT_23 0x800000 131 #define BIT_24 0x1000000 132 #define BIT_25 0x2000000 133 #define BIT_26 0x4000000 134 #define BIT_27 0x8000000 135 #define BIT_28 0x10000000 136 #define BIT_29 0x20000000 137 #define BIT_30 0x40000000 138 #define BIT_31 0x80000000 139 140 #define LSB(x) ((uint8_t)(x)) 141 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 142 143 #define LSW(x) ((uint16_t)(x)) 144 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 145 146 #define LSD(x) ((uint32_t)((uint64_t)(x))) 147 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 148 make_handle(uint16_t x,uint16_t y)149 static inline uint32_t make_handle(uint16_t x, uint16_t y) 150 { 151 return ((uint32_t)x << 16) | y; 152 } 153 154 /* 155 * I/O register 156 */ 157 rd_reg_byte(const volatile u8 __iomem * addr)158 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr) 159 { 160 return readb(addr); 161 } 162 rd_reg_word(const volatile __le16 __iomem * addr)163 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr) 164 { 165 return readw(addr); 166 } 167 rd_reg_dword(const volatile __le32 __iomem * addr)168 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) 169 { 170 return readl(addr); 171 } 172 rd_reg_byte_relaxed(const volatile u8 __iomem * addr)173 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr) 174 { 175 return readb_relaxed(addr); 176 } 177 rd_reg_word_relaxed(const volatile __le16 __iomem * addr)178 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr) 179 { 180 return readw_relaxed(addr); 181 } 182 rd_reg_dword_relaxed(const volatile __le32 __iomem * addr)183 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr) 184 { 185 return readl_relaxed(addr); 186 } 187 wrt_reg_byte(volatile u8 __iomem * addr,u8 data)188 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data) 189 { 190 return writeb(data, addr); 191 } 192 wrt_reg_word(volatile __le16 __iomem * addr,u16 data)193 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data) 194 { 195 return writew(data, addr); 196 } 197 wrt_reg_dword(volatile __le32 __iomem * addr,u32 data)198 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data) 199 { 200 return writel(data, addr); 201 } 202 203 /* 204 * ISP83XX specific remote register addresses 205 */ 206 #define QLA83XX_LED_PORT0 0x00201320 207 #define QLA83XX_LED_PORT1 0x00201328 208 #define QLA83XX_IDC_DEV_STATE 0x22102384 209 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 210 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 211 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 212 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 213 #define QLA83XX_IDC_CONTROL 0x22102390 214 #define QLA83XX_IDC_AUDIT 0x22102394 215 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 216 #define QLA83XX_DRIVER_LOCKID 0x22102104 217 #define QLA83XX_DRIVER_LOCK 0x8111c028 218 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 219 #define QLA83XX_FLASH_LOCKID 0x22102100 220 #define QLA83XX_FLASH_LOCK 0x8111c010 221 #define QLA83XX_FLASH_UNLOCK 0x8111c014 222 #define QLA83XX_DEV_PARTINFO1 0x221023e0 223 #define QLA83XX_DEV_PARTINFO2 0x221023e4 224 #define QLA83XX_FW_HEARTBEAT 0x221020b0 225 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 226 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 227 228 /* 83XX: Macros defining 8200 AEN Reason codes */ 229 #define IDC_DEVICE_STATE_CHANGE BIT_0 230 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 231 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 232 #define IDC_HEARTBEAT_FAILURE BIT_3 233 234 /* 83XX: Macros defining 8200 AEN Error-levels */ 235 #define ERR_LEVEL_NON_FATAL 0x1 236 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 237 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 238 239 /* 83XX: Macros for IDC Version */ 240 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 241 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 242 243 /* 83XX: Macros for scheduling dpc tasks */ 244 #define QLA83XX_NIC_CORE_RESET 0x1 245 #define QLA83XX_IDC_STATE_HANDLER 0x2 246 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 247 248 /* 83XX: Macros for defining IDC-Control bits */ 249 #define QLA83XX_IDC_RESET_DISABLED BIT_0 250 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 251 252 /* 83XX: Macros for different timeouts */ 253 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 254 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 255 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 256 257 /* 83XX: Macros for defining class in DEV-Partition Info register */ 258 #define QLA83XX_CLASS_TYPE_NONE 0x0 259 #define QLA83XX_CLASS_TYPE_NIC 0x1 260 #define QLA83XX_CLASS_TYPE_FCOE 0x2 261 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 262 263 /* 83XX: Macros for IDC Lock-Recovery stages */ 264 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 265 * lock-recovery 266 */ 267 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 268 269 /* 83XX: Macros for IDC Audit type */ 270 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 271 * dev-state change to NEED-RESET 272 * or NEED-QUIESCENT 273 */ 274 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 275 * reset-recovery completion is 276 * second 277 */ 278 /* ISP2031: Values for laser on/off */ 279 #define PORT_0_2031 0x00201340 280 #define PORT_1_2031 0x00201350 281 #define LASER_ON_2031 0x01800100 282 #define LASER_OFF_2031 0x01800180 283 284 /* 285 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 286 * 133Mhz slot. 287 */ 288 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 289 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 290 291 /* 292 * Fibre Channel device definitions. 293 */ 294 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 295 #define MAX_FIBRE_DEVICES_2100 512 296 #define MAX_FIBRE_DEVICES_2400 2048 297 #define MAX_FIBRE_DEVICES_LOOP 128 298 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 299 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 300 #define MAX_FIBRE_LUNS 0xFFFF 301 #define MAX_HOST_COUNT 16 302 303 /* 304 * Host adapter default definitions. 305 */ 306 #define MAX_BUSES 1 /* We only have one bus today */ 307 #define MIN_LUNS 8 308 #define MAX_LUNS MAX_FIBRE_LUNS 309 #define MAX_CMDS_PER_LUN 255 310 311 /* 312 * Fibre Channel device definitions. 313 */ 314 #define SNS_LAST_LOOP_ID_2100 0xfe 315 #define SNS_LAST_LOOP_ID_2300 0x7ff 316 317 #define LAST_LOCAL_LOOP_ID 0x7d 318 #define SNS_FL_PORT 0x7e 319 #define FABRIC_CONTROLLER 0x7f 320 #define SIMPLE_NAME_SERVER 0x80 321 #define SNS_FIRST_LOOP_ID 0x81 322 #define MANAGEMENT_SERVER 0xfe 323 #define BROADCAST 0xff 324 325 /* 326 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 327 * valid range of an N-PORT id is 0 through 0x7ef. 328 */ 329 #define NPH_LAST_HANDLE 0x7ee 330 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 331 #define NPH_SNS 0x7fc /* FFFFFC */ 332 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 333 #define NPH_F_PORT 0x7fe /* FFFFFE */ 334 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 335 336 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 337 338 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 339 #include "qla_fw.h" 340 341 struct name_list_extended { 342 struct get_name_list_extended *l; 343 dma_addr_t ldma; 344 struct list_head fcports; 345 u32 size; 346 u8 sent; 347 }; 348 349 struct qla_nvme_fc_rjt { 350 struct fcnvme_ls_rjt *c; 351 dma_addr_t cdma; 352 u16 size; 353 }; 354 355 struct els_reject { 356 struct fc_els_ls_rjt *c; 357 dma_addr_t cdma; 358 u16 size; 359 }; 360 361 /* 362 * Timeout timer counts in seconds 363 */ 364 #define PORT_RETRY_TIME 1 365 #define LOOP_DOWN_TIMEOUT 60 366 #define LOOP_DOWN_TIME 255 /* 240 */ 367 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 368 369 #define DEFAULT_OUTSTANDING_COMMANDS 4096 370 #define MIN_OUTSTANDING_COMMANDS 128 371 372 /* ISP request and response entry counts (37-65535) */ 373 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 374 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 375 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 376 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 377 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 378 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 379 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 380 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 381 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 382 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 383 #define FW_DEF_EXCHANGES_CNT 2048 384 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 385 #define REDUCE_EXCHANGES_CNT (8 * 1024) 386 387 #define SET_DID_STATUS(stat_var, status) (stat_var = status << 16) 388 389 struct req_que; 390 struct qla_tgt_sess; 391 392 struct qla_buf_dsc { 393 u16 tag; 394 #define TAG_FREED 0xffff 395 void *buf; 396 dma_addr_t buf_dma; 397 }; 398 399 /* 400 * SCSI Request Block 401 */ 402 struct srb_cmd { 403 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 404 uint32_t request_sense_length; 405 uint32_t fw_sense_length; 406 uint8_t *request_sense_ptr; 407 struct crc_context *crc_ctx; 408 struct ct6_dsd ct6_ctx; 409 struct qla_buf_dsc buf_dsc; 410 }; 411 412 /* 413 * SRB flag definitions 414 */ 415 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 416 #define SRB_GOT_BUF BIT_1 417 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 418 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 419 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 420 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 421 #define SRB_WAKEUP_ON_COMP BIT_6 422 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 423 #define SRB_EDIF_CLEANUP_DELETE BIT_9 424 425 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 426 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 427 #define ISP_REG16_DISCONNECT 0xFFFF 428 be_id_to_le(be_id_t id)429 static inline le_id_t be_id_to_le(be_id_t id) 430 { 431 le_id_t res; 432 433 res.domain = id.domain; 434 res.area = id.area; 435 res.al_pa = id.al_pa; 436 437 return res; 438 } 439 le_id_to_be(le_id_t id)440 static inline be_id_t le_id_to_be(le_id_t id) 441 { 442 be_id_t res; 443 444 res.domain = id.domain; 445 res.area = id.area; 446 res.al_pa = id.al_pa; 447 448 return res; 449 } 450 be_to_port_id(be_id_t id)451 static inline port_id_t be_to_port_id(be_id_t id) 452 { 453 port_id_t res; 454 455 res.b.domain = id.domain; 456 res.b.area = id.area; 457 res.b.al_pa = id.al_pa; 458 res.b.rsvd_1 = 0; 459 460 return res; 461 } 462 port_id_to_be_id(port_id_t port_id)463 static inline be_id_t port_id_to_be_id(port_id_t port_id) 464 { 465 be_id_t res; 466 467 res.domain = port_id.b.domain; 468 res.area = port_id.b.area; 469 res.al_pa = port_id.b.al_pa; 470 471 return res; 472 } 473 474 struct tmf_arg { 475 struct list_head tmf_elem; 476 struct qla_qpair *qpair; 477 struct fc_port *fcport; 478 struct scsi_qla_host *vha; 479 u64 lun; 480 u32 flags; 481 uint8_t modifier; 482 }; 483 484 struct els_logo_payload { 485 uint8_t opcode; 486 uint8_t rsvd[3]; 487 uint8_t s_id[3]; 488 uint8_t rsvd1[1]; 489 uint8_t wwpn[WWN_SIZE]; 490 }; 491 492 struct els_plogi_payload { 493 uint8_t opcode; 494 uint8_t rsvd[3]; 495 __be32 data[112 / 4]; 496 }; 497 498 struct ct_arg { 499 void *iocb; 500 u16 nport_handle; 501 dma_addr_t req_dma; 502 dma_addr_t rsp_dma; 503 u32 req_size; 504 u32 rsp_size; 505 u32 req_allocated_size; 506 u32 rsp_allocated_size; 507 void *req; 508 void *rsp; 509 port_id_t id; 510 }; 511 512 struct qla_nvme_lsrjt_pt_arg { 513 struct fc_port *fcport; 514 u8 opcode; 515 u8 vp_idx; 516 u8 reason; 517 u8 explanation; 518 __le16 nport_handle; 519 u16 control_flags; 520 __le16 ox_id; 521 __le32 xchg_address; 522 u32 tx_byte_count, rx_byte_count; 523 dma_addr_t tx_addr, rx_addr; 524 }; 525 526 /* 527 * SRB extensions. 528 */ 529 struct srb_iocb { 530 union { 531 struct { 532 uint16_t flags; 533 #define SRB_LOGIN_RETRIED BIT_0 534 #define SRB_LOGIN_COND_PLOGI BIT_1 535 #define SRB_LOGIN_SKIP_PRLI BIT_2 536 #define SRB_LOGIN_NVME_PRLI BIT_3 537 #define SRB_LOGIN_PRLI_ONLY BIT_4 538 #define SRB_LOGIN_FCSP BIT_5 539 uint16_t data[2]; 540 u32 iop[2]; 541 } logio; 542 struct { 543 #define ELS_DCMD_TIMEOUT 20 544 #define ELS_DCMD_LOGO 0x5 545 uint32_t flags; 546 uint32_t els_cmd; 547 struct completion comp; 548 struct els_logo_payload *els_logo_pyld; 549 dma_addr_t els_logo_pyld_dma; 550 } els_logo; 551 struct els_plogi { 552 #define ELS_DCMD_PLOGI 0x3 553 uint32_t flags; 554 uint32_t els_cmd; 555 struct completion comp; 556 struct els_plogi_payload *els_plogi_pyld; 557 struct els_plogi_payload *els_resp_pyld; 558 u32 tx_size; 559 u32 rx_size; 560 dma_addr_t els_plogi_pyld_dma; 561 dma_addr_t els_resp_pyld_dma; 562 __le32 fw_status[3]; 563 __le16 comp_status; 564 __le16 len; 565 } els_plogi; 566 struct { 567 /* 568 * Values for flags field below are as 569 * defined in tsk_mgmt_entry struct 570 * for control_flags field in qla_fw.h. 571 */ 572 uint64_t lun; 573 uint32_t flags; 574 uint32_t data; 575 struct completion comp; 576 __le16 comp_status; 577 578 uint8_t modifier; 579 uint8_t vp_index; 580 uint16_t loop_id; 581 } tmf; 582 struct { 583 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 584 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 585 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 586 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 587 #define FXDISC_TIMEOUT 20 588 uint8_t flags; 589 uint32_t req_len; 590 uint32_t rsp_len; 591 void *req_addr; 592 void *rsp_addr; 593 dma_addr_t req_dma_handle; 594 dma_addr_t rsp_dma_handle; 595 __le32 adapter_id; 596 __le32 adapter_id_hi; 597 __le16 req_func_type; 598 __le32 req_data; 599 __le32 req_data_extra; 600 __le32 result; 601 __le32 seq_number; 602 __le16 fw_flags; 603 struct completion fxiocb_comp; 604 __le32 reserved_0; 605 uint8_t reserved_1; 606 } fxiocb; 607 struct { 608 uint32_t cmd_hndl; 609 __le16 comp_status; 610 __le16 req_que_no; 611 struct completion comp; 612 } abt; 613 struct ct_arg ctarg; 614 #define MAX_IOCB_MB_REG 28 615 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 616 struct { 617 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 618 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 619 void *out, *in; 620 dma_addr_t out_dma, in_dma; 621 struct completion comp; 622 int rc; 623 } mbx; 624 struct { 625 struct imm_ntfy_from_isp *ntfy; 626 } nack; 627 struct { 628 __le16 comp_status; 629 __le16 rsp_pyld_len; 630 uint8_t aen_op; 631 void *desc; 632 633 /* These are only used with ls4 requests */ 634 __le32 cmd_len; 635 __le32 rsp_len; 636 dma_addr_t cmd_dma; 637 dma_addr_t rsp_dma; 638 enum nvmefc_fcp_datadir dir; 639 uint32_t dl; 640 uint32_t timeout_sec; 641 __le32 exchange_address; 642 __le16 nport_handle; 643 __le16 ox_id; 644 struct list_head entry; 645 } nvme; 646 struct { 647 u16 cmd; 648 u16 vp_index; 649 } ctrlvp; 650 struct { 651 struct edif_sa_ctl *sa_ctl; 652 struct qla_sa_update_frame sa_frame; 653 } sa_update; 654 } u; 655 656 struct timer_list timer; 657 void (*timeout)(void *); 658 }; 659 660 /* Values for srb_ctx type */ 661 #define SRB_LOGIN_CMD 1 662 #define SRB_LOGOUT_CMD 2 663 #define SRB_ELS_CMD_RPT 3 664 #define SRB_ELS_CMD_HST 4 665 #define SRB_CT_CMD 5 666 #define SRB_ADISC_CMD 6 667 #define SRB_TM_CMD 7 668 #define SRB_SCSI_CMD 8 669 #define SRB_BIDI_CMD 9 670 #define SRB_FXIOCB_DCMD 10 671 #define SRB_FXIOCB_BCMD 11 672 #define SRB_ABT_CMD 12 673 #define SRB_ELS_DCMD 13 674 #define SRB_MB_IOCB 14 675 #define SRB_CT_PTHRU_CMD 15 676 #define SRB_NACK_PLOGI 16 677 #define SRB_NACK_PRLI 17 678 #define SRB_NACK_LOGO 18 679 #define SRB_NVME_CMD 19 680 #define SRB_NVME_LS 20 681 #define SRB_PRLI_CMD 21 682 #define SRB_CTRL_VP 22 683 #define SRB_PRLO_CMD 23 684 #define SRB_SA_UPDATE 25 685 #define SRB_ELS_CMD_HST_NOLOGIN 26 686 #define SRB_SA_REPLACE 27 687 #define SRB_MARKER 28 688 689 struct qla_els_pt_arg { 690 u8 els_opcode; 691 u8 vp_idx; 692 __le16 nport_handle; 693 u16 control_flags, ox_id; 694 __le32 rx_xchg_address; 695 port_id_t did, sid; 696 u32 tx_len, tx_byte_count, rx_len, rx_byte_count; 697 dma_addr_t tx_addr, rx_addr; 698 699 }; 700 701 enum { 702 TYPE_SRB, 703 TYPE_TGT_CMD, 704 TYPE_TGT_TMCMD, /* task management */ 705 }; 706 707 struct iocb_resource { 708 u8 res_type; 709 u8 exch_cnt; 710 u16 iocb_cnt; 711 }; 712 713 struct bsg_cmd { 714 struct bsg_job *bsg_job; 715 union { 716 struct qla_els_pt_arg els_arg; 717 } u; 718 }; 719 720 typedef struct srb { 721 /* 722 * Do not move cmd_type field, it needs to 723 * line up with qla_tgt_cmd->cmd_type 724 */ 725 uint8_t cmd_type; 726 uint8_t pad[3]; 727 struct iocb_resource iores; 728 struct kref cmd_kref; /* need to migrate ref_count over to this */ 729 void *priv; 730 struct fc_port *fcport; 731 struct scsi_qla_host *vha; 732 unsigned int start_timer:1; 733 unsigned int abort:1; 734 unsigned int aborted:1; 735 unsigned int completed:1; 736 unsigned int unsol_rsp:1; 737 738 uint32_t handle; 739 uint16_t flags; 740 uint16_t type; 741 const char *name; 742 int iocbs; 743 struct qla_qpair *qpair; 744 struct srb *cmd_sp; 745 struct list_head elem; 746 u32 gen1; /* scratch */ 747 u32 gen2; /* scratch */ 748 int rc; 749 int retry_count; 750 struct completion *comp; 751 union { 752 struct srb_iocb iocb_cmd; 753 struct bsg_job *bsg_job; 754 struct srb_cmd scmd; 755 struct bsg_cmd bsg_cmd; 756 } u; 757 struct { 758 bool remapped; 759 struct { 760 dma_addr_t dma; 761 void *buf; 762 uint len; 763 } req; 764 struct { 765 dma_addr_t dma; 766 void *buf; 767 uint len; 768 } rsp; 769 } remap; 770 /* 771 * Report completion status @res and call sp_put(@sp). @res is 772 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 773 * QLA_* status value. 774 */ 775 void (*done)(struct srb *sp, int res); 776 /* Stop the timer and free @sp. Only used by the FCP code. */ 777 void (*free)(struct srb *sp); 778 /* 779 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 780 * code. 781 */ 782 void (*put_fn)(struct kref *kref); 783 784 /* 785 * Report completion for asynchronous commands. 786 */ 787 void (*async_done)(struct srb *sp, int res); 788 } srb_t; 789 790 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 791 792 #define GET_CMD_SENSE_LEN(sp) \ 793 (sp->u.scmd.request_sense_length) 794 #define SET_CMD_SENSE_LEN(sp, len) \ 795 (sp->u.scmd.request_sense_length = len) 796 #define GET_CMD_SENSE_PTR(sp) \ 797 (sp->u.scmd.request_sense_ptr) 798 #define SET_CMD_SENSE_PTR(sp, ptr) \ 799 (sp->u.scmd.request_sense_ptr = ptr) 800 #define GET_FW_SENSE_LEN(sp) \ 801 (sp->u.scmd.fw_sense_length) 802 #define SET_FW_SENSE_LEN(sp, len) \ 803 (sp->u.scmd.fw_sense_length = len) 804 805 struct msg_echo_lb { 806 dma_addr_t send_dma; 807 dma_addr_t rcv_dma; 808 uint16_t req_sg_cnt; 809 uint16_t rsp_sg_cnt; 810 uint16_t options; 811 uint32_t transfer_size; 812 uint32_t iteration_count; 813 }; 814 815 /* 816 * ISP I/O Register Set structure definitions. 817 */ 818 struct device_reg_2xxx { 819 __le16 flash_address; /* Flash BIOS address */ 820 __le16 flash_data; /* Flash BIOS data */ 821 __le16 unused_1[1]; /* Gap */ 822 __le16 ctrl_status; /* Control/Status */ 823 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 824 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 825 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 826 827 __le16 ictrl; /* Interrupt control */ 828 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 829 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 830 831 __le16 istatus; /* Interrupt status */ 832 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 833 834 __le16 semaphore; /* Semaphore */ 835 __le16 nvram; /* NVRAM register. */ 836 #define NVR_DESELECT 0 837 #define NVR_BUSY BIT_15 838 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 839 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 840 #define NVR_DATA_IN BIT_3 841 #define NVR_DATA_OUT BIT_2 842 #define NVR_SELECT BIT_1 843 #define NVR_CLOCK BIT_0 844 845 #define NVR_WAIT_CNT 20000 846 847 union { 848 struct { 849 __le16 mailbox0; 850 __le16 mailbox1; 851 __le16 mailbox2; 852 __le16 mailbox3; 853 __le16 mailbox4; 854 __le16 mailbox5; 855 __le16 mailbox6; 856 __le16 mailbox7; 857 __le16 unused_2[59]; /* Gap */ 858 } __attribute__((packed)) isp2100; 859 struct { 860 /* Request Queue */ 861 __le16 req_q_in; /* In-Pointer */ 862 __le16 req_q_out; /* Out-Pointer */ 863 /* Response Queue */ 864 __le16 rsp_q_in; /* In-Pointer */ 865 __le16 rsp_q_out; /* Out-Pointer */ 866 867 /* RISC to Host Status */ 868 __le32 host_status; 869 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 870 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 871 872 /* Host to Host Semaphore */ 873 __le16 host_semaphore; 874 __le16 unused_3[17]; /* Gap */ 875 __le16 mailbox0; 876 __le16 mailbox1; 877 __le16 mailbox2; 878 __le16 mailbox3; 879 __le16 mailbox4; 880 __le16 mailbox5; 881 __le16 mailbox6; 882 __le16 mailbox7; 883 __le16 mailbox8; 884 __le16 mailbox9; 885 __le16 mailbox10; 886 __le16 mailbox11; 887 __le16 mailbox12; 888 __le16 mailbox13; 889 __le16 mailbox14; 890 __le16 mailbox15; 891 __le16 mailbox16; 892 __le16 mailbox17; 893 __le16 mailbox18; 894 __le16 mailbox19; 895 __le16 mailbox20; 896 __le16 mailbox21; 897 __le16 mailbox22; 898 __le16 mailbox23; 899 __le16 mailbox24; 900 __le16 mailbox25; 901 __le16 mailbox26; 902 __le16 mailbox27; 903 __le16 mailbox28; 904 __le16 mailbox29; 905 __le16 mailbox30; 906 __le16 mailbox31; 907 __le16 fb_cmd; 908 __le16 unused_4[10]; /* Gap */ 909 } __attribute__((packed)) isp2300; 910 } u; 911 912 __le16 fpm_diag_config; 913 __le16 unused_5[0x4]; /* Gap */ 914 __le16 risc_hw; 915 __le16 unused_5_1; /* Gap */ 916 __le16 pcr; /* Processor Control Register. */ 917 __le16 unused_6[0x5]; /* Gap */ 918 __le16 mctr; /* Memory Configuration and Timing. */ 919 __le16 unused_7[0x3]; /* Gap */ 920 __le16 fb_cmd_2100; /* Unused on 23XX */ 921 __le16 unused_8[0x3]; /* Gap */ 922 __le16 hccr; /* Host command & control register. */ 923 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 924 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 925 /* HCCR commands */ 926 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 927 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 928 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 929 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 930 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 931 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 932 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 933 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 934 935 __le16 unused_9[5]; /* Gap */ 936 __le16 gpiod; /* GPIO Data register. */ 937 __le16 gpioe; /* GPIO Enable register. */ 938 #define GPIO_LED_MASK 0x00C0 939 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 940 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 941 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 942 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 943 #define GPIO_LED_ALL_OFF 0x0000 944 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 945 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 946 947 union { 948 struct { 949 __le16 unused_10[8]; /* Gap */ 950 __le16 mailbox8; 951 __le16 mailbox9; 952 __le16 mailbox10; 953 __le16 mailbox11; 954 __le16 mailbox12; 955 __le16 mailbox13; 956 __le16 mailbox14; 957 __le16 mailbox15; 958 __le16 mailbox16; 959 __le16 mailbox17; 960 __le16 mailbox18; 961 __le16 mailbox19; 962 __le16 mailbox20; 963 __le16 mailbox21; 964 __le16 mailbox22; 965 __le16 mailbox23; /* Also probe reg. */ 966 } __attribute__((packed)) isp2200; 967 } u_end; 968 }; 969 970 struct device_reg_25xxmq { 971 __le32 req_q_in; 972 __le32 req_q_out; 973 __le32 rsp_q_in; 974 __le32 rsp_q_out; 975 __le32 atio_q_in; 976 __le32 atio_q_out; 977 }; 978 979 980 struct device_reg_fx00 { 981 __le32 mailbox0; /* 00 */ 982 __le32 mailbox1; /* 04 */ 983 __le32 mailbox2; /* 08 */ 984 __le32 mailbox3; /* 0C */ 985 __le32 mailbox4; /* 10 */ 986 __le32 mailbox5; /* 14 */ 987 __le32 mailbox6; /* 18 */ 988 __le32 mailbox7; /* 1C */ 989 __le32 mailbox8; /* 20 */ 990 __le32 mailbox9; /* 24 */ 991 __le32 mailbox10; /* 28 */ 992 __le32 mailbox11; 993 __le32 mailbox12; 994 __le32 mailbox13; 995 __le32 mailbox14; 996 __le32 mailbox15; 997 __le32 mailbox16; 998 __le32 mailbox17; 999 __le32 mailbox18; 1000 __le32 mailbox19; 1001 __le32 mailbox20; 1002 __le32 mailbox21; 1003 __le32 mailbox22; 1004 __le32 mailbox23; 1005 __le32 mailbox24; 1006 __le32 mailbox25; 1007 __le32 mailbox26; 1008 __le32 mailbox27; 1009 __le32 mailbox28; 1010 __le32 mailbox29; 1011 __le32 mailbox30; 1012 __le32 mailbox31; 1013 __le32 aenmailbox0; 1014 __le32 aenmailbox1; 1015 __le32 aenmailbox2; 1016 __le32 aenmailbox3; 1017 __le32 aenmailbox4; 1018 __le32 aenmailbox5; 1019 __le32 aenmailbox6; 1020 __le32 aenmailbox7; 1021 /* Request Queue. */ 1022 __le32 req_q_in; /* A0 - Request Queue In-Pointer */ 1023 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ 1024 /* Response Queue. */ 1025 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ 1026 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ 1027 /* Init values shadowed on FW Up Event */ 1028 __le32 initval0; /* B0 */ 1029 __le32 initval1; /* B4 */ 1030 __le32 initval2; /* B8 */ 1031 __le32 initval3; /* BC */ 1032 __le32 initval4; /* C0 */ 1033 __le32 initval5; /* C4 */ 1034 __le32 initval6; /* C8 */ 1035 __le32 initval7; /* CC */ 1036 __le32 fwheartbeat; /* D0 */ 1037 __le32 pseudoaen; /* D4 */ 1038 }; 1039 1040 1041 1042 typedef union { 1043 struct device_reg_2xxx isp; 1044 struct device_reg_24xx isp24; 1045 struct device_reg_25xxmq isp25mq; 1046 struct device_reg_82xx isp82; 1047 struct device_reg_fx00 ispfx00; 1048 } __iomem device_reg_t; 1049 1050 #define ISP_REQ_Q_IN(ha, reg) \ 1051 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1052 &(reg)->u.isp2100.mailbox4 : \ 1053 &(reg)->u.isp2300.req_q_in) 1054 #define ISP_REQ_Q_OUT(ha, reg) \ 1055 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1056 &(reg)->u.isp2100.mailbox4 : \ 1057 &(reg)->u.isp2300.req_q_out) 1058 #define ISP_RSP_Q_IN(ha, reg) \ 1059 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1060 &(reg)->u.isp2100.mailbox5 : \ 1061 &(reg)->u.isp2300.rsp_q_in) 1062 #define ISP_RSP_Q_OUT(ha, reg) \ 1063 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1064 &(reg)->u.isp2100.mailbox5 : \ 1065 &(reg)->u.isp2300.rsp_q_out) 1066 1067 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 1068 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 1069 1070 #define MAILBOX_REG(ha, reg, num) \ 1071 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1072 (num < 8 ? \ 1073 &(reg)->u.isp2100.mailbox0 + (num) : \ 1074 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 1075 &(reg)->u.isp2300.mailbox0 + (num)) 1076 #define RD_MAILBOX_REG(ha, reg, num) \ 1077 rd_reg_word(MAILBOX_REG(ha, reg, num)) 1078 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 1079 wrt_reg_word(MAILBOX_REG(ha, reg, num), data) 1080 1081 #define FB_CMD_REG(ha, reg) \ 1082 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1083 &(reg)->fb_cmd_2100 : \ 1084 &(reg)->u.isp2300.fb_cmd) 1085 #define RD_FB_CMD_REG(ha, reg) \ 1086 rd_reg_word(FB_CMD_REG(ha, reg)) 1087 #define WRT_FB_CMD_REG(ha, reg, data) \ 1088 wrt_reg_word(FB_CMD_REG(ha, reg), data) 1089 1090 typedef struct { 1091 uint32_t out_mb; /* outbound from driver */ 1092 uint32_t in_mb; /* Incoming from RISC */ 1093 uint16_t mb[MAILBOX_REGISTER_COUNT]; 1094 long buf_size; 1095 void *bufp; 1096 uint32_t tov; 1097 uint8_t flags; 1098 #define MBX_DMA_IN BIT_0 1099 #define MBX_DMA_OUT BIT_1 1100 #define IOCTL_CMD BIT_2 1101 } mbx_cmd_t; 1102 1103 struct mbx_cmd_32 { 1104 uint32_t out_mb; /* outbound from driver */ 1105 uint32_t in_mb; /* Incoming from RISC */ 1106 uint32_t mb[MAILBOX_REGISTER_COUNT]; 1107 long buf_size; 1108 void *bufp; 1109 uint32_t tov; 1110 uint8_t flags; 1111 #define MBX_DMA_IN BIT_0 1112 #define MBX_DMA_OUT BIT_1 1113 #define IOCTL_CMD BIT_2 1114 }; 1115 1116 1117 #define MBX_TOV_SECONDS 30 1118 1119 /* 1120 * ISP product identification definitions in mailboxes after reset. 1121 */ 1122 #define PROD_ID_1 0x4953 1123 #define PROD_ID_2 0x0000 1124 #define PROD_ID_2a 0x5020 1125 #define PROD_ID_3 0x2020 1126 1127 /* 1128 * ISP mailbox Self-Test status codes 1129 */ 1130 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 1131 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 1132 #define MBS_BUSY 4 /* Busy. */ 1133 1134 /* 1135 * ISP mailbox command complete status codes 1136 */ 1137 #define MBS_COMMAND_COMPLETE 0x4000 1138 #define MBS_INVALID_COMMAND 0x4001 1139 #define MBS_HOST_INTERFACE_ERROR 0x4002 1140 #define MBS_TEST_FAILED 0x4003 1141 #define MBS_COMMAND_ERROR 0x4005 1142 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1143 #define MBS_PORT_ID_USED 0x4007 1144 #define MBS_LOOP_ID_USED 0x4008 1145 #define MBS_ALL_IDS_IN_USE 0x4009 1146 #define MBS_NOT_LOGGED_IN 0x400A 1147 #define MBS_LINK_DOWN_ERROR 0x400B 1148 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 1149 qla2xxx_is_valid_mbs(unsigned int mbs)1150 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 1151 { 1152 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 1153 } 1154 1155 /* 1156 * ISP mailbox asynchronous event status codes 1157 */ 1158 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1159 #define MBA_RESET 0x8001 /* Reset Detected. */ 1160 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1161 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1162 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1163 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1164 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1165 /* occurred. */ 1166 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1167 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1168 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1169 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1170 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1171 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1172 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1173 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1174 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */ 1175 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1176 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1177 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1178 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1179 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1180 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1181 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1182 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1183 /* used. */ 1184 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1185 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1186 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1187 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1188 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1189 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1190 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1191 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1192 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1193 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1194 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1195 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1196 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1197 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1198 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1199 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1200 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1201 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1202 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1203 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1204 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1205 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1206 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */ 1207 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1208 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1209 Notification */ 1210 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1211 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1212 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1213 /* 83XX FCoE specific */ 1214 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1215 1216 /* Interrupt type codes */ 1217 #define INTR_ROM_MB_SUCCESS 0x1 1218 #define INTR_ROM_MB_FAILED 0x2 1219 #define INTR_MB_SUCCESS 0x10 1220 #define INTR_MB_FAILED 0x11 1221 #define INTR_ASYNC_EVENT 0x12 1222 #define INTR_RSP_QUE_UPDATE 0x13 1223 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1224 #define INTR_ATIO_QUE_UPDATE 0x1C 1225 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1226 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1227 1228 /* ISP mailbox loopback echo diagnostic error code */ 1229 #define MBS_LB_RESET 0x17 1230 1231 /* AEN mailbox Port Diagnostics test */ 1232 #define AEN_START_DIAG_TEST 0x0 /* start the diagnostics */ 1233 #define AEN_DONE_DIAG_TEST_WITH_NOERR 0x1 /* Done with no errors */ 1234 #define AEN_DONE_DIAG_TEST_WITH_ERR 0x2 /* Done with error.*/ 1235 1236 /* 1237 * Firmware options 1, 2, 3. 1238 */ 1239 #define FO1_AE_ON_LIPF8 BIT_0 1240 #define FO1_AE_ALL_LIP_RESET BIT_1 1241 #define FO1_CTIO_RETRY BIT_3 1242 #define FO1_DISABLE_LIP_F7_SW BIT_4 1243 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1244 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1245 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1246 #define FO1_SET_EMPHASIS_SWING BIT_8 1247 #define FO1_AE_AUTO_BYPASS BIT_9 1248 #define FO1_ENABLE_PURE_IOCB BIT_10 1249 #define FO1_AE_PLOGI_RJT BIT_11 1250 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1251 #define FO1_AE_QUEUE_FULL BIT_13 1252 1253 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1254 #define FO2_REV_LOOPBACK BIT_1 1255 1256 #define FO3_ENABLE_EMERG_IOCB BIT_0 1257 #define FO3_AE_RND_ERROR BIT_1 1258 1259 /* 24XX additional firmware options */ 1260 #define ADD_FO_COUNT 3 1261 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1262 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1263 1264 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1265 1266 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1267 1268 /* 1269 * ISP mailbox commands 1270 */ 1271 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1272 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1273 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1274 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1275 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1276 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1277 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1278 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1279 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1280 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1281 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1282 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1283 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1284 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1285 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1286 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1287 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1288 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1289 #define MBC_RESET 0x18 /* Reset. */ 1290 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1291 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1292 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1293 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1294 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1295 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1296 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1297 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1298 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */ 1299 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1300 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1301 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1302 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1303 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1304 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1305 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1306 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1307 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1308 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1309 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1310 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1311 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1312 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1313 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1314 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1315 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1316 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1317 /* Initialization Procedure */ 1318 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1319 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1320 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1321 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1322 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1323 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1324 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1325 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1326 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1327 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1328 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1329 /* commandd. */ 1330 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1331 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1332 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1333 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1334 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1335 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1336 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1337 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1338 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1339 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1340 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1341 1342 /* 1343 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1344 * should be defined with MBC_MR_* 1345 */ 1346 #define MBC_MR_DRV_SHUTDOWN 0x6A 1347 1348 /* 1349 * ISP24xx mailbox commands 1350 */ 1351 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1352 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1353 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1354 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1355 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1356 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1357 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1358 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1359 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1360 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1361 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1362 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1363 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1364 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1365 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1366 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1367 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1368 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1369 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1370 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1371 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1372 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1373 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1374 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1375 1376 /* 1377 * ISP81xx mailbox commands 1378 */ 1379 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1380 1381 /* 1382 * ISP8044 mailbox commands 1383 */ 1384 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1385 #define HCS_WRITE_SERDES 0x3 1386 #define HCS_READ_SERDES 0x4 1387 1388 /* Firmware return data sizes */ 1389 #define FCAL_MAP_SIZE 128 1390 1391 /* Mailbox bit definitions for out_mb and in_mb */ 1392 #define MBX_31 BIT_31 1393 #define MBX_30 BIT_30 1394 #define MBX_29 BIT_29 1395 #define MBX_28 BIT_28 1396 #define MBX_27 BIT_27 1397 #define MBX_26 BIT_26 1398 #define MBX_25 BIT_25 1399 #define MBX_24 BIT_24 1400 #define MBX_23 BIT_23 1401 #define MBX_22 BIT_22 1402 #define MBX_21 BIT_21 1403 #define MBX_20 BIT_20 1404 #define MBX_19 BIT_19 1405 #define MBX_18 BIT_18 1406 #define MBX_17 BIT_17 1407 #define MBX_16 BIT_16 1408 #define MBX_15 BIT_15 1409 #define MBX_14 BIT_14 1410 #define MBX_13 BIT_13 1411 #define MBX_12 BIT_12 1412 #define MBX_11 BIT_11 1413 #define MBX_10 BIT_10 1414 #define MBX_9 BIT_9 1415 #define MBX_8 BIT_8 1416 #define MBX_7 BIT_7 1417 #define MBX_6 BIT_6 1418 #define MBX_5 BIT_5 1419 #define MBX_4 BIT_4 1420 #define MBX_3 BIT_3 1421 #define MBX_2 BIT_2 1422 #define MBX_1 BIT_1 1423 #define MBX_0 BIT_0 1424 1425 #define RNID_TYPE_ELS_CMD 0x5 1426 #define RNID_TYPE_PORT_LOGIN 0x7 1427 #define RNID_BUFFER_CREDITS 0x8 1428 #define RNID_TYPE_SET_VERSION 0x9 1429 #define RNID_TYPE_ASIC_TEMP 0xC 1430 1431 #define ELS_CMD_MAP_SIZE 32 1432 1433 /* 1434 * Firmware state codes from get firmware state mailbox command 1435 */ 1436 #define FSTATE_CONFIG_WAIT 0 1437 #define FSTATE_WAIT_AL_PA 1 1438 #define FSTATE_WAIT_LOGIN 2 1439 #define FSTATE_READY 3 1440 #define FSTATE_LOSS_OF_SYNC 4 1441 #define FSTATE_ERROR 5 1442 #define FSTATE_REINIT 6 1443 #define FSTATE_NON_PART 7 1444 1445 #define FSTATE_CONFIG_CORRECT 0 1446 #define FSTATE_P2P_RCV_LIP 1 1447 #define FSTATE_P2P_CHOOSE_LOOP 2 1448 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1449 #define FSTATE_FATAL_ERROR 4 1450 #define FSTATE_LOOP_BACK_CONN 5 1451 1452 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1453 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1454 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1455 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1456 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1457 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1458 #define QLA27XX_DEFAULT_IMAGE 0 1459 #define QLA27XX_PRIMARY_IMAGE 1 1460 #define QLA27XX_SECONDARY_IMAGE 2 1461 1462 /* 1463 * Port Database structure definition 1464 * Little endian except where noted. 1465 */ 1466 #define PORT_DATABASE_SIZE 128 /* bytes */ 1467 typedef struct { 1468 uint8_t options; 1469 uint8_t control; 1470 uint8_t master_state; 1471 uint8_t slave_state; 1472 uint8_t reserved[2]; 1473 uint8_t hard_address; 1474 uint8_t reserved_1; 1475 uint8_t port_id[4]; 1476 uint8_t node_name[WWN_SIZE]; 1477 uint8_t port_name[WWN_SIZE]; 1478 __le16 execution_throttle; 1479 uint16_t execution_count; 1480 uint8_t reset_count; 1481 uint8_t reserved_2; 1482 uint16_t resource_allocation; 1483 uint16_t current_allocation; 1484 uint16_t queue_head; 1485 uint16_t queue_tail; 1486 uint16_t transmit_execution_list_next; 1487 uint16_t transmit_execution_list_previous; 1488 uint16_t common_features; 1489 uint16_t total_concurrent_sequences; 1490 uint16_t RO_by_information_category; 1491 uint8_t recipient; 1492 uint8_t initiator; 1493 uint16_t receive_data_size; 1494 uint16_t concurrent_sequences; 1495 uint16_t open_sequences_per_exchange; 1496 uint16_t lun_abort_flags; 1497 uint16_t lun_stop_flags; 1498 uint16_t stop_queue_head; 1499 uint16_t stop_queue_tail; 1500 uint16_t port_retry_timer; 1501 uint16_t next_sequence_id; 1502 uint16_t frame_count; 1503 uint16_t PRLI_payload_length; 1504 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1505 /* Bits 15-0 of word 0 */ 1506 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1507 /* Bits 15-0 of word 3 */ 1508 uint16_t loop_id; 1509 uint16_t extended_lun_info_list_pointer; 1510 uint16_t extended_lun_stop_list_pointer; 1511 } port_database_t; 1512 1513 /* 1514 * Port database slave/master states 1515 */ 1516 #define PD_STATE_DISCOVERY 0 1517 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1518 #define PD_STATE_PORT_LOGIN 2 1519 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1520 #define PD_STATE_PROCESS_LOGIN 4 1521 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1522 #define PD_STATE_PORT_LOGGED_IN 6 1523 #define PD_STATE_PORT_UNAVAILABLE 7 1524 #define PD_STATE_PROCESS_LOGOUT 8 1525 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1526 #define PD_STATE_PORT_LOGOUT 10 1527 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1528 1529 1530 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1531 #define QLA_ZIO_DISABLED 0 1532 #define QLA_ZIO_DEFAULT_TIMER 2 1533 1534 /* 1535 * ISP Initialization Control Block. 1536 * Little endian except where noted. 1537 */ 1538 #define ICB_VERSION 1 1539 typedef struct { 1540 uint8_t version; 1541 uint8_t reserved_1; 1542 1543 /* 1544 * LSB BIT 0 = Enable Hard Loop Id 1545 * LSB BIT 1 = Enable Fairness 1546 * LSB BIT 2 = Enable Full-Duplex 1547 * LSB BIT 3 = Enable Fast Posting 1548 * LSB BIT 4 = Enable Target Mode 1549 * LSB BIT 5 = Disable Initiator Mode 1550 * LSB BIT 6 = Enable ADISC 1551 * LSB BIT 7 = Enable Target Inquiry Data 1552 * 1553 * MSB BIT 0 = Enable PDBC Notify 1554 * MSB BIT 1 = Non Participating LIP 1555 * MSB BIT 2 = Descending Loop ID Search 1556 * MSB BIT 3 = Acquire Loop ID in LIPA 1557 * MSB BIT 4 = Stop PortQ on Full Status 1558 * MSB BIT 5 = Full Login after LIP 1559 * MSB BIT 6 = Node Name Option 1560 * MSB BIT 7 = Ext IFWCB enable bit 1561 */ 1562 uint8_t firmware_options[2]; 1563 1564 __le16 frame_payload_size; 1565 __le16 max_iocb_allocation; 1566 __le16 execution_throttle; 1567 uint8_t retry_count; 1568 uint8_t retry_delay; /* unused */ 1569 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1570 uint16_t hard_address; 1571 uint8_t inquiry_data; 1572 uint8_t login_timeout; 1573 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1574 1575 __le16 request_q_outpointer; 1576 __le16 response_q_inpointer; 1577 __le16 request_q_length; 1578 __le16 response_q_length; 1579 __le64 request_q_address __packed; 1580 __le64 response_q_address __packed; 1581 1582 __le16 lun_enables; 1583 uint8_t command_resource_count; 1584 uint8_t immediate_notify_resource_count; 1585 __le16 timeout; 1586 uint8_t reserved_2[2]; 1587 1588 /* 1589 * LSB BIT 0 = Timer Operation mode bit 0 1590 * LSB BIT 1 = Timer Operation mode bit 1 1591 * LSB BIT 2 = Timer Operation mode bit 2 1592 * LSB BIT 3 = Timer Operation mode bit 3 1593 * LSB BIT 4 = Init Config Mode bit 0 1594 * LSB BIT 5 = Init Config Mode bit 1 1595 * LSB BIT 6 = Init Config Mode bit 2 1596 * LSB BIT 7 = Enable Non part on LIHA failure 1597 * 1598 * MSB BIT 0 = Enable class 2 1599 * MSB BIT 1 = Enable ACK0 1600 * MSB BIT 2 = 1601 * MSB BIT 3 = 1602 * MSB BIT 4 = FC Tape Enable 1603 * MSB BIT 5 = Enable FC Confirm 1604 * MSB BIT 6 = Enable command queuing in target mode 1605 * MSB BIT 7 = No Logo On Link Down 1606 */ 1607 uint8_t add_firmware_options[2]; 1608 1609 uint8_t response_accumulation_timer; 1610 uint8_t interrupt_delay_timer; 1611 1612 /* 1613 * LSB BIT 0 = Enable Read xfr_rdy 1614 * LSB BIT 1 = Soft ID only 1615 * LSB BIT 2 = 1616 * LSB BIT 3 = 1617 * LSB BIT 4 = FCP RSP Payload [0] 1618 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1619 * LSB BIT 6 = Enable Out-of-Order frame handling 1620 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1621 * 1622 * MSB BIT 0 = Sbus enable - 2300 1623 * MSB BIT 1 = 1624 * MSB BIT 2 = 1625 * MSB BIT 3 = 1626 * MSB BIT 4 = LED mode 1627 * MSB BIT 5 = enable 50 ohm termination 1628 * MSB BIT 6 = Data Rate (2300 only) 1629 * MSB BIT 7 = Data Rate (2300 only) 1630 */ 1631 uint8_t special_options[2]; 1632 1633 uint8_t reserved_3[26]; 1634 } init_cb_t; 1635 1636 /* Special Features Control Block */ 1637 struct init_sf_cb { 1638 uint8_t format; 1639 uint8_t reserved0; 1640 /* 1641 * BIT 15-14 = Reserved 1642 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled) 1643 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled) 1644 * BIT 11-0 = Reserved 1645 */ 1646 __le16 flags; 1647 uint8_t reserved1[32]; 1648 uint16_t discard_OHRB_timeout_value; 1649 uint16_t remote_write_opt_queue_num; 1650 uint8_t reserved2[40]; 1651 uint8_t scm_related_parameter[16]; 1652 uint8_t reserved3[32]; 1653 }; 1654 1655 /* 1656 * Get Link Status mailbox command return buffer. 1657 */ 1658 #define GLSO_SEND_RPS BIT_0 1659 #define GLSO_USE_DID BIT_3 1660 1661 struct link_statistics { 1662 __le32 link_fail_cnt; 1663 __le32 loss_sync_cnt; 1664 __le32 loss_sig_cnt; 1665 __le32 prim_seq_err_cnt; 1666 __le32 inval_xmit_word_cnt; 1667 __le32 inval_crc_cnt; 1668 __le32 lip_cnt; 1669 __le32 link_up_cnt; 1670 __le32 link_down_loop_init_tmo; 1671 __le32 link_down_los; 1672 __le32 link_down_loss_rcv_clk; 1673 uint32_t reserved0[5]; 1674 __le32 port_cfg_chg; 1675 uint32_t reserved1[11]; 1676 __le32 rsp_q_full; 1677 __le32 atio_q_full; 1678 __le32 drop_ae; 1679 __le32 els_proto_err; 1680 __le32 reserved2; 1681 __le32 tx_frames; 1682 __le32 rx_frames; 1683 __le32 discarded_frames; 1684 __le32 dropped_frames; 1685 uint32_t reserved3; 1686 __le32 nos_rcvd; 1687 uint32_t reserved4[4]; 1688 __le32 tx_prjt; 1689 __le32 rcv_exfail; 1690 __le32 rcv_abts; 1691 __le32 seq_frm_miss; 1692 __le32 corr_err; 1693 __le32 mb_rqst; 1694 __le32 nport_full; 1695 __le32 eofa; 1696 uint32_t reserved5; 1697 __le64 fpm_recv_word_cnt; 1698 __le64 fpm_disc_word_cnt; 1699 __le64 fpm_xmit_word_cnt; 1700 uint32_t reserved6[70]; 1701 }; 1702 1703 /* 1704 * NVRAM Command values. 1705 */ 1706 #define NV_START_BIT BIT_2 1707 #define NV_WRITE_OP (BIT_26+BIT_24) 1708 #define NV_READ_OP (BIT_26+BIT_25) 1709 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1710 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1711 #define NV_DELAY_COUNT 10 1712 1713 /* 1714 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1715 */ 1716 typedef struct { 1717 /* 1718 * NVRAM header 1719 */ 1720 uint8_t id[4]; 1721 uint8_t nvram_version; 1722 uint8_t reserved_0; 1723 1724 /* 1725 * NVRAM RISC parameter block 1726 */ 1727 uint8_t parameter_block_version; 1728 uint8_t reserved_1; 1729 1730 /* 1731 * LSB BIT 0 = Enable Hard Loop Id 1732 * LSB BIT 1 = Enable Fairness 1733 * LSB BIT 2 = Enable Full-Duplex 1734 * LSB BIT 3 = Enable Fast Posting 1735 * LSB BIT 4 = Enable Target Mode 1736 * LSB BIT 5 = Disable Initiator Mode 1737 * LSB BIT 6 = Enable ADISC 1738 * LSB BIT 7 = Enable Target Inquiry Data 1739 * 1740 * MSB BIT 0 = Enable PDBC Notify 1741 * MSB BIT 1 = Non Participating LIP 1742 * MSB BIT 2 = Descending Loop ID Search 1743 * MSB BIT 3 = Acquire Loop ID in LIPA 1744 * MSB BIT 4 = Stop PortQ on Full Status 1745 * MSB BIT 5 = Full Login after LIP 1746 * MSB BIT 6 = Node Name Option 1747 * MSB BIT 7 = Ext IFWCB enable bit 1748 */ 1749 uint8_t firmware_options[2]; 1750 1751 __le16 frame_payload_size; 1752 __le16 max_iocb_allocation; 1753 __le16 execution_throttle; 1754 uint8_t retry_count; 1755 uint8_t retry_delay; /* unused */ 1756 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1757 uint16_t hard_address; 1758 uint8_t inquiry_data; 1759 uint8_t login_timeout; 1760 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1761 1762 /* 1763 * LSB BIT 0 = Timer Operation mode bit 0 1764 * LSB BIT 1 = Timer Operation mode bit 1 1765 * LSB BIT 2 = Timer Operation mode bit 2 1766 * LSB BIT 3 = Timer Operation mode bit 3 1767 * LSB BIT 4 = Init Config Mode bit 0 1768 * LSB BIT 5 = Init Config Mode bit 1 1769 * LSB BIT 6 = Init Config Mode bit 2 1770 * LSB BIT 7 = Enable Non part on LIHA failure 1771 * 1772 * MSB BIT 0 = Enable class 2 1773 * MSB BIT 1 = Enable ACK0 1774 * MSB BIT 2 = 1775 * MSB BIT 3 = 1776 * MSB BIT 4 = FC Tape Enable 1777 * MSB BIT 5 = Enable FC Confirm 1778 * MSB BIT 6 = Enable command queuing in target mode 1779 * MSB BIT 7 = No Logo On Link Down 1780 */ 1781 uint8_t add_firmware_options[2]; 1782 1783 uint8_t response_accumulation_timer; 1784 uint8_t interrupt_delay_timer; 1785 1786 /* 1787 * LSB BIT 0 = Enable Read xfr_rdy 1788 * LSB BIT 1 = Soft ID only 1789 * LSB BIT 2 = 1790 * LSB BIT 3 = 1791 * LSB BIT 4 = FCP RSP Payload [0] 1792 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1793 * LSB BIT 6 = Enable Out-of-Order frame handling 1794 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1795 * 1796 * MSB BIT 0 = Sbus enable - 2300 1797 * MSB BIT 1 = 1798 * MSB BIT 2 = 1799 * MSB BIT 3 = 1800 * MSB BIT 4 = LED mode 1801 * MSB BIT 5 = enable 50 ohm termination 1802 * MSB BIT 6 = Data Rate (2300 only) 1803 * MSB BIT 7 = Data Rate (2300 only) 1804 */ 1805 uint8_t special_options[2]; 1806 1807 /* Reserved for expanded RISC parameter block */ 1808 uint8_t reserved_2[22]; 1809 1810 /* 1811 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1812 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1813 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1814 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1815 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1816 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1817 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1818 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1819 * 1820 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1821 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1822 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1823 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1824 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1825 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1826 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1827 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1828 * 1829 * LSB BIT 0 = Output Swing 1G bit 0 1830 * LSB BIT 1 = Output Swing 1G bit 1 1831 * LSB BIT 2 = Output Swing 1G bit 2 1832 * LSB BIT 3 = Output Emphasis 1G bit 0 1833 * LSB BIT 4 = Output Emphasis 1G bit 1 1834 * LSB BIT 5 = Output Swing 2G bit 0 1835 * LSB BIT 6 = Output Swing 2G bit 1 1836 * LSB BIT 7 = Output Swing 2G bit 2 1837 * 1838 * MSB BIT 0 = Output Emphasis 2G bit 0 1839 * MSB BIT 1 = Output Emphasis 2G bit 1 1840 * MSB BIT 2 = Output Enable 1841 * MSB BIT 3 = 1842 * MSB BIT 4 = 1843 * MSB BIT 5 = 1844 * MSB BIT 6 = 1845 * MSB BIT 7 = 1846 */ 1847 uint8_t seriallink_options[4]; 1848 1849 /* 1850 * NVRAM host parameter block 1851 * 1852 * LSB BIT 0 = Enable spinup delay 1853 * LSB BIT 1 = Disable BIOS 1854 * LSB BIT 2 = Enable Memory Map BIOS 1855 * LSB BIT 3 = Enable Selectable Boot 1856 * LSB BIT 4 = Disable RISC code load 1857 * LSB BIT 5 = Set cache line size 1 1858 * LSB BIT 6 = PCI Parity Disable 1859 * LSB BIT 7 = Enable extended logging 1860 * 1861 * MSB BIT 0 = Enable 64bit addressing 1862 * MSB BIT 1 = Enable lip reset 1863 * MSB BIT 2 = Enable lip full login 1864 * MSB BIT 3 = Enable target reset 1865 * MSB BIT 4 = Enable database storage 1866 * MSB BIT 5 = Enable cache flush read 1867 * MSB BIT 6 = Enable database load 1868 * MSB BIT 7 = Enable alternate WWN 1869 */ 1870 uint8_t host_p[2]; 1871 1872 uint8_t boot_node_name[WWN_SIZE]; 1873 uint8_t boot_lun_number; 1874 uint8_t reset_delay; 1875 uint8_t port_down_retry_count; 1876 uint8_t boot_id_number; 1877 __le16 max_luns_per_target; 1878 uint8_t fcode_boot_port_name[WWN_SIZE]; 1879 uint8_t alternate_port_name[WWN_SIZE]; 1880 uint8_t alternate_node_name[WWN_SIZE]; 1881 1882 /* 1883 * BIT 0 = Selective Login 1884 * BIT 1 = Alt-Boot Enable 1885 * BIT 2 = 1886 * BIT 3 = Boot Order List 1887 * BIT 4 = 1888 * BIT 5 = Selective LUN 1889 * BIT 6 = 1890 * BIT 7 = unused 1891 */ 1892 uint8_t efi_parameters; 1893 1894 uint8_t link_down_timeout; 1895 1896 uint8_t adapter_id[16]; 1897 1898 uint8_t alt1_boot_node_name[WWN_SIZE]; 1899 uint16_t alt1_boot_lun_number; 1900 uint8_t alt2_boot_node_name[WWN_SIZE]; 1901 uint16_t alt2_boot_lun_number; 1902 uint8_t alt3_boot_node_name[WWN_SIZE]; 1903 uint16_t alt3_boot_lun_number; 1904 uint8_t alt4_boot_node_name[WWN_SIZE]; 1905 uint16_t alt4_boot_lun_number; 1906 uint8_t alt5_boot_node_name[WWN_SIZE]; 1907 uint16_t alt5_boot_lun_number; 1908 uint8_t alt6_boot_node_name[WWN_SIZE]; 1909 uint16_t alt6_boot_lun_number; 1910 uint8_t alt7_boot_node_name[WWN_SIZE]; 1911 uint16_t alt7_boot_lun_number; 1912 1913 uint8_t reserved_3[2]; 1914 1915 /* Offset 200-215 : Model Number */ 1916 uint8_t model_number[16]; 1917 1918 /* OEM related items */ 1919 uint8_t oem_specific[16]; 1920 1921 /* 1922 * NVRAM Adapter Features offset 232-239 1923 * 1924 * LSB BIT 0 = External GBIC 1925 * LSB BIT 1 = Risc RAM parity 1926 * LSB BIT 2 = Buffer Plus Module 1927 * LSB BIT 3 = Multi Chip Adapter 1928 * LSB BIT 4 = Internal connector 1929 * LSB BIT 5 = 1930 * LSB BIT 6 = 1931 * LSB BIT 7 = 1932 * 1933 * MSB BIT 0 = 1934 * MSB BIT 1 = 1935 * MSB BIT 2 = 1936 * MSB BIT 3 = 1937 * MSB BIT 4 = 1938 * MSB BIT 5 = 1939 * MSB BIT 6 = 1940 * MSB BIT 7 = 1941 */ 1942 uint8_t adapter_features[2]; 1943 1944 uint8_t reserved_4[16]; 1945 1946 /* Subsystem vendor ID for ISP2200 */ 1947 uint16_t subsystem_vendor_id_2200; 1948 1949 /* Subsystem device ID for ISP2200 */ 1950 uint16_t subsystem_device_id_2200; 1951 1952 uint8_t reserved_5; 1953 uint8_t checksum; 1954 } nvram_t; 1955 1956 /* 1957 * ISP queue - response queue entry definition. 1958 */ 1959 typedef struct { 1960 uint8_t entry_type; /* Entry type. */ 1961 uint8_t entry_count; /* Entry count. */ 1962 uint8_t sys_define; /* System defined. */ 1963 uint8_t entry_status; /* Entry Status. */ 1964 uint32_t handle; /* System defined handle */ 1965 uint8_t data[52]; 1966 uint32_t signature; 1967 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1968 } response_t; 1969 1970 /* 1971 * ISP queue - ATIO queue entry definition. 1972 */ 1973 struct atio { 1974 uint8_t entry_type; /* Entry type. */ 1975 uint8_t entry_count; /* Entry count. */ 1976 __le16 attr_n_length; 1977 uint8_t data[56]; 1978 uint32_t signature; 1979 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1980 }; 1981 1982 typedef union { 1983 __le16 extended; 1984 struct { 1985 uint8_t reserved; 1986 uint8_t standard; 1987 } id; 1988 } target_id_t; 1989 1990 #define SET_TARGET_ID(ha, to, from) \ 1991 do { \ 1992 if (HAS_EXTENDED_IDS(ha)) \ 1993 to.extended = cpu_to_le16(from); \ 1994 else \ 1995 to.id.standard = (uint8_t)from; \ 1996 } while (0) 1997 1998 /* 1999 * ISP queue - command entry structure definition. 2000 */ 2001 #define COMMAND_TYPE 0x11 /* Command entry */ 2002 typedef struct { 2003 uint8_t entry_type; /* Entry type. */ 2004 uint8_t entry_count; /* Entry count. */ 2005 uint8_t sys_define; /* System defined. */ 2006 uint8_t entry_status; /* Entry Status. */ 2007 uint32_t handle; /* System handle. */ 2008 target_id_t target; /* SCSI ID */ 2009 __le16 lun; /* SCSI LUN */ 2010 __le16 control_flags; /* Control flags. */ 2011 #define CF_WRITE BIT_6 2012 #define CF_READ BIT_5 2013 #define CF_SIMPLE_TAG BIT_3 2014 #define CF_ORDERED_TAG BIT_2 2015 #define CF_HEAD_TAG BIT_1 2016 uint16_t reserved_1; 2017 __le16 timeout; /* Command timeout. */ 2018 __le16 dseg_count; /* Data segment count. */ 2019 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 2020 __le32 byte_count; /* Total byte count. */ 2021 union { 2022 struct dsd32 dsd32[3]; 2023 struct dsd64 dsd64[2]; 2024 }; 2025 } cmd_entry_t; 2026 2027 /* 2028 * ISP queue - 64-Bit addressing, command entry structure definition. 2029 */ 2030 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 2031 typedef struct { 2032 uint8_t entry_type; /* Entry type. */ 2033 uint8_t entry_count; /* Entry count. */ 2034 uint8_t sys_define; /* System defined. */ 2035 uint8_t entry_status; /* Entry Status. */ 2036 uint32_t handle; /* System handle. */ 2037 target_id_t target; /* SCSI ID */ 2038 __le16 lun; /* SCSI LUN */ 2039 __le16 control_flags; /* Control flags. */ 2040 uint16_t reserved_1; 2041 __le16 timeout; /* Command timeout. */ 2042 __le16 dseg_count; /* Data segment count. */ 2043 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 2044 uint32_t byte_count; /* Total byte count. */ 2045 struct dsd64 dsd[2]; 2046 } cmd_a64_entry_t, request_t; 2047 2048 /* 2049 * ISP queue - continuation entry structure definition. 2050 */ 2051 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 2052 typedef struct { 2053 uint8_t entry_type; /* Entry type. */ 2054 uint8_t entry_count; /* Entry count. */ 2055 uint8_t sys_define; /* System defined. */ 2056 uint8_t entry_status; /* Entry Status. */ 2057 uint32_t reserved; 2058 struct dsd32 dsd[7]; 2059 } cont_entry_t; 2060 2061 /* 2062 * ISP queue - 64-Bit addressing, continuation entry structure definition. 2063 */ 2064 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 2065 typedef struct { 2066 uint8_t entry_type; /* Entry type. */ 2067 uint8_t entry_count; /* Entry count. */ 2068 uint8_t sys_define; /* System defined. */ 2069 uint8_t entry_status; /* Entry Status. */ 2070 struct dsd64 dsd[5]; 2071 } cont_a64_entry_t; 2072 2073 #define PO_MODE_DIF_INSERT 0 2074 #define PO_MODE_DIF_REMOVE 1 2075 #define PO_MODE_DIF_PASS 2 2076 #define PO_MODE_DIF_REPLACE 3 2077 #define PO_MODE_DIF_TCP_CKSUM 6 2078 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 2079 #define PO_DISABLE_GUARD_CHECK BIT_4 2080 #define PO_DISABLE_INCR_REF_TAG BIT_5 2081 #define PO_DIS_HEADER_MODE BIT_7 2082 #define PO_ENABLE_DIF_BUNDLING BIT_8 2083 #define PO_DIS_FRAME_MODE BIT_9 2084 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 2085 #define PO_DIS_VALD_APP_REF_ESC BIT_11 2086 2087 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 2088 #define PO_DIS_REF_TAG_REPL BIT_13 2089 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 2090 #define PO_DIS_REF_TAG_VALD BIT_15 2091 2092 /* 2093 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 2094 */ 2095 struct crc_context { 2096 uint32_t handle; /* System handle. */ 2097 __le32 ref_tag; 2098 __le16 app_tag; 2099 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 2100 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 2101 __le16 guard_seed; /* Initial Guard Seed */ 2102 __le16 prot_opts; /* Requested Data Protection Mode */ 2103 __le16 blk_size; /* Data size in bytes */ 2104 __le16 runt_blk_guard; /* Guard value for runt block (tape 2105 * only) */ 2106 __le32 byte_count; /* Total byte count/ total data 2107 * transfer count */ 2108 union { 2109 struct { 2110 uint32_t reserved_1; 2111 uint16_t reserved_2; 2112 uint16_t reserved_3; 2113 uint32_t reserved_4; 2114 struct dsd64 data_dsd[1]; 2115 uint32_t reserved_5[2]; 2116 uint32_t reserved_6; 2117 } nobundling; 2118 struct { 2119 __le32 dif_byte_count; /* Total DIF byte 2120 * count */ 2121 uint16_t reserved_1; 2122 __le16 dseg_count; /* Data segment count */ 2123 uint32_t reserved_2; 2124 struct dsd64 data_dsd[1]; 2125 struct dsd64 dif_dsd; 2126 } bundling; 2127 } u; 2128 2129 struct fcp_cmnd fcp_cmnd; 2130 dma_addr_t crc_ctx_dma; 2131 /* List of DMA context transfers */ 2132 struct list_head dsd_list; 2133 2134 /* List of DIF Bundling context DMA address */ 2135 struct list_head ldif_dsd_list; 2136 u8 no_ldif_dsd; 2137 2138 struct list_head ldif_dma_hndl_list; 2139 u32 dif_bundl_len; 2140 u8 no_dif_bundl; 2141 /* This structure should not exceed 512 bytes */ 2142 }; 2143 2144 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 2145 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 2146 2147 /* 2148 * ISP queue - status entry structure definition. 2149 */ 2150 #define STATUS_TYPE 0x03 /* Status entry. */ 2151 typedef struct { 2152 uint8_t entry_type; /* Entry type. */ 2153 uint8_t entry_count; /* Entry count. */ 2154 uint8_t sys_define; /* System defined. */ 2155 uint8_t entry_status; /* Entry Status. */ 2156 uint32_t handle; /* System handle. */ 2157 __le16 scsi_status; /* SCSI status. */ 2158 __le16 comp_status; /* Completion status. */ 2159 __le16 state_flags; /* State flags. */ 2160 __le16 status_flags; /* Status flags. */ 2161 __le16 rsp_info_len; /* Response Info Length. */ 2162 __le16 req_sense_length; /* Request sense data length. */ 2163 __le32 residual_length; /* Residual transfer length. */ 2164 uint8_t rsp_info[8]; /* FCP response information. */ 2165 uint8_t req_sense_data[32]; /* Request sense data. */ 2166 } sts_entry_t; 2167 2168 /* 2169 * Status entry entry status 2170 */ 2171 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 2172 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 2173 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 2174 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 2175 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 2176 #define RF_BUSY BIT_1 /* Busy */ 2177 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 2178 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 2179 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 2180 RF_INV_E_TYPE) 2181 2182 /* 2183 * Status entry SCSI status bit definitions. 2184 */ 2185 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2186 #define SS_RESIDUAL_UNDER BIT_11 2187 #define SS_RESIDUAL_OVER BIT_10 2188 #define SS_SENSE_LEN_VALID BIT_9 2189 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2190 #define SS_SCSI_STATUS_BYTE 0xff 2191 2192 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2193 #define SS_BUSY_CONDITION BIT_3 2194 #define SS_CONDITION_MET BIT_2 2195 #define SS_CHECK_CONDITION BIT_1 2196 2197 /* 2198 * Status entry completion status 2199 */ 2200 #define CS_COMPLETE 0x0 /* No errors */ 2201 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2202 #define CS_DMA 0x2 /* A DMA direction error. */ 2203 #define CS_TRANSPORT 0x3 /* Transport error. */ 2204 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2205 #define CS_ABORTED 0x5 /* System aborted command. */ 2206 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2207 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2208 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2209 2210 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2211 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2212 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2213 /* (selection timeout) */ 2214 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2215 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2216 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2217 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2218 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2219 failure */ 2220 #define CS_REJECT_RECEIVED 0x4E /* Reject received */ 2221 #define CS_EDIF_AUTH_ERROR 0x63 /* decrypt error */ 2222 #define CS_EDIF_PAD_LEN_ERROR 0x65 /* pad > frame size, not 4byte align */ 2223 #define CS_EDIF_INV_REQ 0x66 /* invalid request */ 2224 #define CS_EDIF_SPI_ERROR 0x67 /* rx frame unable to locate sa */ 2225 #define CS_EDIF_HDR_ERROR 0x69 /* data frame != expected len */ 2226 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2227 #define CS_UNKNOWN 0x81 /* Driver defined */ 2228 #define CS_RETRY 0x82 /* Driver defined */ 2229 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2230 2231 #define CS_BIDIR_RD_OVERRUN 0x700 2232 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2233 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2234 #define CS_BIDIR_RD_UNDERRUN 0x1500 2235 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2236 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2237 #define CS_BIDIR_DMA 0x200 2238 /* 2239 * Status entry status flags 2240 */ 2241 #define SF_ABTS_TERMINATED BIT_10 2242 #define SF_LOGOUT_SENT BIT_13 2243 2244 /* 2245 * ISP queue - status continuation entry structure definition. 2246 */ 2247 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2248 typedef struct { 2249 uint8_t entry_type; /* Entry type. */ 2250 uint8_t entry_count; /* Entry count. */ 2251 uint8_t sys_define; /* System defined. */ 2252 uint8_t entry_status; /* Entry Status. */ 2253 uint8_t data[60]; /* data */ 2254 } sts_cont_entry_t; 2255 2256 /* 2257 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2258 * structure definition. 2259 */ 2260 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2261 typedef struct { 2262 uint8_t entry_type; /* Entry type. */ 2263 uint8_t entry_count; /* Entry count. */ 2264 uint8_t handle_count; /* Handle count. */ 2265 uint8_t entry_status; /* Entry Status. */ 2266 uint32_t handle[15]; /* System handles. */ 2267 } sts21_entry_t; 2268 2269 /* 2270 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2271 * structure definition. 2272 */ 2273 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2274 typedef struct { 2275 uint8_t entry_type; /* Entry type. */ 2276 uint8_t entry_count; /* Entry count. */ 2277 uint8_t handle_count; /* Handle count. */ 2278 uint8_t entry_status; /* Entry Status. */ 2279 uint16_t handle[30]; /* System handles. */ 2280 } sts22_entry_t; 2281 2282 /* 2283 * ISP queue - marker entry structure definition. 2284 */ 2285 #define MARKER_TYPE 0x04 /* Marker entry. */ 2286 typedef struct { 2287 uint8_t entry_type; /* Entry type. */ 2288 uint8_t entry_count; /* Entry count. */ 2289 uint8_t handle_count; /* Handle count. */ 2290 uint8_t entry_status; /* Entry Status. */ 2291 uint32_t sys_define_2; /* System defined. */ 2292 target_id_t target; /* SCSI ID */ 2293 uint8_t modifier; /* Modifier (7-0). */ 2294 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2295 #define MK_SYNC_ID 1 /* Synchronize ID */ 2296 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2297 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2298 /* clear port changed, */ 2299 /* use sequence number. */ 2300 uint8_t reserved_1; 2301 __le16 sequence_number; /* Sequence number of event */ 2302 __le16 lun; /* SCSI LUN */ 2303 uint8_t reserved_2[48]; 2304 } mrk_entry_t; 2305 2306 /* 2307 * ISP queue - Management Server entry structure definition. 2308 */ 2309 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2310 typedef struct { 2311 uint8_t entry_type; /* Entry type. */ 2312 uint8_t entry_count; /* Entry count. */ 2313 uint8_t handle_count; /* Handle count. */ 2314 uint8_t entry_status; /* Entry Status. */ 2315 uint32_t handle1; /* System handle. */ 2316 target_id_t loop_id; 2317 __le16 status; 2318 __le16 control_flags; /* Control flags. */ 2319 uint16_t reserved2; 2320 __le16 timeout; 2321 __le16 cmd_dsd_count; 2322 __le16 total_dsd_count; 2323 uint8_t type; 2324 uint8_t r_ctl; 2325 __le16 rx_id; 2326 uint16_t reserved3; 2327 uint32_t handle2; 2328 __le32 rsp_bytecount; 2329 __le32 req_bytecount; 2330 struct dsd64 req_dsd; 2331 struct dsd64 rsp_dsd; 2332 } ms_iocb_entry_t; 2333 2334 #define SCM_EDC_ACC_RECEIVED BIT_6 2335 #define SCM_RDF_ACC_RECEIVED BIT_7 2336 2337 /* 2338 * ISP queue - Mailbox Command entry structure definition. 2339 */ 2340 #define MBX_IOCB_TYPE 0x39 2341 struct mbx_entry { 2342 uint8_t entry_type; 2343 uint8_t entry_count; 2344 uint8_t sys_define1; 2345 /* Use sys_define1 for source type */ 2346 #define SOURCE_SCSI 0x00 2347 #define SOURCE_IP 0x01 2348 #define SOURCE_VI 0x02 2349 #define SOURCE_SCTP 0x03 2350 #define SOURCE_MP 0x04 2351 #define SOURCE_MPIOCTL 0x05 2352 #define SOURCE_ASYNC_IOCB 0x07 2353 2354 uint8_t entry_status; 2355 2356 uint32_t handle; 2357 target_id_t loop_id; 2358 2359 __le16 status; 2360 __le16 state_flags; 2361 __le16 status_flags; 2362 2363 uint32_t sys_define2[2]; 2364 2365 __le16 mb0; 2366 __le16 mb1; 2367 __le16 mb2; 2368 __le16 mb3; 2369 __le16 mb6; 2370 __le16 mb7; 2371 __le16 mb9; 2372 __le16 mb10; 2373 uint32_t reserved_2[2]; 2374 uint8_t node_name[WWN_SIZE]; 2375 uint8_t port_name[WWN_SIZE]; 2376 }; 2377 2378 #ifndef IMMED_NOTIFY_TYPE 2379 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2380 /* 2381 * ISP queue - immediate notify entry structure definition. 2382 * This is sent by the ISP to the Target driver. 2383 * This IOCB would have report of events sent by the 2384 * initiator, that needs to be handled by the target 2385 * driver immediately. 2386 */ 2387 struct imm_ntfy_from_isp { 2388 uint8_t entry_type; /* Entry type. */ 2389 uint8_t entry_count; /* Entry count. */ 2390 uint8_t sys_define; /* System defined. */ 2391 uint8_t entry_status; /* Entry Status. */ 2392 union { 2393 struct { 2394 __le32 sys_define_2; /* System defined. */ 2395 target_id_t target; 2396 __le16 lun; 2397 uint8_t target_id; 2398 uint8_t reserved_1; 2399 __le16 status_modifier; 2400 __le16 status; 2401 __le16 task_flags; 2402 __le16 seq_id; 2403 __le16 srr_rx_id; 2404 __le32 srr_rel_offs; 2405 __le16 srr_ui; 2406 #define SRR_IU_DATA_IN 0x1 2407 #define SRR_IU_DATA_OUT 0x5 2408 #define SRR_IU_STATUS 0x7 2409 __le16 srr_ox_id; 2410 uint8_t reserved_2[28]; 2411 } isp2x; 2412 struct { 2413 uint32_t reserved; 2414 __le16 nport_handle; 2415 uint16_t reserved_2; 2416 __le16 flags; 2417 #define NOTIFY24XX_FLAGS_FCSP BIT_5 2418 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2419 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2420 __le16 srr_rx_id; 2421 __le16 status; 2422 uint8_t status_subcode; 2423 uint8_t fw_handle; 2424 __le32 exchange_address; 2425 __le32 srr_rel_offs; 2426 __le16 srr_ui; 2427 __le16 srr_ox_id; 2428 union { 2429 struct { 2430 uint8_t node_name[8]; 2431 } plogi; /* PLOGI/ADISC/PDISC */ 2432 struct { 2433 /* PRLI word 3 bit 0-15 */ 2434 __le16 wd3_lo; 2435 uint8_t resv0[6]; 2436 } prli; 2437 struct { 2438 uint8_t port_id[3]; 2439 uint8_t resv1; 2440 __le16 nport_handle; 2441 uint16_t resv2; 2442 } req_els; 2443 } u; 2444 uint8_t port_name[8]; 2445 uint8_t resv3[3]; 2446 uint8_t vp_index; 2447 uint32_t reserved_5; 2448 uint8_t port_id[3]; 2449 uint8_t reserved_6; 2450 } isp24; 2451 } u; 2452 uint16_t reserved_7; 2453 __le16 ox_id; 2454 } __packed; 2455 #endif 2456 2457 /* 2458 * ISP request and response queue entry sizes 2459 */ 2460 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2461 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2462 2463 2464 2465 /* 2466 * Switch info gathering structure. 2467 */ 2468 typedef struct { 2469 port_id_t d_id; 2470 uint8_t node_name[WWN_SIZE]; 2471 uint8_t port_name[WWN_SIZE]; 2472 uint8_t fabric_port_name[WWN_SIZE]; 2473 uint16_t fp_speed; 2474 uint8_t fc4_type; 2475 uint8_t fc4_features; 2476 } sw_info_t; 2477 2478 /* FCP-4 types */ 2479 #define FC4_TYPE_FCP_SCSI 0x08 2480 #define FC4_TYPE_NVME 0x28 2481 #define FC4_TYPE_OTHER 0x0 2482 #define FC4_TYPE_UNKNOWN 0xff 2483 2484 /* mailbox command 4G & above */ 2485 struct mbx_24xx_entry { 2486 uint8_t entry_type; 2487 uint8_t entry_count; 2488 uint8_t sys_define1; 2489 uint8_t entry_status; 2490 uint32_t handle; 2491 uint16_t mb[28]; 2492 }; 2493 2494 #define IOCB_SIZE 64 2495 2496 /* 2497 * Fibre channel port type. 2498 */ 2499 typedef enum { 2500 FCT_UNKNOWN, 2501 FCT_BROADCAST = 0x01, 2502 FCT_INITIATOR = 0x02, 2503 FCT_TARGET = 0x04, 2504 FCT_NVME_INITIATOR = 0x10, 2505 FCT_NVME_TARGET = 0x20, 2506 FCT_NVME_DISCOVERY = 0x40, 2507 FCT_NVME = 0xf0, 2508 } fc_port_type_t; 2509 2510 enum qla_sess_deletion { 2511 QLA_SESS_DELETION_NONE = 0, 2512 QLA_SESS_DELETION_IN_PROGRESS, 2513 QLA_SESS_DELETED, 2514 }; 2515 2516 enum qlt_plogi_link_t { 2517 QLT_PLOGI_LINK_SAME_WWN, 2518 QLT_PLOGI_LINK_CONFLICT, 2519 QLT_PLOGI_LINK_MAX 2520 }; 2521 2522 struct qlt_plogi_ack_t { 2523 struct list_head list; 2524 struct imm_ntfy_from_isp iocb; 2525 port_id_t id; 2526 int ref_count; 2527 void *fcport; 2528 }; 2529 2530 struct ct_sns_desc { 2531 struct ct_sns_pkt *ct_sns; 2532 dma_addr_t ct_sns_dma; 2533 }; 2534 2535 enum discovery_state { 2536 DSC_DELETED, 2537 DSC_GNL, 2538 DSC_LOGIN_PEND, 2539 DSC_LOGIN_FAILED, 2540 DSC_GPDB, 2541 DSC_UPD_FCPORT, 2542 DSC_LOGIN_COMPLETE, 2543 DSC_ADISC, 2544 DSC_DELETE_PEND, 2545 DSC_LOGIN_AUTH_PEND, 2546 }; 2547 2548 enum login_state { /* FW control Target side */ 2549 DSC_LS_LLIOCB_SENT = 2, 2550 DSC_LS_PLOGI_PEND, 2551 DSC_LS_PLOGI_COMP, 2552 DSC_LS_PRLI_PEND, 2553 DSC_LS_PRLI_COMP, 2554 DSC_LS_PORT_UNAVAIL, 2555 DSC_LS_PRLO_PEND = 9, 2556 DSC_LS_LOGO_PEND, 2557 }; 2558 2559 enum rscn_addr_format { 2560 RSCN_PORT_ADDR, 2561 RSCN_AREA_ADDR, 2562 RSCN_DOM_ADDR, 2563 RSCN_FAB_ADDR, 2564 }; 2565 2566 /* 2567 * Fibre channel port structure. 2568 */ 2569 typedef struct fc_port { 2570 struct list_head list; 2571 struct scsi_qla_host *vha; 2572 struct list_head unsol_ctx_head; 2573 2574 unsigned int conf_compl_supported:1; 2575 unsigned int deleted:2; 2576 unsigned int free_pending:1; 2577 unsigned int local:1; 2578 unsigned int logout_on_delete:1; 2579 unsigned int logo_ack_needed:1; 2580 unsigned int keep_nport_handle:1; 2581 unsigned int send_els_logo:1; 2582 unsigned int login_pause:1; 2583 unsigned int login_succ:1; 2584 unsigned int query:1; 2585 unsigned int id_changed:1; 2586 unsigned int scan_needed:1; 2587 unsigned int n2n_flag:1; 2588 unsigned int explicit_logout:1; 2589 unsigned int prli_pend_timer:1; 2590 unsigned int do_prli_nvme:1; 2591 2592 uint8_t nvme_flag; 2593 uint8_t node_name[WWN_SIZE]; 2594 uint8_t port_name[WWN_SIZE]; 2595 port_id_t d_id; 2596 uint16_t loop_id; 2597 uint16_t old_loop_id; 2598 2599 struct completion nvme_del_done; 2600 uint32_t nvme_prli_service_param; 2601 #define NVME_PRLI_SP_PI_CTRL BIT_9 2602 #define NVME_PRLI_SP_SLER BIT_8 2603 #define NVME_PRLI_SP_CONF BIT_7 2604 #define NVME_PRLI_SP_INITIATOR BIT_5 2605 #define NVME_PRLI_SP_TARGET BIT_4 2606 #define NVME_PRLI_SP_DISCOVERY BIT_3 2607 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2608 2609 uint32_t nvme_first_burst_size; 2610 #define NVME_FLAG_REGISTERED 4 2611 #define NVME_FLAG_DELETING 2 2612 #define NVME_FLAG_RESETTING 1 2613 2614 struct fc_port *conflict; 2615 unsigned char logout_completed; 2616 int generation; 2617 2618 struct se_session *se_sess; 2619 struct list_head sess_cmd_list; 2620 spinlock_t sess_cmd_lock; 2621 struct kref sess_kref; 2622 struct qla_tgt *tgt; 2623 unsigned long expires; 2624 struct list_head del_list_entry; 2625 struct work_struct free_work; 2626 struct work_struct reg_work; 2627 uint64_t jiffies_at_registration; 2628 unsigned long prli_expired; 2629 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2630 2631 uint16_t tgt_id; 2632 uint16_t old_tgt_id; 2633 uint16_t sec_since_registration; 2634 2635 uint8_t fcp_prio; 2636 2637 uint8_t fabric_port_name[WWN_SIZE]; 2638 uint16_t fp_speed; 2639 2640 fc_port_type_t port_type; 2641 2642 atomic_t state; 2643 uint32_t flags; 2644 2645 int login_retry; 2646 2647 struct fc_rport *rport; 2648 u32 supported_classes; 2649 2650 uint8_t fc4_type; 2651 uint8_t fc4_features; 2652 uint8_t scan_state; 2653 2654 unsigned long last_queue_full; 2655 unsigned long last_ramp_up; 2656 2657 uint16_t port_id; 2658 2659 struct nvme_fc_remote_port *nvme_remote_port; 2660 2661 unsigned long retry_delay_timestamp; 2662 struct qla_tgt_sess *tgt_session; 2663 struct ct_sns_desc ct_desc; 2664 enum discovery_state disc_state; 2665 atomic_t shadow_disc_state; 2666 enum discovery_state next_disc_state; 2667 enum login_state fw_login_state; 2668 unsigned long dm_login_expire; 2669 unsigned long plogi_nack_done_deadline; 2670 2671 u32 login_gen, last_login_gen; 2672 u32 rscn_gen, last_rscn_gen; 2673 u32 chip_reset; 2674 struct list_head gnl_entry; 2675 struct work_struct del_work; 2676 u8 iocb[IOCB_SIZE]; 2677 u8 current_login_state; 2678 u8 last_login_state; 2679 u16 n2n_link_reset_cnt; 2680 u16 n2n_chip_reset; 2681 2682 struct dentry *dfs_rport_dir; 2683 2684 u64 tgt_short_link_down_cnt; 2685 u64 tgt_link_down_time; 2686 u64 dev_loss_tmo; 2687 /* 2688 * EDIF parameters for encryption. 2689 */ 2690 struct { 2691 uint32_t enable:1; /* device is edif enabled/req'd */ 2692 uint32_t app_stop:2; 2693 uint32_t aes_gmac:1; 2694 uint32_t app_sess_online:1; 2695 uint32_t tx_sa_set:1; 2696 uint32_t rx_sa_set:1; 2697 uint32_t tx_sa_pending:1; 2698 uint32_t rx_sa_pending:1; 2699 uint32_t tx_rekey_cnt; 2700 uint32_t rx_rekey_cnt; 2701 uint64_t tx_bytes; 2702 uint64_t rx_bytes; 2703 uint8_t sess_down_acked; 2704 uint8_t auth_state; 2705 uint16_t authok:1; 2706 uint16_t rekey_cnt; 2707 struct list_head edif_indx_list; 2708 spinlock_t indx_list_lock; 2709 2710 struct list_head tx_sa_list; 2711 struct list_head rx_sa_list; 2712 spinlock_t sa_list_lock; 2713 } edif; 2714 } fc_port_t; 2715 2716 enum { 2717 FC4_PRIORITY_NVME = 1, 2718 FC4_PRIORITY_FCP = 2, 2719 }; 2720 2721 #define QLA_FCPORT_SCAN 1 2722 #define QLA_FCPORT_FOUND 2 2723 2724 struct event_arg { 2725 fc_port_t *fcport; 2726 srb_t *sp; 2727 port_id_t id; 2728 u16 data[2], rc; 2729 u8 port_name[WWN_SIZE]; 2730 u32 iop[2]; 2731 }; 2732 2733 #include "qla_mr.h" 2734 2735 /* 2736 * Fibre channel port/lun states. 2737 */ 2738 enum { 2739 FCS_UNKNOWN, 2740 FCS_UNCONFIGURED, 2741 FCS_DEVICE_DEAD, 2742 FCS_DEVICE_LOST, 2743 FCS_ONLINE, 2744 }; 2745 2746 extern const char *const port_state_str[5]; 2747 2748 static const char *const port_dstate_str[] = { 2749 [DSC_DELETED] = "DELETED", 2750 [DSC_GNL] = "GNL", 2751 [DSC_LOGIN_PEND] = "LOGIN_PEND", 2752 [DSC_LOGIN_FAILED] = "LOGIN_FAILED", 2753 [DSC_GPDB] = "GPDB", 2754 [DSC_UPD_FCPORT] = "UPD_FCPORT", 2755 [DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE", 2756 [DSC_ADISC] = "ADISC", 2757 [DSC_DELETE_PEND] = "DELETE_PEND", 2758 [DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND", 2759 }; 2760 2761 /* 2762 * FC port flags. 2763 */ 2764 #define FCF_FABRIC_DEVICE BIT_0 2765 #define FCF_LOGIN_NEEDED BIT_1 2766 #define FCF_FCP2_DEVICE BIT_2 2767 #define FCF_ASYNC_SENT BIT_3 2768 #define FCF_CONF_COMP_SUPPORTED BIT_4 2769 #define FCF_ASYNC_ACTIVE BIT_5 2770 #define FCF_FCSP_DEVICE BIT_6 2771 #define FCF_EDIF_DELETE BIT_7 2772 2773 /* No loop ID flag. */ 2774 #define FC_NO_LOOP_ID 0x1000 2775 2776 /* 2777 * FC-CT interface 2778 * 2779 * NOTE: All structures are big-endian in form. 2780 */ 2781 2782 #define CT_REJECT_RESPONSE 0x8001 2783 #define CT_ACCEPT_RESPONSE 0x8002 2784 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2785 #define CT_REASON_CANNOT_PERFORM 0x09 2786 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2787 #define CT_EXPL_ALREADY_REGISTERED 0x10 2788 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2789 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2790 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2791 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2792 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2793 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2794 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2795 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2796 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2797 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2798 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2799 2800 #define NS_N_PORT_TYPE 0x01 2801 #define NS_NL_PORT_TYPE 0x02 2802 #define NS_NX_PORT_TYPE 0x7F 2803 2804 #define GA_NXT_CMD 0x100 2805 #define GA_NXT_REQ_SIZE (16 + 4) 2806 #define GA_NXT_RSP_SIZE (16 + 620) 2807 2808 #define GPN_FT_CMD 0x172 2809 #define GPN_FT_REQ_SIZE (16 + 4) 2810 #define GNN_FT_CMD 0x173 2811 #define GNN_FT_REQ_SIZE (16 + 4) 2812 2813 #define GID_PT_CMD 0x1A1 2814 #define GID_PT_REQ_SIZE (16 + 4) 2815 2816 #define GPN_ID_CMD 0x112 2817 #define GPN_ID_REQ_SIZE (16 + 4) 2818 #define GPN_ID_RSP_SIZE (16 + 8) 2819 2820 #define GNN_ID_CMD 0x113 2821 #define GNN_ID_REQ_SIZE (16 + 4) 2822 #define GNN_ID_RSP_SIZE (16 + 8) 2823 2824 #define GFT_ID_CMD 0x117 2825 #define GFT_ID_REQ_SIZE (16 + 4) 2826 #define GFT_ID_RSP_SIZE (16 + 32) 2827 2828 #define GID_PN_CMD 0x121 2829 #define GID_PN_REQ_SIZE (16 + 8) 2830 #define GID_PN_RSP_SIZE (16 + 4) 2831 2832 #define RFT_ID_CMD 0x217 2833 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2834 #define RFT_ID_RSP_SIZE 16 2835 2836 #define RFF_ID_CMD 0x21F 2837 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2838 #define RFF_ID_RSP_SIZE 16 2839 2840 #define RNN_ID_CMD 0x213 2841 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2842 #define RNN_ID_RSP_SIZE 16 2843 2844 #define RSNN_NN_CMD 0x239 2845 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2846 #define RSNN_NN_RSP_SIZE 16 2847 2848 #define GFPN_ID_CMD 0x11C 2849 #define GFPN_ID_REQ_SIZE (16 + 4) 2850 #define GFPN_ID_RSP_SIZE (16 + 8) 2851 2852 #define GPSC_CMD 0x127 2853 #define GPSC_REQ_SIZE (16 + 8) 2854 #define GPSC_RSP_SIZE (16 + 2 + 2) 2855 2856 #define GFF_ID_CMD 0x011F 2857 #define GFF_ID_REQ_SIZE (16 + 4) 2858 #define GFF_ID_RSP_SIZE (16 + 128) 2859 2860 /* 2861 * FDMI HBA attribute types. 2862 */ 2863 #define FDMI1_HBA_ATTR_COUNT 10 2864 #define FDMI2_HBA_ATTR_COUNT 17 2865 2866 #define FDMI_HBA_NODE_NAME 0x1 2867 #define FDMI_HBA_MANUFACTURER 0x2 2868 #define FDMI_HBA_SERIAL_NUMBER 0x3 2869 #define FDMI_HBA_MODEL 0x4 2870 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2871 #define FDMI_HBA_HARDWARE_VERSION 0x6 2872 #define FDMI_HBA_DRIVER_VERSION 0x7 2873 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2874 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2875 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2876 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2877 2878 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2879 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd 2880 #define FDMI_HBA_NUM_PORTS 0xe 2881 #define FDMI_HBA_FABRIC_NAME 0xf 2882 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2883 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0 2884 2885 struct ct_fdmi_hba_attr { 2886 __be16 type; 2887 __be16 len; 2888 union { 2889 uint8_t node_name[WWN_SIZE]; 2890 uint8_t manufacturer[64]; 2891 uint8_t serial_num[32]; 2892 uint8_t model[16+1]; 2893 uint8_t model_desc[80]; 2894 uint8_t hw_version[32]; 2895 uint8_t driver_version[32]; 2896 uint8_t orom_version[16]; 2897 uint8_t fw_version[32]; 2898 uint8_t os_version[128]; 2899 __be32 max_ct_len; 2900 2901 uint8_t sym_name[256]; 2902 __be32 vendor_specific_info; 2903 __be32 num_ports; 2904 uint8_t fabric_name[WWN_SIZE]; 2905 uint8_t bios_name[32]; 2906 uint8_t vendor_identifier[8]; 2907 } a; 2908 }; 2909 2910 struct ct_fdmi1_hba_attributes { 2911 __be32 count; 2912 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT]; 2913 }; 2914 2915 struct ct_fdmi2_hba_attributes { 2916 __be32 count; 2917 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT]; 2918 }; 2919 2920 /* 2921 * FDMI Port attribute types. 2922 */ 2923 #define FDMI1_PORT_ATTR_COUNT 6 2924 #define FDMI2_PORT_ATTR_COUNT 16 2925 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23 2926 2927 #define FDMI_PORT_FC4_TYPES 0x1 2928 #define FDMI_PORT_SUPPORT_SPEED 0x2 2929 #define FDMI_PORT_CURRENT_SPEED 0x3 2930 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2931 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2932 #define FDMI_PORT_HOST_NAME 0x6 2933 2934 #define FDMI_PORT_NODE_NAME 0x7 2935 #define FDMI_PORT_NAME 0x8 2936 #define FDMI_PORT_SYM_NAME 0x9 2937 #define FDMI_PORT_TYPE 0xa 2938 #define FDMI_PORT_SUPP_COS 0xb 2939 #define FDMI_PORT_FABRIC_NAME 0xc 2940 #define FDMI_PORT_FC4_TYPE 0xd 2941 #define FDMI_PORT_STATE 0x101 2942 #define FDMI_PORT_COUNT 0x102 2943 #define FDMI_PORT_IDENTIFIER 0x103 2944 2945 #define FDMI_SMARTSAN_SERVICE 0xF100 2946 #define FDMI_SMARTSAN_GUID 0xF101 2947 #define FDMI_SMARTSAN_VERSION 0xF102 2948 #define FDMI_SMARTSAN_PROD_NAME 0xF103 2949 #define FDMI_SMARTSAN_PORT_INFO 0xF104 2950 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105 2951 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106 2952 2953 #define FDMI_PORT_SPEED_1GB 0x1 2954 #define FDMI_PORT_SPEED_2GB 0x2 2955 #define FDMI_PORT_SPEED_10GB 0x4 2956 #define FDMI_PORT_SPEED_4GB 0x8 2957 #define FDMI_PORT_SPEED_8GB 0x10 2958 #define FDMI_PORT_SPEED_16GB 0x20 2959 #define FDMI_PORT_SPEED_32GB 0x40 2960 #define FDMI_PORT_SPEED_20GB 0x80 2961 #define FDMI_PORT_SPEED_40GB 0x100 2962 #define FDMI_PORT_SPEED_128GB 0x200 2963 #define FDMI_PORT_SPEED_64GB 0x400 2964 #define FDMI_PORT_SPEED_256GB 0x800 2965 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2966 2967 #define FC_CLASS_2 0x04 2968 #define FC_CLASS_3 0x08 2969 #define FC_CLASS_2_3 0x0C 2970 2971 struct ct_fdmi_port_attr { 2972 __be16 type; 2973 __be16 len; 2974 union { 2975 uint8_t fc4_types[32]; 2976 __be32 sup_speed; 2977 __be32 cur_speed; 2978 __be32 max_frame_size; 2979 uint8_t os_dev_name[32]; 2980 uint8_t host_name[256]; 2981 2982 uint8_t node_name[WWN_SIZE]; 2983 uint8_t port_name[WWN_SIZE]; 2984 uint8_t port_sym_name[128]; 2985 __be32 port_type; 2986 __be32 port_supported_cos; 2987 uint8_t fabric_name[WWN_SIZE]; 2988 uint8_t port_fc4_type[32]; 2989 __be32 port_state; 2990 __be32 num_ports; 2991 __be32 port_id; 2992 2993 uint8_t smartsan_service[24]; 2994 uint8_t smartsan_guid[16]; 2995 uint8_t smartsan_version[24]; 2996 uint8_t smartsan_prod_name[16]; 2997 __be32 smartsan_port_info; 2998 __be32 smartsan_qos_support; 2999 __be32 smartsan_security_support; 3000 } a; 3001 }; 3002 3003 struct ct_fdmi1_port_attributes { 3004 __be32 count; 3005 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT]; 3006 }; 3007 3008 struct ct_fdmi2_port_attributes { 3009 __be32 count; 3010 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT]; 3011 }; 3012 3013 #define FDMI_ATTR_TYPELEN(obj) \ 3014 (sizeof((obj)->type) + sizeof((obj)->len)) 3015 3016 #define FDMI_ATTR_ALIGNMENT(len) \ 3017 (4 - ((len) & 3)) 3018 3019 /* FDMI register call options */ 3020 #define CALLOPT_FDMI1 0 3021 #define CALLOPT_FDMI2 1 3022 #define CALLOPT_FDMI2_SMARTSAN 2 3023 3024 /* FDMI definitions. */ 3025 #define GRHL_CMD 0x100 3026 #define GHAT_CMD 0x101 3027 #define GRPL_CMD 0x102 3028 #define GPAT_CMD 0x110 3029 3030 #define RHBA_CMD 0x200 3031 #define RHBA_RSP_SIZE 16 3032 3033 #define RHAT_CMD 0x201 3034 3035 #define RPRT_CMD 0x210 3036 #define RPRT_RSP_SIZE 24 3037 3038 #define RPA_CMD 0x211 3039 #define RPA_RSP_SIZE 16 3040 #define SMARTSAN_RPA_RSP_SIZE 24 3041 3042 #define DHBA_CMD 0x300 3043 #define DHBA_REQ_SIZE (16 + 8) 3044 #define DHBA_RSP_SIZE 16 3045 3046 #define DHAT_CMD 0x301 3047 #define DPRT_CMD 0x310 3048 #define DPA_CMD 0x311 3049 3050 /* CT command header -- request/response common fields */ 3051 struct ct_cmd_hdr { 3052 uint8_t revision; 3053 uint8_t in_id[3]; 3054 uint8_t gs_type; 3055 uint8_t gs_subtype; 3056 uint8_t options; 3057 uint8_t reserved; 3058 }; 3059 3060 /* CT command request */ 3061 struct ct_sns_req { 3062 struct ct_cmd_hdr header; 3063 __be16 command; 3064 __be16 max_rsp_size; 3065 uint8_t fragment_id; 3066 uint8_t reserved[3]; 3067 3068 union { 3069 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 3070 struct { 3071 uint8_t reserved; 3072 be_id_t port_id; 3073 } port_id; 3074 3075 struct { 3076 uint8_t reserved; 3077 uint8_t domain; 3078 uint8_t area; 3079 uint8_t port_type; 3080 } gpn_ft; 3081 3082 struct { 3083 uint8_t port_type; 3084 uint8_t domain; 3085 uint8_t area; 3086 uint8_t reserved; 3087 } gid_pt; 3088 3089 struct { 3090 uint8_t reserved; 3091 be_id_t port_id; 3092 uint8_t fc4_types[32]; 3093 } rft_id; 3094 3095 struct { 3096 uint8_t reserved; 3097 be_id_t port_id; 3098 uint16_t reserved2; 3099 uint8_t fc4_feature; 3100 uint8_t fc4_type; 3101 } rff_id; 3102 3103 struct { 3104 uint8_t reserved; 3105 be_id_t port_id; 3106 uint8_t node_name[8]; 3107 } rnn_id; 3108 3109 struct { 3110 uint8_t node_name[8]; 3111 uint8_t name_len; 3112 uint8_t sym_node_name[255]; 3113 } rsnn_nn; 3114 3115 struct { 3116 uint8_t hba_identifier[8]; 3117 } ghat; 3118 3119 struct { 3120 uint8_t hba_identifier[8]; 3121 __be32 entry_count; 3122 uint8_t port_name[8]; 3123 struct ct_fdmi2_hba_attributes attrs; 3124 } rhba; 3125 3126 struct { 3127 uint8_t hba_identifier[8]; 3128 struct ct_fdmi1_hba_attributes attrs; 3129 } rhat; 3130 3131 struct { 3132 uint8_t port_name[8]; 3133 struct ct_fdmi2_port_attributes attrs; 3134 } rpa; 3135 3136 struct { 3137 uint8_t hba_identifier[8]; 3138 uint8_t port_name[8]; 3139 struct ct_fdmi2_port_attributes attrs; 3140 } rprt; 3141 3142 struct { 3143 uint8_t port_name[8]; 3144 } dhba; 3145 3146 struct { 3147 uint8_t port_name[8]; 3148 } dhat; 3149 3150 struct { 3151 uint8_t port_name[8]; 3152 } dprt; 3153 3154 struct { 3155 uint8_t port_name[8]; 3156 } dpa; 3157 3158 struct { 3159 uint8_t port_name[8]; 3160 } gpsc; 3161 3162 struct { 3163 uint8_t reserved; 3164 uint8_t port_id[3]; 3165 } gff_id; 3166 3167 struct { 3168 uint8_t port_name[8]; 3169 } gid_pn; 3170 } req; 3171 }; 3172 3173 /* CT command response header */ 3174 struct ct_rsp_hdr { 3175 struct ct_cmd_hdr header; 3176 __be16 response; 3177 uint16_t residual; 3178 uint8_t fragment_id; 3179 uint8_t reason_code; 3180 uint8_t explanation_code; 3181 uint8_t vendor_unique; 3182 }; 3183 3184 struct ct_sns_gid_pt_data { 3185 uint8_t control_byte; 3186 be_id_t port_id; 3187 }; 3188 3189 /* It's the same for both GPN_FT and GNN_FT */ 3190 struct ct_sns_gpnft_rsp { 3191 struct { 3192 struct ct_cmd_hdr header; 3193 uint16_t response; 3194 uint16_t residual; 3195 uint8_t fragment_id; 3196 uint8_t reason_code; 3197 uint8_t explanation_code; 3198 uint8_t vendor_unique; 3199 }; 3200 /* Assume the largest number of targets for the union */ 3201 DECLARE_FLEX_ARRAY(struct ct_sns_gpn_ft_data { 3202 u8 control_byte; 3203 u8 port_id[3]; 3204 u32 reserved; 3205 u8 port_name[8]; 3206 }, entries); 3207 }; 3208 3209 /* CT command response */ 3210 struct ct_sns_rsp { 3211 struct ct_rsp_hdr header; 3212 3213 union { 3214 struct { 3215 uint8_t port_type; 3216 be_id_t port_id; 3217 uint8_t port_name[8]; 3218 uint8_t sym_port_name_len; 3219 uint8_t sym_port_name[255]; 3220 uint8_t node_name[8]; 3221 uint8_t sym_node_name_len; 3222 uint8_t sym_node_name[255]; 3223 uint8_t init_proc_assoc[8]; 3224 uint8_t node_ip_addr[16]; 3225 uint8_t class_of_service[4]; 3226 uint8_t fc4_types[32]; 3227 uint8_t ip_address[16]; 3228 uint8_t fabric_port_name[8]; 3229 uint8_t reserved; 3230 uint8_t hard_address[3]; 3231 } ga_nxt; 3232 3233 struct { 3234 /* Assume the largest number of targets for the union */ 3235 struct ct_sns_gid_pt_data 3236 entries[MAX_FIBRE_DEVICES_MAX]; 3237 } gid_pt; 3238 3239 struct { 3240 uint8_t port_name[8]; 3241 } gpn_id; 3242 3243 struct { 3244 uint8_t node_name[8]; 3245 } gnn_id; 3246 3247 struct { 3248 uint8_t fc4_types[32]; 3249 } gft_id; 3250 3251 struct { 3252 uint32_t entry_count; 3253 uint8_t port_name[8]; 3254 struct ct_fdmi1_hba_attributes attrs; 3255 } ghat; 3256 3257 struct { 3258 uint8_t port_name[8]; 3259 } gfpn_id; 3260 3261 struct { 3262 __be16 speeds; 3263 __be16 speed; 3264 } gpsc; 3265 3266 #define GFF_FCP_SCSI_OFFSET 7 3267 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3268 struct { 3269 uint8_t fc4_features[128]; 3270 #define FC4_FF_TARGET BIT_0 3271 #define FC4_FF_INITIATOR BIT_1 3272 } gff_id; 3273 struct { 3274 uint8_t reserved; 3275 uint8_t port_id[3]; 3276 } gid_pn; 3277 } rsp; 3278 }; 3279 3280 struct ct_sns_pkt { 3281 union { 3282 struct ct_sns_req req; 3283 struct ct_sns_rsp rsp; 3284 } p; 3285 }; 3286 3287 struct ct_sns_gpnft_pkt { 3288 union { 3289 struct ct_sns_req req; 3290 struct ct_sns_gpnft_rsp rsp; 3291 } p; 3292 }; 3293 3294 enum scan_flags_t { 3295 SF_SCANNING = BIT_0, 3296 SF_QUEUED = BIT_1, 3297 }; 3298 3299 enum fc4type_t { 3300 FS_FC4TYPE_FCP = BIT_0, 3301 FS_FC4TYPE_NVME = BIT_1, 3302 FS_FCP_IS_N2N = BIT_7, 3303 }; 3304 3305 struct fab_scan_rp { 3306 port_id_t id; 3307 enum fc4type_t fc4type; 3308 u8 port_name[8]; 3309 u8 node_name[8]; 3310 }; 3311 3312 struct fab_scan { 3313 struct fab_scan_rp *l; 3314 u32 size; 3315 u16 scan_retry; 3316 #define MAX_SCAN_RETRIES 5 3317 enum scan_flags_t scan_flags; 3318 struct delayed_work scan_work; 3319 }; 3320 3321 /* 3322 * SNS command structures -- for 2200 compatibility. 3323 */ 3324 #define RFT_ID_SNS_SCMD_LEN 22 3325 #define RFT_ID_SNS_CMD_SIZE 60 3326 #define RFT_ID_SNS_DATA_SIZE 16 3327 3328 #define RNN_ID_SNS_SCMD_LEN 10 3329 #define RNN_ID_SNS_CMD_SIZE 36 3330 #define RNN_ID_SNS_DATA_SIZE 16 3331 3332 #define GA_NXT_SNS_SCMD_LEN 6 3333 #define GA_NXT_SNS_CMD_SIZE 28 3334 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3335 3336 #define GID_PT_SNS_SCMD_LEN 6 3337 #define GID_PT_SNS_CMD_SIZE 28 3338 /* 3339 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3340 * adapters. 3341 */ 3342 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3343 3344 #define GPN_ID_SNS_SCMD_LEN 6 3345 #define GPN_ID_SNS_CMD_SIZE 28 3346 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3347 3348 #define GNN_ID_SNS_SCMD_LEN 6 3349 #define GNN_ID_SNS_CMD_SIZE 28 3350 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3351 3352 struct sns_cmd_pkt { 3353 union { 3354 struct { 3355 __le16 buffer_length; 3356 __le16 reserved_1; 3357 __le64 buffer_address __packed; 3358 __le16 subcommand_length; 3359 __le16 reserved_2; 3360 __le16 subcommand; 3361 __le16 size; 3362 uint32_t reserved_3; 3363 uint8_t param[36]; 3364 } cmd; 3365 3366 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3367 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3368 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3369 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3370 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3371 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3372 } p; 3373 }; 3374 3375 struct fw_blob { 3376 char *name; 3377 uint32_t segs[4]; 3378 const struct firmware *fw; 3379 }; 3380 3381 /* Return data from MBC_GET_ID_LIST call. */ 3382 struct gid_list_info { 3383 uint8_t al_pa; 3384 uint8_t area; 3385 uint8_t domain; 3386 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3387 __le16 loop_id; /* ISP23XX -- 6 bytes. */ 3388 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3389 }; 3390 3391 /* NPIV */ 3392 typedef struct vport_info { 3393 uint8_t port_name[WWN_SIZE]; 3394 uint8_t node_name[WWN_SIZE]; 3395 int vp_id; 3396 uint16_t loop_id; 3397 unsigned long host_no; 3398 uint8_t port_id[3]; 3399 int loop_state; 3400 } vport_info_t; 3401 3402 typedef struct vport_params { 3403 uint8_t port_name[WWN_SIZE]; 3404 uint8_t node_name[WWN_SIZE]; 3405 uint32_t options; 3406 #define VP_OPTS_RETRY_ENABLE BIT_0 3407 #define VP_OPTS_VP_DISABLE BIT_1 3408 } vport_params_t; 3409 3410 /* NPIV - return codes of VP create and modify */ 3411 #define VP_RET_CODE_OK 0 3412 #define VP_RET_CODE_FATAL 1 3413 #define VP_RET_CODE_WRONG_ID 2 3414 #define VP_RET_CODE_WWPN 3 3415 #define VP_RET_CODE_RESOURCES 4 3416 #define VP_RET_CODE_NO_MEM 5 3417 #define VP_RET_CODE_NOT_FOUND 6 3418 3419 struct qla_hw_data; 3420 struct rsp_que; 3421 /* 3422 * ISP operations 3423 */ 3424 struct isp_operations { 3425 3426 int (*pci_config) (struct scsi_qla_host *); 3427 int (*reset_chip)(struct scsi_qla_host *); 3428 int (*chip_diag) (struct scsi_qla_host *); 3429 void (*config_rings) (struct scsi_qla_host *); 3430 int (*reset_adapter)(struct scsi_qla_host *); 3431 int (*nvram_config) (struct scsi_qla_host *); 3432 void (*update_fw_options) (struct scsi_qla_host *); 3433 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3434 3435 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3436 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3437 3438 irq_handler_t intr_handler; 3439 void (*enable_intrs) (struct qla_hw_data *); 3440 void (*disable_intrs) (struct qla_hw_data *); 3441 3442 int (*abort_command) (srb_t *); 3443 int (*target_reset) (struct fc_port *, uint64_t, int); 3444 int (*lun_reset) (struct fc_port *, uint64_t, int); 3445 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3446 uint8_t, uint8_t, uint16_t *, uint8_t); 3447 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3448 uint8_t, uint8_t); 3449 3450 uint16_t (*calc_req_entries) (uint16_t); 3451 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3452 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3453 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3454 uint32_t); 3455 3456 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3457 uint32_t, uint32_t); 3458 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3459 uint32_t); 3460 3461 void (*fw_dump)(struct scsi_qla_host *vha); 3462 void (*mpi_fw_dump)(struct scsi_qla_host *, int); 3463 3464 /* Context: task, might sleep */ 3465 int (*beacon_on) (struct scsi_qla_host *); 3466 int (*beacon_off) (struct scsi_qla_host *); 3467 3468 void (*beacon_blink) (struct scsi_qla_host *); 3469 3470 void *(*read_optrom)(struct scsi_qla_host *, void *, 3471 uint32_t, uint32_t); 3472 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3473 uint32_t); 3474 3475 int (*get_flash_version) (struct scsi_qla_host *, void *); 3476 int (*start_scsi) (srb_t *); 3477 int (*start_scsi_mq) (srb_t *); 3478 3479 /* Context: task, might sleep */ 3480 int (*abort_isp) (struct scsi_qla_host *); 3481 3482 int (*iospace_config)(struct qla_hw_data *); 3483 int (*initialize_adapter)(struct scsi_qla_host *); 3484 }; 3485 3486 /* MSI-X Support *************************************************************/ 3487 3488 #define QLA_MSIX_CHIP_REV_24XX 3 3489 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3490 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3491 3492 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3493 #define QLA_MSIX_RSP_Q 0x01 3494 #define QLA_ATIO_VECTOR 0x02 3495 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3496 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04 3497 3498 #define QLA_MIDX_DEFAULT 0 3499 #define QLA_MIDX_RSP_Q 1 3500 #define QLA_PCI_MSIX_CONTROL 0xa2 3501 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3502 3503 struct scsi_qla_host; 3504 3505 3506 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3507 3508 struct qla_msix_entry { 3509 int have_irq; 3510 int in_use; 3511 uint32_t vector; 3512 uint32_t vector_base0; 3513 uint16_t entry; 3514 char name[30]; 3515 void *handle; 3516 int cpuid; 3517 }; 3518 3519 #define WATCH_INTERVAL 1 /* number of seconds */ 3520 3521 /* Work events. */ 3522 enum qla_work_type { 3523 QLA_EVT_AEN, 3524 QLA_EVT_IDC_ACK, 3525 QLA_EVT_ASYNC_LOGIN, 3526 QLA_EVT_ASYNC_LOGOUT, 3527 QLA_EVT_ASYNC_ADISC, 3528 QLA_EVT_UEVENT, 3529 QLA_EVT_AENFX, 3530 QLA_EVT_UNMAP, 3531 QLA_EVT_NEW_SESS, 3532 QLA_EVT_GPDB, 3533 QLA_EVT_PRLI, 3534 QLA_EVT_GPSC, 3535 QLA_EVT_GNL, 3536 QLA_EVT_NACK, 3537 QLA_EVT_RELOGIN, 3538 QLA_EVT_ASYNC_PRLO, 3539 QLA_EVT_ASYNC_PRLO_DONE, 3540 QLA_EVT_GPNFT, 3541 QLA_EVT_GPNFT_DONE, 3542 QLA_EVT_GNNFT_DONE, 3543 QLA_EVT_GFPNID, 3544 QLA_EVT_SP_RETRY, 3545 QLA_EVT_IIDMA, 3546 QLA_EVT_ELS_PLOGI, 3547 QLA_EVT_SA_REPLACE, 3548 }; 3549 3550 3551 struct qla_work_evt { 3552 struct list_head list; 3553 enum qla_work_type type; 3554 u32 flags; 3555 #define QLA_EVT_FLAG_FREE 0x1 3556 3557 union { 3558 struct { 3559 enum fc_host_event_code code; 3560 u32 data; 3561 } aen; 3562 struct { 3563 #define QLA_IDC_ACK_REGS 7 3564 uint16_t mb[QLA_IDC_ACK_REGS]; 3565 } idc_ack; 3566 struct { 3567 struct fc_port *fcport; 3568 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3569 u16 data[2]; 3570 } logio; 3571 struct { 3572 u32 code; 3573 #define QLA_UEVENT_CODE_FW_DUMP 0 3574 } uevent; 3575 struct { 3576 uint32_t evtcode; 3577 uint32_t mbx[8]; 3578 uint32_t count; 3579 } aenfx; 3580 struct { 3581 srb_t *sp; 3582 } iosb; 3583 struct { 3584 port_id_t id; 3585 u8 port_name[8]; 3586 u8 node_name[8]; 3587 void *pla; 3588 u8 fc4_type; 3589 } new_sess; 3590 struct { /*Get PDB, Get Speed, update fcport, gnl */ 3591 fc_port_t *fcport; 3592 u8 opt; 3593 } fcport; 3594 struct { 3595 fc_port_t *fcport; 3596 u8 iocb[IOCB_SIZE]; 3597 int type; 3598 } nack; 3599 struct { 3600 u8 fc4_type; 3601 srb_t *sp; 3602 } gpnft; 3603 struct { 3604 struct edif_sa_ctl *sa_ctl; 3605 fc_port_t *fcport; 3606 uint16_t nport_handle; 3607 } sa_update; 3608 } u; 3609 }; 3610 3611 struct qla_chip_state_84xx { 3612 struct list_head list; 3613 struct kref kref; 3614 3615 void *bus; 3616 spinlock_t access_lock; 3617 struct mutex fw_update_mutex; 3618 uint32_t fw_update; 3619 uint32_t op_fw_version; 3620 uint32_t op_fw_size; 3621 uint32_t op_fw_seq_size; 3622 uint32_t diag_fw_version; 3623 uint32_t gold_fw_version; 3624 }; 3625 3626 struct qla_dif_statistics { 3627 uint64_t dif_input_bytes; 3628 uint64_t dif_output_bytes; 3629 uint64_t dif_input_requests; 3630 uint64_t dif_output_requests; 3631 uint32_t dif_guard_err; 3632 uint32_t dif_ref_tag_err; 3633 uint32_t dif_app_tag_err; 3634 }; 3635 3636 struct qla_statistics { 3637 uint32_t total_isp_aborts; 3638 uint64_t input_bytes; 3639 uint64_t output_bytes; 3640 uint64_t input_requests; 3641 uint64_t output_requests; 3642 uint32_t control_requests; 3643 3644 uint64_t jiffies_at_last_reset; 3645 uint32_t stat_max_pend_cmds; 3646 uint32_t stat_max_qfull_cmds_alloc; 3647 uint32_t stat_max_qfull_cmds_dropped; 3648 3649 struct qla_dif_statistics qla_dif_stats; 3650 }; 3651 3652 struct bidi_statistics { 3653 unsigned long long io_count; 3654 unsigned long long transfer_bytes; 3655 }; 3656 3657 struct qla_tc_param { 3658 struct scsi_qla_host *vha; 3659 uint32_t blk_sz; 3660 uint32_t bufflen; 3661 struct scatterlist *sg; 3662 struct scatterlist *prot_sg; 3663 struct crc_context *ctx; 3664 uint8_t *ctx_dsd_alloced; 3665 }; 3666 3667 /* Multi queue support */ 3668 #define MBC_INITIALIZE_MULTIQ 0x1f 3669 #define QLA_QUE_PAGE 0X1000 3670 #define QLA_MQ_SIZE 32 3671 #define QLA_MAX_QUEUES 256 3672 #define ISP_QUE_REG(ha, id) \ 3673 ((ha->mqenable || IS_QLA83XX(ha) || \ 3674 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3675 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3676 ((void __iomem *)ha->iobase)) 3677 #define QLA_REQ_QUE_ID(tag) \ 3678 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3679 #define QLA_DEFAULT_QUE_QOS 5 3680 #define QLA_PRECONFIG_VPORTS 32 3681 #define QLA_MAX_VPORTS_QLA24XX 128 3682 #define QLA_MAX_VPORTS_QLA25XX 256 3683 3684 struct qla_tgt_counters { 3685 uint64_t qla_core_sbt_cmd; 3686 uint64_t core_qla_que_buf; 3687 uint64_t qla_core_ret_ctio; 3688 uint64_t core_qla_snd_status; 3689 uint64_t qla_core_ret_sta_ctio; 3690 uint64_t core_qla_free_cmd; 3691 uint64_t num_q_full_sent; 3692 uint64_t num_alloc_iocb_failed; 3693 uint64_t num_term_xchg_sent; 3694 }; 3695 3696 struct qla_counters { 3697 uint64_t input_bytes; 3698 uint64_t input_requests; 3699 uint64_t output_bytes; 3700 uint64_t output_requests; 3701 3702 }; 3703 3704 struct qla_qpair; 3705 3706 /* Response queue data structure */ 3707 struct rsp_que { 3708 dma_addr_t dma; 3709 response_t *ring; 3710 response_t *ring_ptr; 3711 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */ 3712 __le32 __iomem *rsp_q_out; 3713 uint16_t ring_index; 3714 uint16_t out_ptr; 3715 uint16_t *in_ptr; /* queue shadow in index */ 3716 uint16_t length; 3717 uint16_t options; 3718 uint16_t rid; 3719 uint16_t id; 3720 uint16_t vp_idx; 3721 struct qla_hw_data *hw; 3722 struct qla_msix_entry *msix; 3723 struct req_que *req; 3724 srb_t *status_srb; /* status continuation entry */ 3725 struct qla_qpair *qpair; 3726 3727 dma_addr_t dma_fx00; 3728 response_t *ring_fx00; 3729 uint16_t length_fx00; 3730 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3731 }; 3732 3733 /* Request queue data structure */ 3734 struct req_que { 3735 dma_addr_t dma; 3736 request_t *ring; 3737 request_t *ring_ptr; 3738 __le32 __iomem *req_q_in; /* FWI2-capable only. */ 3739 __le32 __iomem *req_q_out; 3740 uint16_t ring_index; 3741 uint16_t in_ptr; 3742 uint16_t *out_ptr; /* queue shadow out index */ 3743 uint16_t cnt; 3744 uint16_t length; 3745 uint16_t options; 3746 uint16_t rid; 3747 uint16_t id; 3748 uint16_t qos; 3749 uint16_t vp_idx; 3750 struct rsp_que *rsp; 3751 srb_t **outstanding_cmds; 3752 uint32_t current_outstanding_cmd; 3753 uint16_t num_outstanding_cmds; 3754 int max_q_depth; 3755 3756 dma_addr_t dma_fx00; 3757 request_t *ring_fx00; 3758 uint16_t length_fx00; 3759 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3760 }; 3761 3762 struct qla_fw_resources { 3763 u16 iocbs_total; 3764 u16 iocbs_limit; 3765 u16 iocbs_qp_limit; 3766 u16 iocbs_used; 3767 u16 exch_total; 3768 u16 exch_limit; 3769 u16 exch_used; 3770 u16 pad; 3771 }; 3772 3773 struct qla_fw_res { 3774 u16 iocb_total; 3775 u16 iocb_limit; 3776 atomic_t iocb_used; 3777 3778 u16 exch_total; 3779 u16 exch_limit; 3780 atomic_t exch_used; 3781 }; 3782 3783 #define QLA_IOCB_PCT_LIMIT 95 3784 3785 struct qla_buf_pool { 3786 u16 num_bufs; 3787 u16 num_active; 3788 u16 max_used; 3789 u16 num_alloc; 3790 u16 prev_max; 3791 u16 pad; 3792 uint32_t take_snapshot:1; 3793 unsigned long *buf_map; 3794 void **buf_array; 3795 dma_addr_t *dma_array; 3796 }; 3797 3798 /*Queue pair data structure */ 3799 struct qla_qpair { 3800 spinlock_t qp_lock; 3801 atomic_t ref_count; 3802 uint32_t lun_cnt; 3803 /* 3804 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3805 * legacy code. For other Qpair(s), it will point at qp_lock. 3806 */ 3807 spinlock_t *qp_lock_ptr; 3808 struct scsi_qla_host *vha; 3809 u32 chip_reset; 3810 3811 /* distill these fields down to 'online=0/1' 3812 * ha->flags.eeh_busy 3813 * ha->flags.pci_channel_io_perm_failure 3814 * base_vha->loop_state 3815 */ 3816 uint32_t online:1; 3817 /* move vha->flags.difdix_supported here */ 3818 uint32_t difdix_supported:1; 3819 uint32_t delete_in_progress:1; 3820 uint32_t fw_started:1; 3821 uint32_t enable_class_2:1; 3822 uint32_t enable_explicit_conf:1; 3823 uint32_t use_shadow_reg:1; 3824 uint32_t rcv_intr:1; 3825 3826 uint16_t id; /* qp number used with FW */ 3827 uint16_t vp_idx; /* vport ID */ 3828 3829 uint16_t dsd_inuse; 3830 uint16_t dsd_avail; 3831 struct list_head dsd_list; 3832 #define NUM_DSD_CHAIN 4096 3833 3834 mempool_t *srb_mempool; 3835 3836 struct pci_dev *pdev; 3837 void (*reqq_start_iocbs)(struct qla_qpair *); 3838 3839 /* to do: New driver: move queues to here instead of pointers */ 3840 struct req_que *req; 3841 struct rsp_que *rsp; 3842 struct atio_que *atio; 3843 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3844 struct qla_hw_data *hw; 3845 struct work_struct q_work; 3846 struct qla_counters counters; 3847 3848 struct list_head qp_list_elem; /* vha->qp_list */ 3849 struct list_head hints_list; 3850 3851 uint16_t retry_term_cnt; 3852 __le32 retry_term_exchg_addr; 3853 uint64_t retry_term_jiff; 3854 struct qla_tgt_counters tgt_counters; 3855 uint16_t cpuid; 3856 bool cpu_mapped; 3857 struct qla_fw_resources fwres ____cacheline_aligned; 3858 struct qla_buf_pool buf_pool; 3859 u32 cmd_cnt; 3860 u32 cmd_completion_cnt; 3861 u32 prev_completion_cnt; 3862 }; 3863 3864 /* Place holder for FW buffer parameters */ 3865 struct qlfc_fw { 3866 void *fw_buf; 3867 dma_addr_t fw_dma; 3868 uint32_t len; 3869 }; 3870 3871 struct rdp_req_payload { 3872 uint32_t els_request; 3873 uint32_t desc_list_len; 3874 3875 /* NPIV descriptor */ 3876 struct { 3877 uint32_t desc_tag; 3878 uint32_t desc_len; 3879 uint8_t reserved; 3880 uint8_t nport_id[3]; 3881 } npiv_desc; 3882 }; 3883 3884 struct rdp_rsp_payload { 3885 struct { 3886 __be32 cmd; 3887 __be32 len; 3888 } hdr; 3889 3890 /* LS Request Info descriptor */ 3891 struct { 3892 __be32 desc_tag; 3893 __be32 desc_len; 3894 __be32 req_payload_word_0; 3895 } ls_req_info_desc; 3896 3897 /* LS Request Info descriptor */ 3898 struct { 3899 __be32 desc_tag; 3900 __be32 desc_len; 3901 __be32 req_payload_word_0; 3902 } ls_req_info_desc2; 3903 3904 /* SFP diagnostic param descriptor */ 3905 struct { 3906 __be32 desc_tag; 3907 __be32 desc_len; 3908 __be16 temperature; 3909 __be16 vcc; 3910 __be16 tx_bias; 3911 __be16 tx_power; 3912 __be16 rx_power; 3913 __be16 sfp_flags; 3914 } sfp_diag_desc; 3915 3916 /* Port Speed Descriptor */ 3917 struct { 3918 __be32 desc_tag; 3919 __be32 desc_len; 3920 __be16 speed_capab; 3921 __be16 operating_speed; 3922 } port_speed_desc; 3923 3924 /* Link Error Status Descriptor */ 3925 struct { 3926 __be32 desc_tag; 3927 __be32 desc_len; 3928 __be32 link_fail_cnt; 3929 __be32 loss_sync_cnt; 3930 __be32 loss_sig_cnt; 3931 __be32 prim_seq_err_cnt; 3932 __be32 inval_xmit_word_cnt; 3933 __be32 inval_crc_cnt; 3934 uint8_t pn_port_phy_type; 3935 uint8_t reserved[3]; 3936 } ls_err_desc; 3937 3938 /* Port name description with diag param */ 3939 struct { 3940 __be32 desc_tag; 3941 __be32 desc_len; 3942 uint8_t WWNN[WWN_SIZE]; 3943 uint8_t WWPN[WWN_SIZE]; 3944 } port_name_diag_desc; 3945 3946 /* Port Name desc for Direct attached Fx_Port or Nx_Port */ 3947 struct { 3948 __be32 desc_tag; 3949 __be32 desc_len; 3950 uint8_t WWNN[WWN_SIZE]; 3951 uint8_t WWPN[WWN_SIZE]; 3952 } port_name_direct_desc; 3953 3954 /* Buffer Credit descriptor */ 3955 struct { 3956 __be32 desc_tag; 3957 __be32 desc_len; 3958 __be32 fcport_b2b; 3959 __be32 attached_fcport_b2b; 3960 __be32 fcport_rtt; 3961 } buffer_credit_desc; 3962 3963 /* Optical Element Data Descriptor */ 3964 struct { 3965 __be32 desc_tag; 3966 __be32 desc_len; 3967 __be16 high_alarm; 3968 __be16 low_alarm; 3969 __be16 high_warn; 3970 __be16 low_warn; 3971 __be32 element_flags; 3972 } optical_elmt_desc[5]; 3973 3974 /* Optical Product Data Descriptor */ 3975 struct { 3976 __be32 desc_tag; 3977 __be32 desc_len; 3978 uint8_t vendor_name[16]; 3979 uint8_t part_number[16]; 3980 uint8_t serial_number[16]; 3981 uint8_t revision[4]; 3982 uint8_t date[8]; 3983 } optical_prod_desc; 3984 }; 3985 3986 #define RDP_DESC_LEN(obj) \ 3987 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len)) 3988 3989 #define RDP_PORT_SPEED_1GB BIT_15 3990 #define RDP_PORT_SPEED_2GB BIT_14 3991 #define RDP_PORT_SPEED_4GB BIT_13 3992 #define RDP_PORT_SPEED_10GB BIT_12 3993 #define RDP_PORT_SPEED_8GB BIT_11 3994 #define RDP_PORT_SPEED_16GB BIT_10 3995 #define RDP_PORT_SPEED_32GB BIT_9 3996 #define RDP_PORT_SPEED_64GB BIT_8 3997 #define RDP_PORT_SPEED_UNKNOWN BIT_0 3998 3999 struct scsi_qlt_host { 4000 void *target_lport_ptr; 4001 struct mutex tgt_mutex; 4002 struct mutex tgt_host_action_mutex; 4003 struct qla_tgt *qla_tgt; 4004 }; 4005 4006 struct qlt_hw_data { 4007 /* Protected by hw lock */ 4008 uint32_t node_name_set:1; 4009 4010 dma_addr_t atio_dma; /* Physical address. */ 4011 struct atio *atio_ring; /* Base virtual address */ 4012 struct atio *atio_ring_ptr; /* Current address. */ 4013 uint16_t atio_ring_index; /* Current index. */ 4014 uint16_t atio_q_length; 4015 __le32 __iomem *atio_q_in; 4016 __le32 __iomem *atio_q_out; 4017 4018 const struct qla_tgt_func_tmpl *tgt_ops; 4019 4020 int saved_set; 4021 __le16 saved_exchange_count; 4022 __le32 saved_firmware_options_1; 4023 __le32 saved_firmware_options_2; 4024 __le32 saved_firmware_options_3; 4025 uint8_t saved_firmware_options[2]; 4026 uint8_t saved_add_firmware_options[2]; 4027 4028 uint8_t tgt_node_name[WWN_SIZE]; 4029 4030 struct dentry *dfs_tgt_sess; 4031 struct dentry *dfs_tgt_port_database; 4032 struct dentry *dfs_naqp; 4033 4034 struct list_head q_full_list; 4035 uint32_t num_pend_cmds; 4036 uint32_t num_qfull_cmds_alloc; 4037 uint32_t num_qfull_cmds_dropped; 4038 spinlock_t q_full_lock; 4039 uint32_t leak_exchg_thresh_hold; 4040 spinlock_t sess_lock; 4041 int num_act_qpairs; 4042 #define DEFAULT_NAQP 2 4043 spinlock_t atio_lock ____cacheline_aligned; 4044 }; 4045 4046 #define MAX_QFULL_CMDS_ALLOC 8192 4047 #define Q_FULL_THRESH_HOLD_PERCENT 90 4048 #define Q_FULL_THRESH_HOLD(ha) \ 4049 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 4050 4051 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 4052 4053 struct qla_hw_data_stat { 4054 u32 num_fw_dump; 4055 u32 num_mpi_reset; 4056 }; 4057 4058 /* refer to pcie_do_recovery reference */ 4059 typedef enum { 4060 QLA_PCI_RESUME, 4061 QLA_PCI_ERR_DETECTED, 4062 QLA_PCI_MMIO_ENABLED, 4063 QLA_PCI_SLOT_RESET, 4064 } pci_error_state_t; 4065 /* 4066 * Qlogic host adapter specific data structure. 4067 */ 4068 struct qla_hw_data { 4069 struct pci_dev *pdev; 4070 /* SRB cache. */ 4071 #define SRB_MIN_REQ 128 4072 mempool_t *srb_mempool; 4073 u8 port_name[WWN_SIZE]; 4074 4075 volatile struct { 4076 uint32_t mbox_int :1; 4077 uint32_t mbox_busy :1; 4078 uint32_t disable_risc_code_load :1; 4079 uint32_t enable_64bit_addressing :1; 4080 uint32_t enable_lip_reset :1; 4081 uint32_t enable_target_reset :1; 4082 uint32_t enable_lip_full_login :1; 4083 uint32_t enable_led_scheme :1; 4084 4085 uint32_t msi_enabled :1; 4086 uint32_t msix_enabled :1; 4087 uint32_t disable_serdes :1; 4088 uint32_t gpsc_supported :1; 4089 uint32_t npiv_supported :1; 4090 uint32_t pci_channel_io_perm_failure :1; 4091 uint32_t fce_enabled :1; 4092 uint32_t fac_supported :1; 4093 4094 uint32_t chip_reset_done :1; 4095 uint32_t running_gold_fw :1; 4096 uint32_t eeh_busy :1; 4097 uint32_t disable_msix_handshake :1; 4098 uint32_t fcp_prio_enabled :1; 4099 uint32_t isp82xx_fw_hung:1; 4100 uint32_t nic_core_hung:1; 4101 4102 uint32_t quiesce_owner:1; 4103 uint32_t nic_core_reset_hdlr_active:1; 4104 uint32_t nic_core_reset_owner:1; 4105 uint32_t isp82xx_no_md_cap:1; 4106 uint32_t host_shutting_down:1; 4107 uint32_t idc_compl_status:1; 4108 uint32_t mr_reset_hdlr_active:1; 4109 uint32_t mr_intr_valid:1; 4110 4111 uint32_t dport_enabled:1; 4112 uint32_t fawwpn_enabled:1; 4113 uint32_t exlogins_enabled:1; 4114 uint32_t exchoffld_enabled:1; 4115 4116 uint32_t lip_ae:1; 4117 uint32_t n2n_ae:1; 4118 uint32_t fw_started:1; 4119 uint32_t fw_init_done:1; 4120 4121 uint32_t lr_detected:1; 4122 4123 uint32_t rida_fmt2:1; 4124 uint32_t purge_mbox:1; 4125 uint32_t n2n_bigger:1; 4126 uint32_t secure_adapter:1; 4127 uint32_t secure_fw:1; 4128 /* Supported by Adapter */ 4129 uint32_t scm_supported_a:1; 4130 /* Supported by Firmware */ 4131 uint32_t scm_supported_f:1; 4132 /* Enabled in Driver */ 4133 uint32_t scm_enabled:1; 4134 uint32_t edif_hw:1; 4135 uint32_t edif_enabled:1; 4136 uint32_t n2n_fw_acc_sec:1; 4137 uint32_t plogi_template_valid:1; 4138 uint32_t port_isolated:1; 4139 uint32_t eeh_flush:2; 4140 #define EEH_FLUSH_RDY 1 4141 #define EEH_FLUSH_DONE 2 4142 } flags; 4143 4144 uint16_t max_exchg; 4145 uint16_t lr_distance; /* 32G & above */ 4146 #define LR_DISTANCE_5K 1 4147 #define LR_DISTANCE_10K 0 4148 4149 /* This spinlock is used to protect "io transactions", you must 4150 * acquire it before doing any IO to the card, eg with RD_REG*() and 4151 * WRT_REG*() for the duration of your entire commandtransaction. 4152 * 4153 * This spinlock is of lower priority than the io request lock. 4154 */ 4155 4156 spinlock_t hardware_lock ____cacheline_aligned; 4157 int bars; 4158 int mem_only; 4159 device_reg_t *iobase; /* Base I/O address */ 4160 resource_size_t pio_address; 4161 4162 #define MIN_IOBASE_LEN 0x100 4163 dma_addr_t bar0_hdl; 4164 4165 void __iomem *cregbase; 4166 dma_addr_t bar2_hdl; 4167 #define BAR0_LEN_FX00 (1024 * 1024) 4168 #define BAR2_LEN_FX00 (128 * 1024) 4169 4170 uint32_t rqstq_intr_code; 4171 uint32_t mbx_intr_code; 4172 uint32_t req_que_len; 4173 uint32_t rsp_que_len; 4174 uint32_t req_que_off; 4175 uint32_t rsp_que_off; 4176 unsigned long eeh_jif; 4177 4178 /* Multi queue data structs */ 4179 device_reg_t *mqiobase; 4180 device_reg_t *msixbase; 4181 uint16_t msix_count; 4182 uint8_t mqenable; 4183 struct req_que **req_q_map; 4184 struct rsp_que **rsp_q_map; 4185 struct qla_qpair **queue_pair_map; 4186 struct qla_qpair **qp_cpu_map; 4187 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4188 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4189 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 4190 / sizeof(unsigned long)]; 4191 uint8_t max_req_queues; 4192 uint8_t max_rsp_queues; 4193 uint8_t max_qpairs; 4194 uint8_t num_qpairs; 4195 struct qla_qpair *base_qpair; 4196 struct qla_npiv_entry *npiv_info; 4197 uint16_t nvram_npiv_size; 4198 4199 uint16_t switch_cap; 4200 #define FLOGI_SEQ_DEL BIT_8 4201 #define FLOGI_MID_SUPPORT BIT_10 4202 #define FLOGI_VSAN_SUPPORT BIT_12 4203 #define FLOGI_SP_SUPPORT BIT_13 4204 4205 uint8_t port_no; /* Physical port of adapter */ 4206 uint8_t exch_starvation; 4207 4208 /* Timeout timers. */ 4209 uint8_t loop_down_abort_time; /* port down timer */ 4210 atomic_t loop_down_timer; /* loop down timer */ 4211 uint8_t link_down_timeout; /* link down timeout */ 4212 uint16_t max_loop_id; 4213 uint16_t max_fibre_devices; /* Maximum number of targets */ 4214 4215 uint16_t fb_rev; 4216 uint16_t min_external_loopid; /* First external loop Id */ 4217 4218 #define PORT_SPEED_UNKNOWN 0xFFFF 4219 #define PORT_SPEED_1GB 0x00 4220 #define PORT_SPEED_2GB 0x01 4221 #define PORT_SPEED_AUTO 0x02 4222 #define PORT_SPEED_4GB 0x03 4223 #define PORT_SPEED_8GB 0x04 4224 #define PORT_SPEED_16GB 0x05 4225 #define PORT_SPEED_32GB 0x06 4226 #define PORT_SPEED_64GB 0x07 4227 #define PORT_SPEED_10GB 0x13 4228 uint16_t link_data_rate; /* F/W operating speed */ 4229 uint16_t set_data_rate; /* Set by user */ 4230 4231 uint8_t current_topology; 4232 uint8_t prev_topology; 4233 #define ISP_CFG_NL 1 4234 #define ISP_CFG_N 2 4235 #define ISP_CFG_FL 4 4236 #define ISP_CFG_F 8 4237 4238 uint8_t operating_mode; /* F/W operating mode */ 4239 #define LOOP 0 4240 #define P2P 1 4241 #define LOOP_P2P 2 4242 #define P2P_LOOP 3 4243 uint8_t interrupts_on; 4244 uint32_t isp_abort_cnt; 4245 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 4246 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 4247 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 4248 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 4249 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 4250 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 4251 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 4252 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 4253 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 4254 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 4255 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 4256 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 4257 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 4258 4259 uint32_t isp_type; 4260 #define DT_ISP2100 BIT_0 4261 #define DT_ISP2200 BIT_1 4262 #define DT_ISP2300 BIT_2 4263 #define DT_ISP2312 BIT_3 4264 #define DT_ISP2322 BIT_4 4265 #define DT_ISP6312 BIT_5 4266 #define DT_ISP6322 BIT_6 4267 #define DT_ISP2422 BIT_7 4268 #define DT_ISP2432 BIT_8 4269 #define DT_ISP5422 BIT_9 4270 #define DT_ISP5432 BIT_10 4271 #define DT_ISP2532 BIT_11 4272 #define DT_ISP8432 BIT_12 4273 #define DT_ISP8001 BIT_13 4274 #define DT_ISP8021 BIT_14 4275 #define DT_ISP2031 BIT_15 4276 #define DT_ISP8031 BIT_16 4277 #define DT_ISPFX00 BIT_17 4278 #define DT_ISP8044 BIT_18 4279 #define DT_ISP2071 BIT_19 4280 #define DT_ISP2271 BIT_20 4281 #define DT_ISP2261 BIT_21 4282 #define DT_ISP2061 BIT_22 4283 #define DT_ISP2081 BIT_23 4284 #define DT_ISP2089 BIT_24 4285 #define DT_ISP2281 BIT_25 4286 #define DT_ISP2289 BIT_26 4287 #define DT_ISP_LAST (DT_ISP2289 << 1) 4288 4289 uint32_t device_type; 4290 #define DT_T10_PI BIT_25 4291 #define DT_IIDMA BIT_26 4292 #define DT_FWI2 BIT_27 4293 #define DT_ZIO_SUPPORTED BIT_28 4294 #define DT_OEM_001 BIT_29 4295 #define DT_ISP2200A BIT_30 4296 #define DT_EXTENDED_IDS BIT_31 4297 4298 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 4299 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 4300 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 4301 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 4302 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 4303 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 4304 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 4305 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 4306 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 4307 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 4308 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 4309 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 4310 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 4311 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 4312 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 4313 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 4314 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 4315 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 4316 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 4317 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 4318 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 4319 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 4320 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 4321 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 4322 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 4323 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 4324 4325 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 4326 IS_QLA6312(ha) || IS_QLA6322(ha)) 4327 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 4328 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 4329 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 4330 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 4331 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 4332 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 4333 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 4334 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 4335 IS_QLA84XX(ha)) 4336 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 4337 IS_QLA8031(ha) || IS_QLA8044(ha)) 4338 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 4339 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 4340 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 4341 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 4342 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 4343 IS_QLA28XX(ha)) 4344 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4345 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4346 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 4347 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4348 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4349 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4350 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4351 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 4352 4353 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 4354 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 4355 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 4356 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 4357 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 4358 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 4359 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 4360 #define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4361 IS_QLA28XX(ha)) 4362 #define IS_BIDI_CAPABLE(ha) \ 4363 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4364 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 4365 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 4366 ((ha)->fw_attributes_ext[0] & BIT_0)) 4367 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14) 4368 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS) 4369 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD) 4370 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp)) 4371 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \ 4372 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4373 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \ 4374 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4375 #define QLA_ABTS_WAIT_ENABLED(_sp) \ 4376 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4377 4378 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4379 IS_QLA28XX(ha)) 4380 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4381 IS_QLA28XX(ha)) 4382 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 4383 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4384 IS_QLA28XX(ha)) 4385 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 4386 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 4387 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4388 IS_QLA28XX(ha)) 4389 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 4390 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4391 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4392 IS_QLA28XX(ha)) 4393 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4394 IS_QLA28XX(ha)) 4395 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 4396 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4397 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 4398 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4399 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4400 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 4401 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4402 4403 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \ 4404 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\ 4405 (ha->zio_mode == QLA_ZIO_MODE_6)) 4406 4407 /* HBA serial number */ 4408 uint8_t serial0; 4409 uint8_t serial1; 4410 uint8_t serial2; 4411 4412 /* NVRAM configuration data */ 4413 #define MAX_NVRAM_SIZE 4096 4414 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 4415 uint16_t nvram_size; 4416 uint16_t nvram_base; 4417 void *nvram; 4418 uint16_t vpd_size; 4419 uint16_t vpd_base; 4420 void *vpd; 4421 4422 uint16_t loop_reset_delay; 4423 uint8_t retry_count; 4424 uint8_t login_timeout; 4425 uint16_t r_a_tov; 4426 int port_down_retry_count; 4427 uint8_t mbx_count; 4428 uint8_t aen_mbx_count; 4429 atomic_t num_pend_mbx_stage1; 4430 atomic_t num_pend_mbx_stage2; 4431 uint16_t frame_payload_size; 4432 4433 uint32_t login_retry_count; 4434 /* SNS command interfaces. */ 4435 ms_iocb_entry_t *ms_iocb; 4436 dma_addr_t ms_iocb_dma; 4437 struct ct_sns_pkt *ct_sns; 4438 dma_addr_t ct_sns_dma; 4439 /* SNS command interfaces for 2200. */ 4440 struct sns_cmd_pkt *sns_cmd; 4441 dma_addr_t sns_cmd_dma; 4442 4443 #define SFP_DEV_SIZE 512 4444 #define SFP_BLOCK_SIZE 64 4445 #define SFP_RTDI_LEN SFP_BLOCK_SIZE 4446 4447 void *sfp_data; 4448 dma_addr_t sfp_data_dma; 4449 4450 struct qla_flt_header *flt; 4451 dma_addr_t flt_dma; 4452 4453 #define XGMAC_DATA_SIZE 4096 4454 void *xgmac_data; 4455 dma_addr_t xgmac_data_dma; 4456 4457 #define DCBX_TLV_DATA_SIZE 4096 4458 void *dcbx_tlv; 4459 dma_addr_t dcbx_tlv_dma; 4460 4461 struct task_struct *dpc_thread; 4462 uint8_t dpc_active; /* DPC routine is active */ 4463 4464 dma_addr_t gid_list_dma; 4465 struct gid_list_info *gid_list; 4466 int gid_list_info_size; 4467 4468 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 4469 #define DMA_POOL_SIZE 256 4470 struct dma_pool *s_dma_pool; 4471 4472 dma_addr_t init_cb_dma; 4473 init_cb_t *init_cb; 4474 int init_cb_size; 4475 dma_addr_t ex_init_cb_dma; 4476 struct ex_init_cb_81xx *ex_init_cb; 4477 dma_addr_t sf_init_cb_dma; 4478 struct init_sf_cb *sf_init_cb; 4479 4480 void *scm_fpin_els_buff; 4481 uint64_t scm_fpin_els_buff_size; 4482 bool scm_fpin_valid; 4483 bool scm_fpin_payload_size; 4484 4485 void *async_pd; 4486 dma_addr_t async_pd_dma; 4487 4488 #define ENABLE_EXTENDED_LOGIN BIT_7 4489 4490 /* Extended Logins */ 4491 void *exlogin_buf; 4492 dma_addr_t exlogin_buf_dma; 4493 uint32_t exlogin_size; 4494 4495 #define ENABLE_EXCHANGE_OFFLD BIT_2 4496 4497 /* Exchange Offload */ 4498 void *exchoffld_buf; 4499 dma_addr_t exchoffld_buf_dma; 4500 int exchoffld_size; 4501 int exchoffld_count; 4502 4503 /* n2n */ 4504 struct fc_els_flogi plogi_els_payld; 4505 4506 void *swl; 4507 4508 /* These are used by mailbox operations. */ 4509 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 4510 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4511 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4512 4513 mbx_cmd_t *mcp; 4514 struct mbx_cmd_32 *mcp32; 4515 4516 unsigned long mbx_cmd_flags; 4517 #define MBX_INTERRUPT 1 4518 #define MBX_INTR_WAIT 2 4519 #define MBX_UPDATE_FLASH_ACTIVE 3 4520 4521 struct mutex vport_lock; /* Virtual port synchronization */ 4522 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4523 struct mutex mq_lock; /* multi-queue synchronization */ 4524 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4525 struct completion mbx_intr_comp; /* Used for completion notification */ 4526 struct completion dcbx_comp; /* For set port config notification */ 4527 struct completion lb_portup_comp; /* Used to wait for link up during 4528 * loopback */ 4529 #define DCBX_COMP_TIMEOUT 20 4530 #define LB_PORTUP_COMP_TIMEOUT 10 4531 4532 int notify_dcbx_comp; 4533 int notify_lb_portup_comp; 4534 struct mutex selflogin_lock; 4535 4536 /* Basic firmware related information. */ 4537 uint16_t fw_major_version; 4538 uint16_t fw_minor_version; 4539 uint16_t fw_subminor_version; 4540 uint16_t fw_attributes; 4541 uint16_t fw_attributes_h; 4542 #define FW_ATTR_H_NVME_FBURST BIT_1 4543 #define FW_ATTR_H_NVME BIT_10 4544 #define FW_ATTR_H_NVME_UPDATED BIT_14 4545 4546 /* About firmware SCM support */ 4547 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12 4548 /* Brocade fabric attached */ 4549 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000 4550 /* Cisco fabric attached */ 4551 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000 4552 #define FW_ATTR_EXT0_NVME2 BIT_13 4553 #define FW_ATTR_EXT0_EDIF BIT_5 4554 uint16_t fw_attributes_ext[2]; 4555 uint32_t fw_memory_size; 4556 uint32_t fw_transfer_size; 4557 uint32_t fw_srisc_address; 4558 #define RISC_START_ADDRESS_2100 0x1000 4559 #define RISC_START_ADDRESS_2300 0x800 4560 #define RISC_START_ADDRESS_2400 0x100000 4561 4562 uint16_t orig_fw_tgt_xcb_count; 4563 uint16_t cur_fw_tgt_xcb_count; 4564 uint16_t orig_fw_xcb_count; 4565 uint16_t cur_fw_xcb_count; 4566 uint16_t orig_fw_iocb_count; 4567 uint16_t cur_fw_iocb_count; 4568 uint16_t fw_max_fcf_count; 4569 4570 uint32_t fw_shared_ram_start; 4571 uint32_t fw_shared_ram_end; 4572 uint32_t fw_ddr_ram_start; 4573 uint32_t fw_ddr_ram_end; 4574 4575 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4576 uint8_t fw_seriallink_options[4]; 4577 __le16 fw_seriallink_options24[4]; 4578 4579 uint8_t serdes_version[3]; 4580 uint8_t mpi_version[3]; 4581 uint32_t mpi_capabilities; 4582 uint8_t phy_version[3]; 4583 uint8_t pep_version[3]; 4584 4585 /* Firmware dump template */ 4586 struct fwdt { 4587 void *template; 4588 ulong length; 4589 ulong dump_size; 4590 } fwdt[2]; 4591 struct qla2xxx_fw_dump *fw_dump; 4592 uint32_t fw_dump_len; 4593 u32 fw_dump_alloc_len; 4594 bool fw_dumped; 4595 unsigned long fw_dump_cap_flags; 4596 #define RISC_PAUSE_CMPL 0 4597 #define DMA_SHUTDOWN_CMPL 1 4598 #define ISP_RESET_CMPL 2 4599 #define RISC_RDY_AFT_RESET 3 4600 #define RISC_SRAM_DUMP_CMPL 4 4601 #define RISC_EXT_MEM_DUMP_CMPL 5 4602 #define ISP_MBX_RDY 6 4603 #define ISP_SOFT_RESET_CMPL 7 4604 int fw_dump_reading; 4605 void *mpi_fw_dump; 4606 u32 mpi_fw_dump_len; 4607 unsigned int mpi_fw_dump_reading:1; 4608 unsigned int mpi_fw_dumped:1; 4609 int prev_minidump_failed; 4610 dma_addr_t eft_dma; 4611 void *eft; 4612 /* Current size of mctp dump is 0x086064 bytes */ 4613 #define MCTP_DUMP_SIZE 0x086064 4614 dma_addr_t mctp_dump_dma; 4615 void *mctp_dump; 4616 int mctp_dumped; 4617 int mctp_dump_reading; 4618 uint32_t chain_offset; 4619 struct dentry *dfs_dir; 4620 struct dentry *dfs_fce; 4621 struct dentry *dfs_tgt_counters; 4622 struct dentry *dfs_fw_resource_cnt; 4623 4624 dma_addr_t fce_dma; 4625 void *fce; 4626 uint32_t fce_bufs; 4627 uint16_t fce_mb[8]; 4628 uint64_t fce_wr, fce_rd; 4629 struct mutex fce_mutex; 4630 4631 uint32_t pci_attr; 4632 uint16_t chip_revision; 4633 4634 uint16_t product_id[4]; 4635 4636 uint8_t model_number[16+1]; 4637 char model_desc[80]; 4638 uint8_t adapter_id[16+1]; 4639 4640 /* Option ROM information. */ 4641 char *optrom_buffer; 4642 uint32_t optrom_size; 4643 int optrom_state; 4644 #define QLA_SWAITING 0 4645 #define QLA_SREADING 1 4646 #define QLA_SWRITING 2 4647 uint32_t optrom_region_start; 4648 uint32_t optrom_region_size; 4649 struct mutex optrom_mutex; 4650 4651 /* PCI expansion ROM image information. */ 4652 #define ROM_CODE_TYPE_BIOS 0 4653 #define ROM_CODE_TYPE_FCODE 1 4654 #define ROM_CODE_TYPE_EFI 3 4655 uint8_t bios_revision[2]; 4656 uint8_t efi_revision[2]; 4657 uint8_t fcode_revision[16]; 4658 uint32_t fw_revision[4]; 4659 4660 uint32_t gold_fw_version[4]; 4661 4662 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4663 uint32_t flash_conf_off; 4664 uint32_t flash_data_off; 4665 uint32_t nvram_conf_off; 4666 uint32_t nvram_data_off; 4667 4668 uint32_t fdt_wrt_disable; 4669 uint32_t fdt_wrt_enable; 4670 uint32_t fdt_erase_cmd; 4671 uint32_t fdt_block_size; 4672 uint32_t fdt_unprotect_sec_cmd; 4673 uint32_t fdt_protect_sec_cmd; 4674 uint32_t fdt_wrt_sts_reg_cmd; 4675 4676 struct { 4677 uint32_t flt_region_flt; 4678 uint32_t flt_region_fdt; 4679 uint32_t flt_region_boot; 4680 uint32_t flt_region_boot_sec; 4681 uint32_t flt_region_fw; 4682 uint32_t flt_region_fw_sec; 4683 uint32_t flt_region_vpd_nvram; 4684 uint32_t flt_region_vpd_nvram_sec; 4685 uint32_t flt_region_vpd; 4686 uint32_t flt_region_vpd_sec; 4687 uint32_t flt_region_nvram; 4688 uint32_t flt_region_nvram_sec; 4689 uint32_t flt_region_npiv_conf; 4690 uint32_t flt_region_gold_fw; 4691 uint32_t flt_region_fcp_prio; 4692 uint32_t flt_region_bootload; 4693 uint32_t flt_region_img_status_pri; 4694 uint32_t flt_region_img_status_sec; 4695 uint32_t flt_region_aux_img_status_pri; 4696 uint32_t flt_region_aux_img_status_sec; 4697 }; 4698 uint8_t active_image; 4699 uint8_t active_tmf; 4700 #define MAX_ACTIVE_TMF 8 4701 4702 /* Needed for BEACON */ 4703 uint16_t beacon_blink_led; 4704 uint8_t beacon_color_state; 4705 #define QLA_LED_GRN_ON 0x01 4706 #define QLA_LED_YLW_ON 0x02 4707 #define QLA_LED_ABR_ON 0x04 4708 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4709 /* ISP2322: red, green, amber. */ 4710 uint16_t zio_mode; 4711 uint16_t zio_timer; 4712 4713 struct qla_msix_entry *msix_entries; 4714 4715 struct list_head tmf_pending; 4716 struct list_head tmf_active; 4717 struct list_head vp_list; /* list of VP */ 4718 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4719 sizeof(unsigned long)]; 4720 uint16_t num_vhosts; /* number of vports created */ 4721 uint16_t num_vsans; /* number of vsan created */ 4722 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4723 int cur_vport_count; 4724 4725 struct qla_chip_state_84xx *cs84xx; 4726 struct isp_operations *isp_ops; 4727 struct workqueue_struct *wq; 4728 struct work_struct heartbeat_work; 4729 struct qlfc_fw fw_buf; 4730 unsigned long last_heartbeat_run_jiffies; 4731 4732 /* FCP_CMND priority support */ 4733 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4734 4735 struct dma_pool *dl_dma_pool; 4736 #define DSD_LIST_DMA_POOL_SIZE 512 4737 4738 struct dma_pool *fcp_cmnd_dma_pool; 4739 mempool_t *ctx_mempool; 4740 #define FCP_CMND_DMA_POOL_SIZE 512 4741 4742 void __iomem *nx_pcibase; /* Base I/O address */ 4743 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4744 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4745 4746 uint32_t crb_win; 4747 uint32_t curr_window; 4748 uint32_t ddr_mn_window; 4749 unsigned long mn_win_crb; 4750 unsigned long ms_win_crb; 4751 int qdr_sn_window; 4752 uint32_t fcoe_dev_init_timeout; 4753 uint32_t fcoe_reset_timeout; 4754 rwlock_t hw_lock; 4755 uint16_t portnum; /* port number */ 4756 int link_width; 4757 struct fw_blob *hablob; 4758 struct qla82xx_legacy_intr_set nx_legacy_intr; 4759 4760 uint8_t fw_type; 4761 uint32_t file_prd_off; /* File firmware product offset */ 4762 4763 uint32_t md_template_size; 4764 void *md_tmplt_hdr; 4765 dma_addr_t md_tmplt_hdr_dma; 4766 void *md_dump; 4767 uint32_t md_dump_size; 4768 4769 void *loop_id_map; 4770 4771 /* QLA83XX IDC specific fields */ 4772 uint32_t idc_audit_ts; 4773 uint32_t idc_extend_tmo; 4774 4775 /* DPC low-priority workqueue */ 4776 struct workqueue_struct *dpc_lp_wq; 4777 struct work_struct idc_aen; 4778 /* DPC high-priority workqueue */ 4779 struct workqueue_struct *dpc_hp_wq; 4780 struct work_struct nic_core_reset; 4781 struct work_struct idc_state_handler; 4782 struct work_struct nic_core_unrecoverable; 4783 struct work_struct board_disable; 4784 4785 struct mr_data_fx00 mr; 4786 uint32_t chip_reset; 4787 4788 struct qlt_hw_data tgt; 4789 int allow_cna_fw_dump; 4790 uint32_t fw_ability_mask; 4791 uint16_t min_supported_speed; 4792 uint16_t max_supported_speed; 4793 4794 /* DMA pool for the DIF bundling buffers */ 4795 struct dma_pool *dif_bundl_pool; 4796 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4797 struct { 4798 struct { 4799 struct list_head head; 4800 uint count; 4801 } good; 4802 struct { 4803 struct list_head head; 4804 uint count; 4805 } unusable; 4806 } pool; 4807 4808 unsigned long long dif_bundle_crossed_pages; 4809 unsigned long long dif_bundle_reads; 4810 unsigned long long dif_bundle_writes; 4811 unsigned long long dif_bundle_kallocs; 4812 unsigned long long dif_bundle_dma_allocs; 4813 4814 atomic_t nvme_active_aen_cnt; 4815 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4816 4817 uint8_t fc4_type_priority; 4818 4819 atomic_t zio_threshold; 4820 uint16_t last_zio_threshold; 4821 4822 #define DEFAULT_ZIO_THRESHOLD 5 4823 4824 struct qla_hw_data_stat stat; 4825 pci_error_state_t pci_error_state; 4826 struct dma_pool *purex_dma_pool; 4827 struct btree_head32 host_map; 4828 4829 #define EDIF_NUM_SA_INDEX 512 4830 #define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX 4831 void *edif_rx_sa_id_map; 4832 void *edif_tx_sa_id_map; 4833 spinlock_t sadb_fp_lock; 4834 4835 struct list_head sadb_tx_index_list; 4836 struct list_head sadb_rx_index_list; 4837 spinlock_t sadb_lock; /* protects list */ 4838 struct els_reject elsrej; 4839 u8 edif_post_stop_cnt_down; 4840 struct qla_vp_map *vp_map; 4841 struct qla_nvme_fc_rjt lsrjt; 4842 struct qla_fw_res fwres ____cacheline_aligned; 4843 }; 4844 4845 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES)) 4846 4847 struct active_regions { 4848 uint8_t global; 4849 struct { 4850 uint8_t board_config; 4851 uint8_t vpd_nvram; 4852 uint8_t npiv_config_0_1; 4853 uint8_t npiv_config_2_3; 4854 uint8_t nvme_params; 4855 } aux; 4856 }; 4857 4858 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4859 #define FW_ABILITY_MAX_SPEED_16G 0x0 4860 #define FW_ABILITY_MAX_SPEED_32G 0x1 4861 #define FW_ABILITY_MAX_SPEED(ha) \ 4862 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4863 4864 #define QLA_GET_DATA_RATE 0 4865 #define QLA_SET_DATA_RATE_NOLR 1 4866 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4867 4868 #define QLA_DEFAULT_PAYLOAD_SIZE 64 4869 /* 4870 * This item might be allocated with a size > sizeof(struct purex_item). 4871 * The "size" variable gives the size of the payload (which 4872 * is variable) starting at "iocb". 4873 */ 4874 struct purex_item { 4875 void *purls_context; 4876 struct list_head list; 4877 struct scsi_qla_host *vha; 4878 void (*process_item)(struct scsi_qla_host *vha, 4879 struct purex_item *pkt); 4880 atomic_t in_use; 4881 uint16_t size; 4882 struct { 4883 uint8_t iocb[64]; 4884 } iocb; 4885 }; 4886 4887 #include "qla_edif.h" 4888 4889 #define SCM_FLAG_RDF_REJECT 0x00 4890 #define SCM_FLAG_RDF_COMPLETED 0x01 4891 4892 #define QLA_CON_PRIMITIVE_RECEIVED 0x1 4893 #define QLA_CONGESTION_ARB_WARNING 0x1 4894 #define QLA_CONGESTION_ARB_ALARM 0X2 4895 4896 /* 4897 * Qlogic scsi host structure 4898 */ 4899 typedef struct scsi_qla_host { 4900 struct list_head list; 4901 struct list_head vp_fcports; /* list of fcports */ 4902 struct list_head work_list; 4903 spinlock_t work_lock; 4904 struct work_struct iocb_work; 4905 4906 /* Commonly used flags and state information. */ 4907 struct Scsi_Host *host; 4908 unsigned long host_no; 4909 uint8_t host_str[16]; 4910 4911 volatile struct { 4912 uint32_t init_done :1; 4913 uint32_t online :1; 4914 uint32_t reset_active :1; 4915 4916 uint32_t management_server_logged_in :1; 4917 uint32_t process_response_queue :1; 4918 uint32_t difdix_supported:1; 4919 uint32_t delete_progress:1; 4920 4921 uint32_t fw_tgt_reported:1; 4922 uint32_t bbcr_enable:1; 4923 uint32_t qpairs_available:1; 4924 uint32_t qpairs_req_created:1; 4925 uint32_t qpairs_rsp_created:1; 4926 uint32_t nvme_enabled:1; 4927 uint32_t nvme_first_burst:1; 4928 uint32_t nvme2_enabled:1; 4929 } flags; 4930 4931 atomic_t loop_state; 4932 #define LOOP_TIMEOUT 1 4933 #define LOOP_DOWN 2 4934 #define LOOP_UP 3 4935 #define LOOP_UPDATE 4 4936 #define LOOP_READY 5 4937 #define LOOP_DEAD 6 4938 4939 unsigned long buf_expired; 4940 unsigned long relogin_jif; 4941 unsigned long dpc_flags; 4942 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4943 #define RESET_ACTIVE 1 4944 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4945 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4946 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4947 #define LOOP_RESYNC_ACTIVE 5 4948 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4949 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4950 #define RELOGIN_NEEDED 8 4951 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4952 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4953 #define BEACON_BLINK_NEEDED 11 4954 #define REGISTER_FDMI_NEEDED 12 4955 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4956 #define UNLOADING 15 4957 #define NPIV_CONFIG_NEEDED 16 4958 #define ISP_UNRECOVERABLE 17 4959 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4960 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4961 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4962 #define N2N_LINK_RESET 21 4963 #define PORT_UPDATE_NEEDED 22 4964 #define FX00_RESET_RECOVERY 23 4965 #define FX00_TARGET_SCAN 24 4966 #define FX00_CRITEMP_RECOVERY 25 4967 #define FX00_HOST_INFO_RESEND 26 4968 #define QPAIR_ONLINE_CHECK_NEEDED 27 4969 #define DO_EEH_RECOVERY 28 4970 #define DETECT_SFP_CHANGE 29 4971 #define N2N_LOGIN_NEEDED 30 4972 #define IOCB_WORK_ACTIVE 31 4973 #define SET_ZIO_THRESHOLD_NEEDED 32 4974 #define ISP_ABORT_TO_ROM 33 4975 #define VPORT_DELETE 34 4976 4977 #define PROCESS_PUREX_IOCB 63 4978 4979 unsigned long pci_flags; 4980 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4981 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4982 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4983 4984 uint32_t device_flags; 4985 #define SWITCH_FOUND BIT_0 4986 #define DFLG_NO_CABLE BIT_1 4987 #define DFLG_DEV_FAILED BIT_5 4988 4989 /* ISP configuration data. */ 4990 uint16_t loop_id; /* Host adapter loop id */ 4991 uint16_t self_login_loop_id; /* host adapter loop id 4992 * get it on self login 4993 */ 4994 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4995 * no need of allocating it for 4996 * each command 4997 */ 4998 4999 port_id_t d_id; /* Host adapter port id */ 5000 uint8_t marker_needed; 5001 uint16_t mgmt_svr_loop_id; 5002 5003 5004 5005 /* Timeout timers. */ 5006 uint8_t loop_down_abort_time; /* port down timer */ 5007 atomic_t loop_down_timer; /* loop down timer */ 5008 uint8_t link_down_timeout; /* link down timeout */ 5009 5010 uint32_t timer_active; 5011 struct timer_list timer; 5012 5013 uint8_t node_name[WWN_SIZE]; 5014 uint8_t port_name[WWN_SIZE]; 5015 uint8_t fabric_node_name[WWN_SIZE]; 5016 uint8_t fabric_port_name[WWN_SIZE]; 5017 5018 struct nvme_fc_local_port *nvme_local_port; 5019 struct completion nvme_del_done; 5020 5021 uint16_t fcoe_vlan_id; 5022 uint16_t fcoe_fcf_idx; 5023 uint8_t fcoe_vn_port_mac[6]; 5024 5025 /* list of commands waiting on workqueue */ 5026 struct list_head qla_cmd_list; 5027 struct list_head unknown_atio_list; 5028 spinlock_t cmd_list_lock; 5029 struct delayed_work unknown_atio_work; 5030 5031 /* Counter to detect races between ELS and RSCN events */ 5032 atomic_t generation_tick; 5033 /* Time when global fcport update has been scheduled */ 5034 int total_fcport_update_gen; 5035 /* List of pending LOGOs, protected by tgt_mutex */ 5036 struct list_head logo_list; 5037 /* List of pending PLOGI acks, protected by hw lock */ 5038 struct list_head plogi_ack_list; 5039 5040 struct list_head qp_list; 5041 5042 uint32_t vp_abort_cnt; 5043 5044 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 5045 uint16_t vp_idx; /* vport ID */ 5046 struct qla_qpair *qpair; /* base qpair */ 5047 5048 unsigned long vp_flags; 5049 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 5050 #define VP_CREATE_NEEDED 1 5051 #define VP_BIND_NEEDED 2 5052 #define VP_DELETE_NEEDED 3 5053 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 5054 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 5055 atomic_t vp_state; 5056 #define VP_OFFLINE 0 5057 #define VP_ACTIVE 1 5058 #define VP_FAILED 2 5059 // #define VP_DISABLE 3 5060 uint16_t vp_err_state; 5061 uint16_t vp_prev_err_state; 5062 #define VP_ERR_UNKWN 0 5063 #define VP_ERR_PORTDWN 1 5064 #define VP_ERR_FAB_UNSUPPORTED 2 5065 #define VP_ERR_FAB_NORESOURCES 3 5066 #define VP_ERR_FAB_LOGOUT 4 5067 #define VP_ERR_ADAP_NORESOURCES 5 5068 struct qla_hw_data *hw; 5069 struct scsi_qlt_host vha_tgt; 5070 struct req_que *req; 5071 int fw_heartbeat_counter; 5072 int seconds_since_last_heartbeat; 5073 struct fc_host_statistics fc_host_stat; 5074 struct qla_statistics qla_stats; 5075 struct bidi_statistics bidi_stats; 5076 atomic_t vref_count; 5077 struct qla8044_reset_template reset_tmplt; 5078 uint16_t bbcr; 5079 5080 uint16_t u_ql2xexchoffld; 5081 uint16_t u_ql2xiniexchg; 5082 uint16_t qlini_mode; 5083 uint16_t ql2xexchoffld; 5084 uint16_t ql2xiniexchg; 5085 5086 struct dentry *dfs_rport_root; 5087 5088 struct purex_list { 5089 struct list_head head; 5090 spinlock_t lock; 5091 } purex_list; 5092 struct purex_item default_item; 5093 5094 struct name_list_extended gnl; 5095 /* Count of active session/fcport */ 5096 int fcport_count; 5097 wait_queue_head_t fcport_waitQ; 5098 wait_queue_head_t vref_waitq; 5099 uint8_t min_supported_speed; 5100 uint8_t n2n_node_name[WWN_SIZE]; 5101 uint8_t n2n_port_name[WWN_SIZE]; 5102 uint16_t n2n_id; 5103 __le16 dport_data[4]; 5104 struct fab_scan scan; 5105 uint8_t scm_fabric_connection_flags; 5106 5107 unsigned int irq_offset; 5108 5109 u64 hw_err_cnt; 5110 u64 interface_err_cnt; 5111 u64 cmd_timeout_cnt; 5112 u64 reset_cmd_err_cnt; 5113 u64 link_down_time; 5114 u64 short_link_down_cnt; 5115 struct edif_dbell e_dbell; 5116 struct pur_core pur_cinfo; 5117 5118 #define DPORT_DIAG_IN_PROGRESS BIT_0 5119 #define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1 5120 uint16_t dport_status; 5121 } scsi_qla_host_t; 5122 5123 struct qla27xx_image_status { 5124 uint8_t image_status_mask; 5125 __le16 generation; 5126 uint8_t ver_major; 5127 uint8_t ver_minor; 5128 uint8_t bitmap; /* 28xx only */ 5129 uint8_t reserved[2]; 5130 __le32 checksum; 5131 __le32 signature; 5132 } __packed; 5133 5134 /* 28xx aux image status bimap values */ 5135 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 5136 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 5137 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 5138 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 5139 #define QLA28XX_AUX_IMG_NVME_PARAMS BIT_4 5140 5141 #define SET_VP_IDX 1 5142 #define SET_AL_PA 2 5143 #define RESET_VP_IDX 3 5144 #define RESET_AL_PA 4 5145 struct qla_vp_map { 5146 uint8_t idx; 5147 scsi_qla_host_t *vha; 5148 }; 5149 5150 struct qla2_sgx { 5151 dma_addr_t dma_addr; /* OUT */ 5152 uint32_t dma_len; /* OUT */ 5153 5154 uint32_t tot_bytes; /* IN */ 5155 struct scatterlist *cur_sg; /* IN */ 5156 5157 /* for book keeping, bzero on initial invocation */ 5158 uint32_t bytes_consumed; 5159 uint32_t num_bytes; 5160 uint32_t tot_partial; 5161 5162 /* for debugging */ 5163 uint32_t num_sg; 5164 srb_t *sp; 5165 }; 5166 5167 #define QLA_FW_STARTED(_ha) { \ 5168 int i; \ 5169 _ha->flags.fw_started = 1; \ 5170 _ha->base_qpair->fw_started = 1; \ 5171 for (i = 0; i < _ha->max_qpairs; i++) { \ 5172 if (_ha->queue_pair_map[i]) \ 5173 _ha->queue_pair_map[i]->fw_started = 1; \ 5174 } \ 5175 } 5176 5177 #define QLA_FW_STOPPED(_ha) { \ 5178 int i; \ 5179 _ha->flags.fw_started = 0; \ 5180 _ha->base_qpair->fw_started = 0; \ 5181 for (i = 0; i < _ha->max_qpairs; i++) { \ 5182 if (_ha->queue_pair_map[i]) \ 5183 _ha->queue_pair_map[i]->fw_started = 0; \ 5184 } \ 5185 } 5186 5187 5188 #define SFUB_CHECKSUM_SIZE 4 5189 5190 struct secure_flash_update_block { 5191 uint32_t block_info; 5192 uint32_t signature_lo; 5193 uint32_t signature_hi; 5194 uint32_t signature_upper[0x3e]; 5195 }; 5196 5197 struct secure_flash_update_block_pk { 5198 uint32_t block_info; 5199 uint32_t signature_lo; 5200 uint32_t signature_hi; 5201 uint32_t signature_upper[0x3e]; 5202 uint32_t public_key[0x41]; 5203 }; 5204 5205 /* 5206 * Macros to help code, maintain, etc. 5207 */ 5208 #define LOOP_TRANSITION(ha) \ 5209 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5210 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 5211 atomic_read(&ha->loop_state) == LOOP_DOWN) 5212 5213 #define STATE_TRANSITION(ha) \ 5214 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5215 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 5216 qla_vha_mark_busy(scsi_qla_host_t * vha)5217 static inline bool qla_vha_mark_busy(scsi_qla_host_t *vha) 5218 { 5219 atomic_inc(&vha->vref_count); 5220 mb(); 5221 if (vha->flags.delete_progress) { 5222 atomic_dec(&vha->vref_count); 5223 wake_up(&vha->vref_waitq); 5224 return true; 5225 } 5226 return false; 5227 } 5228 5229 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 5230 atomic_dec(&__vha->vref_count); \ 5231 wake_up(&__vha->vref_waitq); \ 5232 } while (0) \ 5233 5234 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 5235 atomic_inc(&__qpair->ref_count); \ 5236 mb(); \ 5237 if (__qpair->delete_in_progress) { \ 5238 atomic_dec(&__qpair->ref_count); \ 5239 __bail = 1; \ 5240 } else { \ 5241 __bail = 0; \ 5242 } \ 5243 } while (0) 5244 5245 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 5246 atomic_dec(&__qpair->ref_count) 5247 5248 #define QLA_ENA_CONF(_ha) {\ 5249 int i;\ 5250 _ha->base_qpair->enable_explicit_conf = 1; \ 5251 for (i = 0; i < _ha->max_qpairs; i++) { \ 5252 if (_ha->queue_pair_map[i]) \ 5253 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 5254 } \ 5255 } 5256 5257 #define QLA_DIS_CONF(_ha) {\ 5258 int i;\ 5259 _ha->base_qpair->enable_explicit_conf = 0; \ 5260 for (i = 0; i < _ha->max_qpairs; i++) { \ 5261 if (_ha->queue_pair_map[i]) \ 5262 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 5263 } \ 5264 } 5265 5266 /* 5267 * qla2x00 local function return status codes 5268 */ 5269 #define MBS_MASK 0x3fff 5270 5271 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 5272 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 5273 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 5274 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 5275 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 5276 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 5277 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 5278 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 5279 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 5280 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 5281 5282 #define QLA_FUNCTION_TIMEOUT 0x100 5283 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 5284 #define QLA_FUNCTION_FAILED 0x102 5285 #define QLA_MEMORY_ALLOC_FAILED 0x103 5286 #define QLA_LOCK_TIMEOUT 0x104 5287 #define QLA_ABORTED 0x105 5288 #define QLA_SUSPENDED 0x106 5289 #define QLA_BUSY 0x107 5290 #define QLA_ALREADY_REGISTERED 0x109 5291 #define QLA_OS_TIMER_EXPIRED 0x10a 5292 #define QLA_ERR_NO_QPAIR 0x10b 5293 #define QLA_ERR_NOT_FOUND 0x10c 5294 #define QLA_ERR_FROM_FW 0x10d 5295 5296 #define NVRAM_DELAY() udelay(10) 5297 5298 /* 5299 * Flash support definitions 5300 */ 5301 #define OPTROM_SIZE_2300 0x20000 5302 #define OPTROM_SIZE_2322 0x100000 5303 #define OPTROM_SIZE_24XX 0x100000 5304 #define OPTROM_SIZE_25XX 0x200000 5305 #define OPTROM_SIZE_81XX 0x400000 5306 #define OPTROM_SIZE_82XX 0x800000 5307 #define OPTROM_SIZE_83XX 0x1000000 5308 #define OPTROM_SIZE_28XX 0x2000000 5309 5310 #define OPTROM_BURST_SIZE 0x1000 5311 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 5312 5313 #define QLA_DSDS_PER_IOCB 37 5314 5315 #define QLA_SG_ALL 1024 5316 5317 enum nexus_wait_type { 5318 WAIT_HOST = 0, 5319 WAIT_TARGET, 5320 WAIT_LUN, 5321 }; 5322 5323 #define INVALID_EDIF_SA_INDEX 0xffff 5324 #define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe 5325 5326 #define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE 5327 5328 /* edif hash element */ 5329 struct edif_list_entry { 5330 uint16_t handle; /* nport_handle */ 5331 uint32_t update_sa_index; 5332 uint32_t delete_sa_index; 5333 uint32_t count; /* counter for filtering sa_index */ 5334 #define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */ 5335 uint32_t flags; /* used by sadb cleanup code */ 5336 fc_port_t *fcport; /* needed by rx delay timer function */ 5337 struct timer_list timer; /* rx delay timer */ 5338 struct list_head next; 5339 }; 5340 5341 #define EDIF_TX_INDX_BASE 512 5342 #define EDIF_RX_INDX_BASE 0 5343 #define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */ 5344 5345 /* entry in the sa_index free pool */ 5346 5347 struct sa_index_pair { 5348 uint16_t sa_index; 5349 uint32_t spi; 5350 }; 5351 5352 /* edif sa_index data structure */ 5353 struct edif_sa_index_entry { 5354 struct sa_index_pair sa_pair[2]; 5355 fc_port_t *fcport; 5356 uint16_t handle; 5357 struct list_head next; 5358 }; 5359 5360 /* Refer to SNIA SFF 8247 */ 5361 struct sff_8247_a0 { 5362 u8 txid; /* transceiver id */ 5363 u8 ext_txid; 5364 u8 connector; 5365 /* compliance code */ 5366 u8 eth_infi_cc3; /* ethernet, inifiband */ 5367 u8 sonet_cc4[2]; 5368 u8 eth_cc6; 5369 /* link length */ 5370 #define FC_LL_VL BIT_7 /* very long */ 5371 #define FC_LL_S BIT_6 /* Short */ 5372 #define FC_LL_I BIT_5 /* Intermidiate*/ 5373 #define FC_LL_L BIT_4 /* Long */ 5374 #define FC_LL_M BIT_3 /* Medium */ 5375 #define FC_LL_SA BIT_2 /* ShortWave laser */ 5376 #define FC_LL_LC BIT_1 /* LongWave laser */ 5377 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 5378 u8 fc_ll_cc7; 5379 /* FC technology */ 5380 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 5381 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 5382 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 5383 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 5384 #define FC_TEC_ACT BIT_3 /* Active cable */ 5385 #define FC_TEC_PAS BIT_2 /* Passive cable */ 5386 u8 fc_tec_cc8; 5387 /* Transmission Media */ 5388 #define FC_MED_TW BIT_7 /* Twin Ax */ 5389 #define FC_MED_TP BIT_6 /* Twited Pair */ 5390 #define FC_MED_MI BIT_5 /* Min Coax */ 5391 #define FC_MED_TV BIT_4 /* Video Coax */ 5392 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 5393 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 5394 #define FC_MED_SM BIT_0 /* Single Mode */ 5395 u8 fc_med_cc9; 5396 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 5397 #define FC_SP_12 BIT_7 5398 #define FC_SP_8 BIT_6 5399 #define FC_SP_16 BIT_5 5400 #define FC_SP_4 BIT_4 5401 #define FC_SP_32 BIT_3 5402 #define FC_SP_2 BIT_2 5403 #define FC_SP_1 BIT_0 5404 u8 fc_sp_cc10; 5405 u8 encode; 5406 u8 bitrate; 5407 u8 rate_id; 5408 u8 length_km; /* offset 14/eh */ 5409 u8 length_100m; 5410 u8 length_50um_10m; 5411 u8 length_62um_10m; 5412 u8 length_om4_10m; 5413 u8 length_om3_10m; 5414 #define SFF_VEN_NAME_LEN 16 5415 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 5416 u8 tx_compat; 5417 u8 vendor_oui[3]; 5418 #define SFF_PART_NAME_LEN 16 5419 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 5420 u8 vendor_rev[4]; 5421 u8 wavelength[2]; 5422 u8 resv; 5423 u8 cc_base; 5424 u8 options[2]; /* offset 64 */ 5425 u8 br_max; 5426 u8 br_min; 5427 u8 vendor_sn[16]; 5428 u8 date_code[8]; 5429 u8 diag; 5430 u8 enh_options; 5431 u8 sff_revision; 5432 u8 cc_ext; 5433 u8 vendor_specific[32]; 5434 u8 resv2[128]; 5435 }; 5436 5437 /* BPM -- Buffer Plus Management support. */ 5438 #define IS_BPM_CAPABLE(ha) \ 5439 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 5440 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5441 #define IS_BPM_RANGE_CAPABLE(ha) \ 5442 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5443 #define IS_BPM_ENABLED(vha) \ 5444 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw)) 5445 5446 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 5447 5448 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 5449 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 5450 5451 #define SAVE_TOPO(_ha) { \ 5452 if (_ha->current_topology) \ 5453 _ha->prev_topology = _ha->current_topology; \ 5454 } 5455 5456 #define N2N_TOPO(ha) \ 5457 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 5458 ha->current_topology == ISP_CFG_N || \ 5459 !ha->current_topology) 5460 5461 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */ 5462 5463 #define NVME_TYPE(fcport) \ 5464 (fcport->fc4_type & FS_FC4TYPE_NVME) \ 5465 5466 #define FCP_TYPE(fcport) \ 5467 (fcport->fc4_type & FS_FC4TYPE_FCP) \ 5468 5469 #define NVME_ONLY_TARGET(fcport) \ 5470 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ 5471 5472 #define NVME_FCP_TARGET(fcport) \ 5473 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ 5474 5475 #define NVME_PRIORITY(ha, fcport) \ 5476 (NVME_FCP_TARGET(fcport) && \ 5477 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) 5478 5479 #define NVME_TARGET(ha, fcport) \ 5480 (fcport->do_prli_nvme || \ 5481 NVME_ONLY_TARGET(fcport)) \ 5482 5483 #define PRLI_PHASE(_cls) \ 5484 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) 5485 5486 enum ql_vnd_host_stat_action { 5487 QLA_STOP = 0, 5488 QLA_START, 5489 QLA_CLEAR, 5490 }; 5491 5492 struct ql_vnd_mng_host_stats_param { 5493 u32 stat_type; 5494 enum ql_vnd_host_stat_action action; 5495 } __packed; 5496 5497 struct ql_vnd_mng_host_stats_resp { 5498 u32 status; 5499 } __packed; 5500 5501 struct ql_vnd_stats_param { 5502 u32 stat_type; 5503 } __packed; 5504 5505 struct ql_vnd_tgt_stats_param { 5506 s32 tgt_id; 5507 u32 stat_type; 5508 } __packed; 5509 5510 enum ql_vnd_host_port_action { 5511 QLA_ENABLE = 0, 5512 QLA_DISABLE, 5513 }; 5514 5515 struct ql_vnd_mng_host_port_param { 5516 enum ql_vnd_host_port_action action; 5517 } __packed; 5518 5519 struct ql_vnd_mng_host_port_resp { 5520 u32 status; 5521 } __packed; 5522 5523 struct ql_vnd_stat_entry { 5524 u32 stat_type; /* Failure type */ 5525 u32 tgt_num; /* Target Num */ 5526 u64 cnt; /* Counter value */ 5527 } __packed; 5528 5529 struct ql_vnd_stats { 5530 u64 entry_count; /* Num of entries */ 5531 u64 rservd; 5532 struct ql_vnd_stat_entry entry[]; /* Place holder of entries */ 5533 } __packed; 5534 5535 struct ql_vnd_host_stats_resp { 5536 u32 status; 5537 struct ql_vnd_stats stats; 5538 } __packed; 5539 5540 struct ql_vnd_tgt_stats_resp { 5541 u32 status; 5542 struct ql_vnd_stats stats; 5543 } __packed; 5544 5545 #include "qla_target.h" 5546 #include "qla_gbl.h" 5547 #include "qla_dbg.h" 5548 #include "qla_inline.h" 5549 5550 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \ 5551 _fcport->disc_state == DSC_DELETED) 5552 5553 #define DBG_FCPORT_PRFMT(_fp, _fmt, _args...) \ 5554 "%s: %8phC: " _fmt " (state=%d disc_state=%d scan_state=%d loopid=0x%x deleted=%d flags=0x%x)\n", \ 5555 __func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \ 5556 _fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \ 5557 _fp->flags 5558 5559 #define TMF_NOT_READY(_fcport) \ 5560 (!_fcport || IS_SESSION_DELETED(_fcport) || atomic_read(&_fcport->state) != FCS_ONLINE || \ 5561 !_fcport->vha->hw->flags.fw_started) 5562 5563 #endif 5564
