1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #ifndef NIC_H
10 #define NIC_H
11
12 #include <linux/netdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include "thunder_bgx.h"
16
17 /* PCI device IDs */
18 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E
19 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011
20 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034
21 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026
22
23 /* Subsystem device IDs */
24 #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E
25 #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E
26 #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E
27
28 #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E
29 #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134
30 #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234
31 #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334
32
33
34 /* PCI BAR nos */
35 #define PCI_CFG_REG_BAR_NUM 0
36 #define PCI_MSIX_REG_BAR_NUM 4
37
38 /* NIC SRIOV VF count */
39 #define MAX_NUM_VFS_SUPPORTED 128
40 #define DEFAULT_NUM_VF_ENABLED 8
41
42 #define NIC_TNS_BYPASS_MODE 0
43 #define NIC_TNS_MODE 1
44
45 /* NIC priv flags */
46 #define NIC_SRIOV_ENABLED BIT(0)
47
48 /* Min/Max packet size */
49 #define NIC_HW_MIN_FRS 64
50 #define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */
51
52 /* Max pkinds */
53 #define NIC_MAX_PKIND 16
54
55 /* Max when CPI_ALG is IP diffserv */
56 #define NIC_MAX_CPI_PER_LMAC 64
57
58 /* NIC VF Interrupts */
59 #define NICVF_INTR_CQ 0
60 #define NICVF_INTR_SQ 1
61 #define NICVF_INTR_RBDR 2
62 #define NICVF_INTR_PKT_DROP 3
63 #define NICVF_INTR_TCP_TIMER 4
64 #define NICVF_INTR_MBOX 5
65 #define NICVF_INTR_QS_ERR 6
66
67 #define NICVF_INTR_CQ_SHIFT 0
68 #define NICVF_INTR_SQ_SHIFT 8
69 #define NICVF_INTR_RBDR_SHIFT 16
70 #define NICVF_INTR_PKT_DROP_SHIFT 20
71 #define NICVF_INTR_TCP_TIMER_SHIFT 21
72 #define NICVF_INTR_MBOX_SHIFT 22
73 #define NICVF_INTR_QS_ERR_SHIFT 23
74
75 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
76 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
77 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
78 #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT)
79 #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT)
80 #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT)
81 #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT)
82
83 /* MSI-X interrupts */
84 #define NIC_PF_MSIX_VECTORS 10
85 #define NIC_VF_MSIX_VECTORS 20
86
87 #define NIC_PF_INTR_ID_ECC0_SBE 0
88 #define NIC_PF_INTR_ID_ECC0_DBE 1
89 #define NIC_PF_INTR_ID_ECC1_SBE 2
90 #define NIC_PF_INTR_ID_ECC1_DBE 3
91 #define NIC_PF_INTR_ID_ECC2_SBE 4
92 #define NIC_PF_INTR_ID_ECC2_DBE 5
93 #define NIC_PF_INTR_ID_ECC3_SBE 6
94 #define NIC_PF_INTR_ID_ECC3_DBE 7
95 #define NIC_PF_INTR_ID_MBOX0 8
96 #define NIC_PF_INTR_ID_MBOX1 9
97
98 /* Minimum FIFO level before all packets for the CQ are dropped
99 *
100 * This value ensures that once a packet has been "accepted"
101 * for reception it will not get dropped due to non-availability
102 * of CQ descriptor. An errata in HW mandates this value to be
103 * atleast 0x100.
104 */
105 #define NICPF_CQM_MIN_DROP_LEVEL 0x100
106
107 /* Global timer for CQ timer thresh interrupts
108 * Calculated for SCLK of 700Mhz
109 * value written should be a 1/16th of what is expected
110 *
111 * 1 tick per 0.025usec
112 */
113 #define NICPF_CLK_PER_INT_TICK 1
114
115 /* Time to wait before we decide that a SQ is stuck.
116 *
117 * Since both pkt rx and tx notifications are done with same CQ,
118 * when packets are being received at very high rate (eg: L2 forwarding)
119 * then freeing transmitted skbs will be delayed and watchdog
120 * will kick in, resetting interface. Hence keeping this value high.
121 */
122 #define NICVF_TX_TIMEOUT (50 * HZ)
123
124 struct nicvf_cq_poll {
125 struct nicvf *nicvf;
126 u8 cq_idx; /* Completion queue index */
127 struct napi_struct napi;
128 };
129
130 #define NIC_MAX_RSS_HASH_BITS 8
131 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
132 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
133
134 struct nicvf_rss_info {
135 bool enable;
136 #define RSS_L2_EXTENDED_HASH_ENA BIT(0)
137 #define RSS_IP_HASH_ENA BIT(1)
138 #define RSS_TCP_HASH_ENA BIT(2)
139 #define RSS_TCP_SYN_DIS BIT(3)
140 #define RSS_UDP_HASH_ENA BIT(4)
141 #define RSS_L4_EXTENDED_HASH_ENA BIT(5)
142 #define RSS_ROCE_ENA BIT(6)
143 #define RSS_L3_BI_DIRECTION_ENA BIT(7)
144 #define RSS_L4_BI_DIRECTION_ENA BIT(8)
145 u64 cfg;
146 u8 hash_bits;
147 u16 rss_size;
148 u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
149 u64 key[RSS_HASH_KEY_SIZE];
150 } ____cacheline_aligned_in_smp;
151
152 struct nicvf_pfc {
153 u8 autoneg;
154 u8 fc_rx;
155 u8 fc_tx;
156 };
157
158 enum rx_stats_reg_offset {
159 RX_OCTS = 0x0,
160 RX_UCAST = 0x1,
161 RX_BCAST = 0x2,
162 RX_MCAST = 0x3,
163 RX_RED = 0x4,
164 RX_RED_OCTS = 0x5,
165 RX_ORUN = 0x6,
166 RX_ORUN_OCTS = 0x7,
167 RX_FCS = 0x8,
168 RX_L2ERR = 0x9,
169 RX_DRP_BCAST = 0xa,
170 RX_DRP_MCAST = 0xb,
171 RX_DRP_L3BCAST = 0xc,
172 RX_DRP_L3MCAST = 0xd,
173 RX_STATS_ENUM_LAST,
174 };
175
176 enum tx_stats_reg_offset {
177 TX_OCTS = 0x0,
178 TX_UCAST = 0x1,
179 TX_BCAST = 0x2,
180 TX_MCAST = 0x3,
181 TX_DROP = 0x4,
182 TX_STATS_ENUM_LAST,
183 };
184
185 struct nicvf_hw_stats {
186 u64 rx_bytes;
187 u64 rx_frames;
188 u64 rx_ucast_frames;
189 u64 rx_bcast_frames;
190 u64 rx_mcast_frames;
191 u64 rx_drops;
192 u64 rx_drop_red;
193 u64 rx_drop_red_bytes;
194 u64 rx_drop_overrun;
195 u64 rx_drop_overrun_bytes;
196 u64 rx_drop_bcast;
197 u64 rx_drop_mcast;
198 u64 rx_drop_l3_bcast;
199 u64 rx_drop_l3_mcast;
200 u64 rx_fcs_errors;
201 u64 rx_l2_errors;
202
203 u64 tx_bytes;
204 u64 tx_frames;
205 u64 tx_ucast_frames;
206 u64 tx_bcast_frames;
207 u64 tx_mcast_frames;
208 u64 tx_drops;
209 };
210
211 struct nicvf_drv_stats {
212 /* CQE Rx errs */
213 u64 rx_bgx_truncated_pkts;
214 u64 rx_jabber_errs;
215 u64 rx_fcs_errs;
216 u64 rx_bgx_errs;
217 u64 rx_prel2_errs;
218 u64 rx_l2_hdr_malformed;
219 u64 rx_oversize;
220 u64 rx_undersize;
221 u64 rx_l2_len_mismatch;
222 u64 rx_l2_pclp;
223 u64 rx_ip_ver_errs;
224 u64 rx_ip_csum_errs;
225 u64 rx_ip_hdr_malformed;
226 u64 rx_ip_payload_malformed;
227 u64 rx_ip_ttl_errs;
228 u64 rx_l3_pclp;
229 u64 rx_l4_malformed;
230 u64 rx_l4_csum_errs;
231 u64 rx_udp_len_errs;
232 u64 rx_l4_port_errs;
233 u64 rx_tcp_flag_errs;
234 u64 rx_tcp_offset_errs;
235 u64 rx_l4_pclp;
236 u64 rx_truncated_pkts;
237
238 /* CQE Tx errs */
239 u64 tx_desc_fault;
240 u64 tx_hdr_cons_err;
241 u64 tx_subdesc_err;
242 u64 tx_max_size_exceeded;
243 u64 tx_imm_size_oflow;
244 u64 tx_data_seq_err;
245 u64 tx_mem_seq_err;
246 u64 tx_lock_viol;
247 u64 tx_data_fault;
248 u64 tx_tstmp_conflict;
249 u64 tx_tstmp_timeout;
250 u64 tx_mem_fault;
251 u64 tx_csum_overlap;
252 u64 tx_csum_overflow;
253
254 /* driver debug stats */
255 u64 tx_tso;
256 u64 tx_timeout;
257 u64 txq_stop;
258 u64 txq_wake;
259
260 u64 rcv_buffer_alloc_failures;
261 u64 page_alloc;
262
263 struct u64_stats_sync syncp;
264 };
265
266 struct cavium_ptp;
267
268 struct xcast_addr_list {
269 int count;
270 u64 mc[];
271 };
272
273 struct nicvf_work {
274 struct delayed_work work;
275 u8 mode;
276 struct xcast_addr_list *mc;
277 };
278
279 struct nicvf {
280 struct nicvf *pnicvf;
281 struct net_device *netdev;
282 struct pci_dev *pdev;
283 void __iomem *reg_base;
284 struct bpf_prog *xdp_prog;
285 #define MAX_QUEUES_PER_QSET 8
286 struct queue_set *qs;
287 void *iommu_domain;
288 u8 vf_id;
289 u8 sqs_id;
290 bool sqs_mode;
291 bool hw_tso;
292 bool t88;
293
294 /* Receive buffer alloc */
295 u32 rb_page_offset;
296 u16 rb_pageref;
297 bool rb_alloc_fail;
298 bool rb_work_scheduled;
299 struct page *rb_page;
300 struct delayed_work rbdr_work;
301 struct tasklet_struct rbdr_task;
302
303 /* Secondary Qset */
304 u8 sqs_count;
305 #define MAX_SQS_PER_VF_SINGLE_NODE 5
306 #define MAX_SQS_PER_VF 11
307 struct nicvf *snicvf[MAX_SQS_PER_VF];
308
309 /* Queue count */
310 u8 rx_queues;
311 u8 tx_queues;
312 u8 xdp_tx_queues;
313 u8 max_queues;
314
315 u8 node;
316 u8 cpi_alg;
317 bool link_up;
318 u8 mac_type;
319 u8 duplex;
320 u32 speed;
321 bool tns_mode;
322 bool loopback_supported;
323 struct nicvf_rss_info rss_info;
324 struct nicvf_pfc pfc;
325 struct tasklet_struct qs_err_task;
326 struct work_struct reset_task;
327 struct nicvf_work rx_mode_work;
328 /* spinlock to protect workqueue arguments from concurrent access */
329 spinlock_t rx_mode_wq_lock;
330
331 /* PTP timestamp */
332 struct cavium_ptp *ptp_clock;
333 /* Inbound timestamping is on */
334 bool hw_rx_tstamp;
335 /* When the packet that requires timestamping is sent, hardware inserts
336 * two entries to the completion queue. First is the regular
337 * CQE_TYPE_SEND entry that signals that the packet was sent.
338 * The second is CQE_TYPE_SEND_PTP that contains the actual timestamp
339 * for that packet.
340 * `ptp_skb` is initialized in the handler for the CQE_TYPE_SEND
341 * entry and is used and zeroed in the handler for the CQE_TYPE_SEND_PTP
342 * entry.
343 * So `ptp_skb` is used to hold the pointer to the packet between
344 * the calls to CQE_TYPE_SEND and CQE_TYPE_SEND_PTP handlers.
345 */
346 struct sk_buff *ptp_skb;
347 /* `tx_ptp_skbs` is set when the hardware is sending a packet that
348 * requires timestamping. Cavium hardware can not process more than one
349 * such packet at once so this is set each time the driver submits
350 * a packet that requires timestamping to the send queue and clears
351 * each time it receives the entry on the completion queue saying
352 * that such packet was sent.
353 * So `tx_ptp_skbs` prevents driver from submitting more than one
354 * packet that requires timestamping to the hardware for transmitting.
355 */
356 atomic_t tx_ptp_skbs;
357
358 /* Interrupt coalescing settings */
359 u32 cq_coalesce_usecs;
360 u32 msg_enable;
361
362 /* Stats */
363 struct nicvf_hw_stats hw_stats;
364 struct nicvf_drv_stats __percpu *drv_stats;
365 struct bgx_stats bgx_stats;
366
367 /* Napi */
368 struct nicvf_cq_poll *napi[8];
369
370 /* MSI-X */
371 u8 num_vec;
372 char irq_name[NIC_VF_MSIX_VECTORS][IFNAMSIZ + 15];
373 bool irq_allocated[NIC_VF_MSIX_VECTORS];
374 cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS];
375
376 /* VF <-> PF mailbox communication */
377 bool pf_acked;
378 bool pf_nacked;
379 bool set_mac_pending;
380 } ____cacheline_aligned_in_smp;
381
382 /* PF <--> VF Mailbox communication
383 * Eight 64bit registers are shared between PF and VF.
384 * Separate set for each VF.
385 * Writing '1' into last register mbx7 means end of message.
386 */
387
388 /* PF <--> VF mailbox communication */
389 #define NIC_PF_VF_MAILBOX_SIZE 2
390 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */
391
392 /* Mailbox message types */
393 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */
394 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */
395 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */
396 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */
397 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */
398 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */
399 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */
400 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */
401 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */
402 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */
403 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */
404 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */
405 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */
406 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */
407 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */
408 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */
409 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */
410 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */
411 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */
412 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */
413 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */
414 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */
415 #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */
416 #define NIC_MBOX_MSG_PFC 0x18 /* Pause frame control */
417 #define NIC_MBOX_MSG_PTP_CFG 0x19 /* HW packet timestamp */
418 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */
419 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */
420 #define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */
421 #define NIC_MBOX_MSG_ADD_MCAST 0xF3 /* Add MAC to DCAM filters */
422 #define NIC_MBOX_MSG_SET_XCAST 0xF4 /* Set MCAST/BCAST RX mode */
423
424 struct nic_cfg_msg {
425 u8 msg;
426 u8 vf_id;
427 u8 node_id;
428 u8 tns_mode:1;
429 u8 sqs_mode:1;
430 u8 loopback_supported:1;
431 u8 mac_addr[ETH_ALEN];
432 };
433
434 /* Qset configuration */
435 struct qs_cfg_msg {
436 u8 msg;
437 u8 num;
438 u8 sqs_count;
439 u64 cfg;
440 };
441
442 /* Receive queue configuration */
443 struct rq_cfg_msg {
444 u8 msg;
445 u8 qs_num;
446 u8 rq_num;
447 u64 cfg;
448 };
449
450 /* Send queue configuration */
451 struct sq_cfg_msg {
452 u8 msg;
453 u8 qs_num;
454 u8 sq_num;
455 bool sqs_mode;
456 u64 cfg;
457 };
458
459 /* Set VF's MAC address */
460 struct set_mac_msg {
461 u8 msg;
462 u8 vf_id;
463 u8 mac_addr[ETH_ALEN];
464 };
465
466 /* Set Maximum frame size */
467 struct set_frs_msg {
468 u8 msg;
469 u8 vf_id;
470 u16 max_frs;
471 };
472
473 /* Set CPI algorithm type */
474 struct cpi_cfg_msg {
475 u8 msg;
476 u8 vf_id;
477 u8 rq_cnt;
478 u8 cpi_alg;
479 };
480
481 /* Get RSS table size */
482 struct rss_sz_msg {
483 u8 msg;
484 u8 vf_id;
485 u16 ind_tbl_size;
486 };
487
488 /* Set RSS configuration */
489 struct rss_cfg_msg {
490 u8 msg;
491 u8 vf_id;
492 u8 hash_bits;
493 u8 tbl_len;
494 u8 tbl_offset;
495 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8
496 u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG];
497 };
498
499 struct bgx_stats_msg {
500 u8 msg;
501 u8 vf_id;
502 u8 rx;
503 u8 idx;
504 u64 stats;
505 };
506
507 /* Physical interface link status */
508 struct bgx_link_status {
509 u8 msg;
510 u8 mac_type;
511 u8 link_up;
512 u8 duplex;
513 u32 speed;
514 };
515
516 /* Get Extra Qset IDs */
517 struct sqs_alloc {
518 u8 msg;
519 u8 vf_id;
520 u8 qs_count;
521 };
522
523 struct nicvf_ptr {
524 u8 msg;
525 u8 vf_id;
526 bool sqs_mode;
527 u8 sqs_id;
528 u64 nicvf;
529 };
530
531 /* Set interface in loopback mode */
532 struct set_loopback {
533 u8 msg;
534 u8 vf_id;
535 bool enable;
536 };
537
538 /* Reset statistics counters */
539 struct reset_stat_cfg {
540 u8 msg;
541 /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */
542 u16 rx_stat_mask;
543 /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */
544 u8 tx_stat_mask;
545 /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1)
546 * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1)
547 * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1)
548 * ..
549 * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1)
550 * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1)
551 */
552 u16 rq_stat_mask;
553 /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1)
554 * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1)
555 * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1)
556 * ..
557 * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1)
558 * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1)
559 */
560 u16 sq_stat_mask;
561 };
562
563 struct pfc {
564 u8 msg;
565 u8 get; /* Get or set PFC settings */
566 u8 autoneg;
567 u8 fc_rx;
568 u8 fc_tx;
569 };
570
571 struct set_ptp {
572 u8 msg;
573 bool enable;
574 };
575
576 struct xcast {
577 u8 msg;
578 union {
579 u8 mode;
580 u64 mac;
581 } data;
582 };
583
584 /* 128 bit shared memory between PF and each VF */
585 union nic_mbx {
586 struct { u8 msg; } msg;
587 struct nic_cfg_msg nic_cfg;
588 struct qs_cfg_msg qs;
589 struct rq_cfg_msg rq;
590 struct sq_cfg_msg sq;
591 struct set_mac_msg mac;
592 struct set_frs_msg frs;
593 struct cpi_cfg_msg cpi_cfg;
594 struct rss_sz_msg rss_size;
595 struct rss_cfg_msg rss_cfg;
596 struct bgx_stats_msg bgx_stats;
597 struct bgx_link_status link_status;
598 struct sqs_alloc sqs_alloc;
599 struct nicvf_ptr nicvf;
600 struct set_loopback lbk;
601 struct reset_stat_cfg reset_stat;
602 struct pfc pfc;
603 struct set_ptp ptp;
604 struct xcast xcast;
605 };
606
607 #define NIC_NODE_ID_MASK 0x03
608 #define NIC_NODE_ID_SHIFT 44
609
nic_get_node_id(struct pci_dev * pdev)610 static inline int nic_get_node_id(struct pci_dev *pdev)
611 {
612 u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM);
613 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK);
614 }
615
pass1_silicon(struct pci_dev * pdev)616 static inline bool pass1_silicon(struct pci_dev *pdev)
617 {
618 return (pdev->revision < 8) &&
619 (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);
620 }
621
pass2_silicon(struct pci_dev * pdev)622 static inline bool pass2_silicon(struct pci_dev *pdev)
623 {
624 return (pdev->revision >= 8) &&
625 (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);
626 }
627
628 int nicvf_set_real_num_queues(struct net_device *netdev,
629 int tx_queues, int rx_queues);
630 int nicvf_open(struct net_device *netdev);
631 int nicvf_stop(struct net_device *netdev);
632 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx);
633 void nicvf_config_rss(struct nicvf *nic);
634 void nicvf_set_rss_key(struct nicvf *nic);
635 void nicvf_set_ethtool_ops(struct net_device *netdev);
636 void nicvf_update_stats(struct nicvf *nic);
637 void nicvf_update_lmac_stats(struct nicvf *nic);
638
639 #endif /* NIC_H */
640
