1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * twl4030.h - header for TWL4030 PM and audio CODEC device
4 *
5 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 *
7 * Based on tlv320aic23.c:
8 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
9 */
10
11 #ifndef __TWL_H_
12 #define __TWL_H_
13
14 #include <linux/types.h>
15 #include <linux/input/matrix_keypad.h>
16
17 /*
18 * Using the twl4030 core we address registers using a pair
19 * { module id, relative register offset }
20 * which that core then maps to the relevant
21 * { i2c slave, absolute register address }
22 *
23 * The module IDs are meaningful only to the twl4030 core code,
24 * which uses them as array indices to look up the first register
25 * address each module uses within a given i2c slave.
26 */
27
28 /* Module IDs for similar functionalities found in twl4030/twl6030 */
29 enum twl_module_ids {
30 TWL_MODULE_USB,
31 TWL_MODULE_PIH,
32 TWL_MODULE_MAIN_CHARGE,
33 TWL_MODULE_PM_MASTER,
34 TWL_MODULE_PM_RECEIVER,
35
36 TWL_MODULE_RTC,
37 TWL_MODULE_PWM,
38 TWL_MODULE_LED,
39 TWL_MODULE_SECURED_REG,
40
41 TWL_MODULE_LAST,
42 };
43
44 /* Modules only available in twl4030 series */
45 enum twl4030_module_ids {
46 TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST,
47 TWL4030_MODULE_GPIO,
48 TWL4030_MODULE_INTBR,
49 TWL4030_MODULE_TEST,
50 TWL4030_MODULE_KEYPAD,
51
52 TWL4030_MODULE_MADC,
53 TWL4030_MODULE_INTERRUPTS,
54 TWL4030_MODULE_PRECHARGE,
55 TWL4030_MODULE_BACKUP,
56 TWL4030_MODULE_INT,
57
58 TWL5031_MODULE_ACCESSORY,
59 TWL5031_MODULE_INTERRUPTS,
60
61 TWL4030_MODULE_LAST,
62 };
63
64 /* Modules only available in twl6030 series */
65 enum twl6030_module_ids {
66 TWL6030_MODULE_ID0 = TWL_MODULE_LAST,
67 TWL6030_MODULE_ID1,
68 TWL6030_MODULE_ID2,
69 TWL6030_MODULE_GPADC,
70 TWL6030_MODULE_GASGAUGE,
71
72 TWL6030_MODULE_LAST,
73 };
74
75 /* Until the clients has been converted to use TWL_MODULE_LED */
76 #define TWL4030_MODULE_LED TWL_MODULE_LED
77
78 #define GPIO_INTR_OFFSET 0
79 #define KEYPAD_INTR_OFFSET 1
80 #define BCI_INTR_OFFSET 2
81 #define MADC_INTR_OFFSET 3
82 #define USB_INTR_OFFSET 4
83 #define CHARGERFAULT_INTR_OFFSET 5
84 #define BCI_PRES_INTR_OFFSET 9
85 #define USB_PRES_INTR_OFFSET 10
86 #define RTC_INTR_OFFSET 11
87
88 /*
89 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
90 */
91 #define PWR_INTR_OFFSET 0
92 #define HOTDIE_INTR_OFFSET 12
93 #define SMPSLDO_INTR_OFFSET 13
94 #define BATDETECT_INTR_OFFSET 14
95 #define SIMDETECT_INTR_OFFSET 15
96 #define MMCDETECT_INTR_OFFSET 16
97 #define GASGAUGE_INTR_OFFSET 17
98 #define USBOTG_INTR_OFFSET 4
99 #define CHARGER_INTR_OFFSET 2
100 #define RSV_INTR_OFFSET 0
101
102 /* INT register offsets */
103 #define REG_INT_STS_A 0x00
104 #define REG_INT_STS_B 0x01
105 #define REG_INT_STS_C 0x02
106
107 #define REG_INT_MSK_LINE_A 0x03
108 #define REG_INT_MSK_LINE_B 0x04
109 #define REG_INT_MSK_LINE_C 0x05
110
111 #define REG_INT_MSK_STS_A 0x06
112 #define REG_INT_MSK_STS_B 0x07
113 #define REG_INT_MSK_STS_C 0x08
114
115 /* MASK INT REG GROUP A */
116 #define TWL6030_PWR_INT_MASK 0x07
117 #define TWL6030_RTC_INT_MASK 0x18
118 #define TWL6030_HOTDIE_INT_MASK 0x20
119 #define TWL6030_SMPSLDOA_INT_MASK 0xC0
120
121 /* MASK INT REG GROUP B */
122 #define TWL6030_SMPSLDOB_INT_MASK 0x01
123 #define TWL6030_BATDETECT_INT_MASK 0x02
124 #define TWL6030_SIMDETECT_INT_MASK 0x04
125 #define TWL6030_MMCDETECT_INT_MASK 0x08
126 #define TWL6030_GPADC_INT_MASK 0x60
127 #define TWL6030_GASGAUGE_INT_MASK 0x80
128
129 /* MASK INT REG GROUP C */
130 #define TWL6030_USBOTG_INT_MASK 0x0F
131 #define TWL6030_CHARGER_CTRL_INT_MASK 0x10
132 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60
133
134 #define TWL6030_MMCCTRL 0xEE
135 #define VMMC_AUTO_OFF (0x1 << 3)
136 #define SW_FC (0x1 << 2)
137 #define STS_MMC 0x1
138
139 #define TWL6030_CFG_INPUT_PUPD3 0xF2
140 #define MMC_PU (0x1 << 3)
141 #define MMC_PD (0x1 << 2)
142
143 #define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF)
144 #define TWL_SIL_REV(rev) ((rev) >> 24)
145 #define TWL_SIL_5030 0x09002F
146 #define TWL5030_REV_1_0 0x00
147 #define TWL5030_REV_1_1 0x10
148 #define TWL5030_REV_1_2 0x30
149
150 #define TWL4030_CLASS_ID 0x4030
151 #define TWL6030_CLASS_ID 0x6030
152 unsigned int twl_rev(void);
153 #define GET_TWL_REV (twl_rev())
154 #define TWL_CLASS_IS(class, id) \
155 static inline int twl_class_is_ ##class(void) \
156 { \
157 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
158 }
159
160 TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
161 TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
162
163 /* Set the regcache bypass for the regmap associated with the nodule */
164 int twl_set_regcache_bypass(u8 mod_no, bool enable);
165
166 /*
167 * Read and write several 8-bit registers at once.
168 */
169 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
170 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
171
172 /*
173 * Read and write single 8-bit registers
174 */
twl_i2c_write_u8(u8 mod_no,u8 val,u8 reg)175 static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) {
176 return twl_i2c_write(mod_no, &val, reg, 1);
177 }
178
twl_i2c_read_u8(u8 mod_no,u8 * val,u8 reg)179 static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) {
180 return twl_i2c_read(mod_no, val, reg, 1);
181 }
182
twl_i2c_write_u16(u8 mod_no,u16 val,u8 reg)183 static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) {
184 val = cpu_to_le16(val);
185 return twl_i2c_write(mod_no, (u8*) &val, reg, 2);
186 }
187
twl_i2c_read_u16(u8 mod_no,u16 * val,u8 reg)188 static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) {
189 int ret;
190 ret = twl_i2c_read(mod_no, (u8*) val, reg, 2);
191 *val = le16_to_cpu(*val);
192 return ret;
193 }
194
195 int twl_get_type(void);
196 int twl_get_version(void);
197 int twl_get_hfclk_rate(void);
198
199 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
200 int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
201
202 /* Card detect Configuration for MMC1 Controller on OMAP4 */
203 #ifdef CONFIG_TWL4030_CORE
204 int twl6030_mmc_card_detect_config(void);
205 #else
twl6030_mmc_card_detect_config(void)206 static inline int twl6030_mmc_card_detect_config(void)
207 {
208 pr_debug("twl6030_mmc_card_detect_config not supported\n");
209 return 0;
210 }
211 #endif
212
213 /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */
214 #ifdef CONFIG_TWL4030_CORE
215 int twl6030_mmc_card_detect(struct device *dev, int slot);
216 #else
twl6030_mmc_card_detect(struct device * dev,int slot)217 static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
218 {
219 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
220 return -EIO;
221 }
222 #endif
223 /*----------------------------------------------------------------------*/
224
225 /*
226 * NOTE: at up to 1024 registers, this is a big chip.
227 *
228 * Avoid putting register declarations in this file, instead of into
229 * a driver-private file, unless some of the registers in a block
230 * need to be shared with other drivers. One example is blocks that
231 * have Secondary IRQ Handler (SIH) registers.
232 */
233
234 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
235 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
236 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
237
238 /*----------------------------------------------------------------------*/
239
240 /*
241 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
242 */
243
244 #define REG_GPIODATAIN1 0x0
245 #define REG_GPIODATAIN2 0x1
246 #define REG_GPIODATAIN3 0x2
247 #define REG_GPIODATADIR1 0x3
248 #define REG_GPIODATADIR2 0x4
249 #define REG_GPIODATADIR3 0x5
250 #define REG_GPIODATAOUT1 0x6
251 #define REG_GPIODATAOUT2 0x7
252 #define REG_GPIODATAOUT3 0x8
253 #define REG_CLEARGPIODATAOUT1 0x9
254 #define REG_CLEARGPIODATAOUT2 0xA
255 #define REG_CLEARGPIODATAOUT3 0xB
256 #define REG_SETGPIODATAOUT1 0xC
257 #define REG_SETGPIODATAOUT2 0xD
258 #define REG_SETGPIODATAOUT3 0xE
259 #define REG_GPIO_DEBEN1 0xF
260 #define REG_GPIO_DEBEN2 0x10
261 #define REG_GPIO_DEBEN3 0x11
262 #define REG_GPIO_CTRL 0x12
263 #define REG_GPIOPUPDCTR1 0x13
264 #define REG_GPIOPUPDCTR2 0x14
265 #define REG_GPIOPUPDCTR3 0x15
266 #define REG_GPIOPUPDCTR4 0x16
267 #define REG_GPIOPUPDCTR5 0x17
268 #define REG_GPIO_ISR1A 0x19
269 #define REG_GPIO_ISR2A 0x1A
270 #define REG_GPIO_ISR3A 0x1B
271 #define REG_GPIO_IMR1A 0x1C
272 #define REG_GPIO_IMR2A 0x1D
273 #define REG_GPIO_IMR3A 0x1E
274 #define REG_GPIO_ISR1B 0x1F
275 #define REG_GPIO_ISR2B 0x20
276 #define REG_GPIO_ISR3B 0x21
277 #define REG_GPIO_IMR1B 0x22
278 #define REG_GPIO_IMR2B 0x23
279 #define REG_GPIO_IMR3B 0x24
280 #define REG_GPIO_EDR1 0x28
281 #define REG_GPIO_EDR2 0x29
282 #define REG_GPIO_EDR3 0x2A
283 #define REG_GPIO_EDR4 0x2B
284 #define REG_GPIO_EDR5 0x2C
285 #define REG_GPIO_SIH_CTRL 0x2D
286
287 /* Up to 18 signals are available as GPIOs, when their
288 * pins are not assigned to another use (such as ULPI/USB).
289 */
290 #define TWL4030_GPIO_MAX 18
291
292 /*----------------------------------------------------------------------*/
293
294 /*Interface Bit Register (INTBR) offsets
295 *(Use TWL_4030_MODULE_INTBR)
296 */
297
298 #define REG_IDCODE_7_0 0x00
299 #define REG_IDCODE_15_8 0x01
300 #define REG_IDCODE_16_23 0x02
301 #define REG_IDCODE_31_24 0x03
302 #define REG_GPPUPDCTR1 0x0F
303 #define REG_UNLOCK_TEST_REG 0x12
304
305 /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
306
307 #define I2C_SCL_CTRL_PU BIT(0)
308 #define I2C_SDA_CTRL_PU BIT(2)
309 #define SR_I2C_SCL_CTRL_PU BIT(4)
310 #define SR_I2C_SDA_CTRL_PU BIT(6)
311
312 #define TWL_EEPROM_R_UNLOCK 0x49
313
314 /*----------------------------------------------------------------------*/
315
316 /*
317 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
318 * ... SIH/interrupt only
319 */
320
321 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
322 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
323 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
324 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
325 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
326 #define TWL4030_KEYPAD_KEYP_EDR 0x16
327 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
328
329 /*----------------------------------------------------------------------*/
330
331 /*
332 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
333 * ... SIH/interrupt only
334 */
335
336 #define TWL4030_MADC_ISR1 0x61
337 #define TWL4030_MADC_IMR1 0x62
338 #define TWL4030_MADC_ISR2 0x63
339 #define TWL4030_MADC_IMR2 0x64
340 #define TWL4030_MADC_SIR 0x65 /* test register */
341 #define TWL4030_MADC_EDR 0x66
342 #define TWL4030_MADC_SIH_CTRL 0x67
343
344 /*----------------------------------------------------------------------*/
345
346 /*
347 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
348 */
349
350 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
351 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
352 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
353 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
354 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
355 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
356 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
357 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
358 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
359 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
360 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
361 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
362 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
363 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
364
365 /*----------------------------------------------------------------------*/
366
367 /*
368 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
369 */
370
371 #define TWL4030_INT_PWR_ISR1 0x0
372 #define TWL4030_INT_PWR_IMR1 0x1
373 #define TWL4030_INT_PWR_ISR2 0x2
374 #define TWL4030_INT_PWR_IMR2 0x3
375 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
376 #define TWL4030_INT_PWR_EDR1 0x5
377 #define TWL4030_INT_PWR_EDR2 0x6
378 #define TWL4030_INT_PWR_SIH_CTRL 0x7
379
380 /*----------------------------------------------------------------------*/
381
382 /*
383 * Accessory Interrupts
384 */
385 #define TWL5031_ACIIMR_LSB 0x05
386 #define TWL5031_ACIIMR_MSB 0x06
387 #define TWL5031_ACIIDR_LSB 0x07
388 #define TWL5031_ACIIDR_MSB 0x08
389 #define TWL5031_ACCISR1 0x0F
390 #define TWL5031_ACCIMR1 0x10
391 #define TWL5031_ACCISR2 0x11
392 #define TWL5031_ACCIMR2 0x12
393 #define TWL5031_ACCSIR 0x13
394 #define TWL5031_ACCEDR1 0x14
395 #define TWL5031_ACCSIHCTRL 0x15
396
397 /*----------------------------------------------------------------------*/
398
399 /*
400 * Battery Charger Controller
401 */
402
403 #define TWL5031_INTERRUPTS_BCIISR1 0x0
404 #define TWL5031_INTERRUPTS_BCIIMR1 0x1
405 #define TWL5031_INTERRUPTS_BCIISR2 0x2
406 #define TWL5031_INTERRUPTS_BCIIMR2 0x3
407 #define TWL5031_INTERRUPTS_BCISIR 0x4
408 #define TWL5031_INTERRUPTS_BCIEDR1 0x5
409 #define TWL5031_INTERRUPTS_BCIEDR2 0x6
410 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
411
412 /*----------------------------------------------------------------------*/
413
414 /*
415 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
416 */
417
418 #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
419 #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
420 #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
421 #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
422 #define TWL4030_PM_MASTER_STS_BOOT 0x04
423 #define TWL4030_PM_MASTER_CFG_BOOT 0x05
424 #define TWL4030_PM_MASTER_SHUNDAN 0x06
425 #define TWL4030_PM_MASTER_BOOT_BCI 0x07
426 #define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
427 #define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
428 #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
429 #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
430 #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
431 #define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
432 #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
433 #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
434 #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
435 #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
436 #define TWL4030_PM_MASTER_STS_P123_STATE 0x13
437 #define TWL4030_PM_MASTER_PB_CFG 0x14
438 #define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
439 #define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
440 #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
441 #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
442 #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
443 #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
444 #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
445 #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
446 #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
447 #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
448 #define TWL4030_PM_MASTER_MEMORY_DATA 0x24
449
450 #define TWL4030_PM_MASTER_KEY_CFG1 0xc0
451 #define TWL4030_PM_MASTER_KEY_CFG2 0x0c
452
453 #define TWL4030_PM_MASTER_KEY_TST1 0xe0
454 #define TWL4030_PM_MASTER_KEY_TST2 0x0e
455
456 #define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
457
458 /*----------------------------------------------------------------------*/
459
460 /* Power bus message definitions */
461
462 /* The TWL4030/5030 splits its power-management resources (the various
463 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
464 * P3. These groups can then be configured to transition between sleep, wait-on
465 * and active states by sending messages to the power bus. See Section 5.4.2
466 * Power Resources of TWL4030 TRM
467 */
468
469 /* Processor groups */
470 #define DEV_GRP_NULL 0x0
471 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
472 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
473 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
474
475 /* Resource groups */
476 #define RES_GRP_RES 0x0 /* Reserved */
477 #define RES_GRP_PP 0x1 /* Power providers */
478 #define RES_GRP_RC 0x2 /* Reset and control */
479 #define RES_GRP_PP_RC 0x3
480 #define RES_GRP_PR 0x4 /* Power references */
481 #define RES_GRP_PP_PR 0x5
482 #define RES_GRP_RC_PR 0x6
483 #define RES_GRP_ALL 0x7 /* All resource groups */
484
485 #define RES_TYPE2_R0 0x0
486 #define RES_TYPE2_R1 0x1
487 #define RES_TYPE2_R2 0x2
488
489 #define RES_TYPE_R0 0x0
490 #define RES_TYPE_ALL 0x7
491
492 /* Resource states */
493 #define RES_STATE_WRST 0xF
494 #define RES_STATE_ACTIVE 0xE
495 #define RES_STATE_SLEEP 0x8
496 #define RES_STATE_OFF 0x0
497
498 /* Power resources */
499
500 /* Power providers */
501 #define RES_VAUX1 1
502 #define RES_VAUX2 2
503 #define RES_VAUX3 3
504 #define RES_VAUX4 4
505 #define RES_VMMC1 5
506 #define RES_VMMC2 6
507 #define RES_VPLL1 7
508 #define RES_VPLL2 8
509 #define RES_VSIM 9
510 #define RES_VDAC 10
511 #define RES_VINTANA1 11
512 #define RES_VINTANA2 12
513 #define RES_VINTDIG 13
514 #define RES_VIO 14
515 #define RES_VDD1 15
516 #define RES_VDD2 16
517 #define RES_VUSB_1V5 17
518 #define RES_VUSB_1V8 18
519 #define RES_VUSB_3V1 19
520 #define RES_VUSBCP 20
521 #define RES_REGEN 21
522 /* Reset and control */
523 #define RES_NRES_PWRON 22
524 #define RES_CLKEN 23
525 #define RES_SYSEN 24
526 #define RES_HFCLKOUT 25
527 #define RES_32KCLKOUT 26
528 #define RES_RESET 27
529 /* Power Reference */
530 #define RES_MAIN_REF 28
531
532 #define TOTAL_RESOURCES 28
533 /*
534 * Power Bus Message Format ... these can be sent individually by Linux,
535 * but are usually part of downloaded scripts that are run when various
536 * power events are triggered.
537 *
538 * Broadcast Message (16 Bits):
539 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
540 * RES_STATE[3:0]
541 *
542 * Singular Message (16 Bits):
543 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
544 */
545
546 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
547 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
548 | (type) << 4 | (state))
549
550 #define MSG_SINGULAR(devgrp, id, state) \
551 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
552
553 #define MSG_BROADCAST_ALL(devgrp, state) \
554 ((devgrp) << 5 | (state))
555
556 #define MSG_BROADCAST_REF MSG_BROADCAST_ALL
557 #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
558 #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
559 /*----------------------------------------------------------------------*/
560
561 struct twl4030_clock_init_data {
562 bool ck32k_lowpwr_enable;
563 };
564
565 struct twl4030_bci_platform_data {
566 int *battery_tmp_tbl;
567 unsigned int tblsize;
568 int bb_uvolt; /* voltage to charge backup battery */
569 int bb_uamp; /* current for backup battery charging */
570 };
571
572 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
573 struct twl4030_gpio_platform_data {
574 /* package the two LED signals as output-only GPIOs? */
575 bool use_leds;
576
577 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
578 u8 mmc_cd;
579
580 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
581 u32 debounce;
582
583 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
584 * should be enabled. Else, if that bit is set in "pulldowns",
585 * that pulldown is enabled. Don't waste power by letting any
586 * digital inputs float...
587 */
588 u32 pullups;
589 u32 pulldowns;
590
591 int (*setup)(struct device *dev,
592 unsigned gpio, unsigned ngpio);
593 int (*teardown)(struct device *dev,
594 unsigned gpio, unsigned ngpio);
595 };
596
597 struct twl4030_madc_platform_data {
598 int irq_line;
599 };
600
601 /* Boards have unique mappings of {row, col} --> keycode.
602 * Column and row are 8 bits each, but range only from 0..7.
603 * a PERSISTENT_KEY is "always on" and never reported.
604 */
605 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
606
607 struct twl4030_keypad_data {
608 const struct matrix_keymap_data *keymap_data;
609 unsigned rows;
610 unsigned cols;
611 bool rep;
612 };
613
614 enum twl4030_usb_mode {
615 T2_USB_MODE_ULPI = 1,
616 T2_USB_MODE_CEA2011_3PIN = 2,
617 };
618
619 struct twl4030_usb_data {
620 enum twl4030_usb_mode usb_mode;
621 unsigned long features;
622
623 int (*phy_init)(struct device *dev);
624 int (*phy_exit)(struct device *dev);
625 /* Power on/off the PHY */
626 int (*phy_power)(struct device *dev, int iD, int on);
627 /* enable/disable phy clocks */
628 int (*phy_set_clock)(struct device *dev, int on);
629 /* suspend/resume of phy */
630 int (*phy_suspend)(struct device *dev, int suspend);
631 };
632
633 struct twl4030_ins {
634 u16 pmb_message;
635 u8 delay;
636 };
637
638 struct twl4030_script {
639 struct twl4030_ins *script;
640 unsigned size;
641 u8 flags;
642 #define TWL4030_WRST_SCRIPT (1<<0)
643 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
644 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
645 #define TWL4030_SLEEP_SCRIPT (1<<3)
646 };
647
648 struct twl4030_resconfig {
649 u8 resource;
650 u8 devgroup; /* Processor group that Power resource belongs to */
651 u8 type; /* Power resource addressed, 6 / broadcast message */
652 u8 type2; /* Power resource addressed, 3 / broadcast message */
653 u8 remap_off; /* off state remapping */
654 u8 remap_sleep; /* sleep state remapping */
655 };
656
657 struct twl4030_power_data {
658 struct twl4030_script **scripts;
659 unsigned num;
660 struct twl4030_resconfig *resource_config;
661 struct twl4030_resconfig *board_config;
662 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
663 bool use_poweroff; /* Board is wired for TWL poweroff */
664 bool ac_charger_quirk; /* Disable AC charger on board */
665 };
666
667 extern int twl4030_remove_script(u8 flags);
668 extern void twl4030_power_off(void);
669
670 struct twl4030_codec_data {
671 unsigned int digimic_delay; /* in ms */
672 unsigned int ramp_delay_value;
673 unsigned int offset_cncl_path;
674 unsigned int hs_extmute:1;
675 int hs_extmute_gpio;
676 };
677
678 struct twl4030_vibra_data {
679 unsigned int coexist;
680 };
681
682 struct twl4030_audio_data {
683 unsigned int audio_mclk;
684 struct twl4030_codec_data *codec;
685 struct twl4030_vibra_data *vibra;
686
687 /* twl6040 */
688 int audpwron_gpio; /* audio power-on gpio */
689 int naudint_irq; /* audio interrupt */
690 unsigned int irq_base;
691 };
692
693 struct twl4030_platform_data {
694 struct twl4030_clock_init_data *clock;
695 struct twl4030_bci_platform_data *bci;
696 struct twl4030_gpio_platform_data *gpio;
697 struct twl4030_madc_platform_data *madc;
698 struct twl4030_keypad_data *keypad;
699 struct twl4030_usb_data *usb;
700 struct twl4030_power_data *power;
701 struct twl4030_audio_data *audio;
702
703 /* Common LDO regulators for TWL4030/TWL6030 */
704 struct regulator_init_data *vdac;
705 struct regulator_init_data *vaux1;
706 struct regulator_init_data *vaux2;
707 struct regulator_init_data *vaux3;
708 struct regulator_init_data *vdd1;
709 struct regulator_init_data *vdd2;
710 struct regulator_init_data *vdd3;
711 /* TWL4030 LDO regulators */
712 struct regulator_init_data *vpll1;
713 struct regulator_init_data *vpll2;
714 struct regulator_init_data *vmmc1;
715 struct regulator_init_data *vmmc2;
716 struct regulator_init_data *vsim;
717 struct regulator_init_data *vaux4;
718 struct regulator_init_data *vio;
719 struct regulator_init_data *vintana1;
720 struct regulator_init_data *vintana2;
721 struct regulator_init_data *vintdig;
722 /* TWL6030 LDO regulators */
723 struct regulator_init_data *vmmc;
724 struct regulator_init_data *vpp;
725 struct regulator_init_data *vusim;
726 struct regulator_init_data *vana;
727 struct regulator_init_data *vcxio;
728 struct regulator_init_data *vusb;
729 struct regulator_init_data *clk32kg;
730 struct regulator_init_data *v1v8;
731 struct regulator_init_data *v2v1;
732 /* TWL6032 LDO regulators */
733 struct regulator_init_data *ldo1;
734 struct regulator_init_data *ldo2;
735 struct regulator_init_data *ldo3;
736 struct regulator_init_data *ldo4;
737 struct regulator_init_data *ldo5;
738 struct regulator_init_data *ldo6;
739 struct regulator_init_data *ldo7;
740 struct regulator_init_data *ldoln;
741 struct regulator_init_data *ldousb;
742 /* TWL6032 DCDC regulators */
743 struct regulator_init_data *smps3;
744 struct regulator_init_data *smps4;
745 struct regulator_init_data *vio6025;
746 };
747
748 struct twl_regulator_driver_data {
749 int (*set_voltage)(void *data, int target_uV);
750 int (*get_voltage)(void *data);
751 void *data;
752 unsigned long features;
753 };
754 /* chip-specific feature flags, for twl_regulator_driver_data.features */
755 #define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */
756 #define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */
757 #define TWL5031 BIT(2) /* twl5031 has different registers */
758 #define TWL6030_CLASS BIT(3) /* TWL6030 class */
759 #define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */
760 #define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible
761 * but not officially supported.
762 * This flag is necessary to
763 * enable them.
764 */
765
766 /*----------------------------------------------------------------------*/
767
768 int twl4030_sih_setup(struct device *dev, int module, int irq_base);
769
770 /* Offsets to Power Registers */
771 #define TWL4030_VDAC_DEV_GRP 0x3B
772 #define TWL4030_VDAC_DEDICATED 0x3E
773 #define TWL4030_VAUX1_DEV_GRP 0x17
774 #define TWL4030_VAUX1_DEDICATED 0x1A
775 #define TWL4030_VAUX2_DEV_GRP 0x1B
776 #define TWL4030_VAUX2_DEDICATED 0x1E
777 #define TWL4030_VAUX3_DEV_GRP 0x1F
778 #define TWL4030_VAUX3_DEDICATED 0x22
779
twl4030charger_usb_en(int enable)780 static inline int twl4030charger_usb_en(int enable) { return 0; }
781
782 /*----------------------------------------------------------------------*/
783
784 /* Linux-specific regulator identifiers ... for now, we only support
785 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
786 * need to tie into hardware based voltage scaling (cpufreq etc), while
787 * VIO is generally fixed.
788 */
789
790 /* TWL4030 SMPS/LDO's */
791 /* EXTERNAL dc-to-dc buck converters */
792 #define TWL4030_REG_VDD1 0
793 #define TWL4030_REG_VDD2 1
794 #define TWL4030_REG_VIO 2
795
796 /* EXTERNAL LDOs */
797 #define TWL4030_REG_VDAC 3
798 #define TWL4030_REG_VPLL1 4
799 #define TWL4030_REG_VPLL2 5 /* not on all chips */
800 #define TWL4030_REG_VMMC1 6
801 #define TWL4030_REG_VMMC2 7 /* not on all chips */
802 #define TWL4030_REG_VSIM 8 /* not on all chips */
803 #define TWL4030_REG_VAUX1 9 /* not on all chips */
804 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
805 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
806 #define TWL4030_REG_VAUX3 12 /* not on all chips */
807 #define TWL4030_REG_VAUX4 13 /* not on all chips */
808
809 /* INTERNAL LDOs */
810 #define TWL4030_REG_VINTANA1 14
811 #define TWL4030_REG_VINTANA2 15
812 #define TWL4030_REG_VINTDIG 16
813 #define TWL4030_REG_VUSB1V5 17
814 #define TWL4030_REG_VUSB1V8 18
815 #define TWL4030_REG_VUSB3V1 19
816
817 /* TWL6030 SMPS/LDO's */
818 /* EXTERNAL dc-to-dc buck convertor controllable via SR */
819 #define TWL6030_REG_VDD1 30
820 #define TWL6030_REG_VDD2 31
821 #define TWL6030_REG_VDD3 32
822
823 /* Non SR compliant dc-to-dc buck convertors */
824 #define TWL6030_REG_VMEM 33
825 #define TWL6030_REG_V2V1 34
826 #define TWL6030_REG_V1V29 35
827 #define TWL6030_REG_V1V8 36
828
829 /* EXTERNAL LDOs */
830 #define TWL6030_REG_VAUX1_6030 37
831 #define TWL6030_REG_VAUX2_6030 38
832 #define TWL6030_REG_VAUX3_6030 39
833 #define TWL6030_REG_VMMC 40
834 #define TWL6030_REG_VPP 41
835 #define TWL6030_REG_VUSIM 42
836 #define TWL6030_REG_VANA 43
837 #define TWL6030_REG_VCXIO 44
838 #define TWL6030_REG_VDAC 45
839 #define TWL6030_REG_VUSB 46
840
841 /* INTERNAL LDOs */
842 #define TWL6030_REG_VRTC 47
843 #define TWL6030_REG_CLK32KG 48
844
845 /* LDOs on 6025 have different names */
846 #define TWL6032_REG_LDO2 49
847 #define TWL6032_REG_LDO4 50
848 #define TWL6032_REG_LDO3 51
849 #define TWL6032_REG_LDO5 52
850 #define TWL6032_REG_LDO1 53
851 #define TWL6032_REG_LDO7 54
852 #define TWL6032_REG_LDO6 55
853 #define TWL6032_REG_LDOLN 56
854 #define TWL6032_REG_LDOUSB 57
855
856 /* 6025 DCDC supplies */
857 #define TWL6032_REG_SMPS3 58
858 #define TWL6032_REG_SMPS4 59
859 #define TWL6032_REG_VIO 60
860
861
862 #endif /* End of __TWL4030_H */
863
