1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2021 Gerhard Engleder <gerhard@engleder-embedded.com> */ 3 4 /* Hardware definition of TSNEP and EtherCAT MAC device */ 5 6 #ifndef _TSNEP_HW_H 7 #define _TSNEP_HW_H 8 9 #include <linux/types.h> 10 11 /* type */ 12 #define ECM_TYPE 0x0000 13 #define ECM_REVISION_MASK 0x000000FF 14 #define ECM_REVISION_SHIFT 0 15 #define ECM_VERSION_MASK 0x0000FF00 16 #define ECM_VERSION_SHIFT 8 17 #define ECM_QUEUE_COUNT_MASK 0x00070000 18 #define ECM_QUEUE_COUNT_SHIFT 16 19 #define ECM_GATE_CONTROL 0x02000000 20 21 /* system time */ 22 #define ECM_SYSTEM_TIME_LOW 0x0008 23 #define ECM_SYSTEM_TIME_HIGH 0x000C 24 25 /* clock */ 26 #define ECM_CLOCK_RATE 0x0010 27 #define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF 28 #define ECM_CLOCK_RATE_OFFSET_SIGN 0x80000000 29 30 /* interrupt */ 31 #define ECM_INT_ENABLE 0x0018 32 #define ECM_INT_ACTIVE 0x001C 33 #define ECM_INT_ACKNOWLEDGE 0x001C 34 #define ECM_INT_LINK 0x00000020 35 #define ECM_INT_TX_0 0x00000100 36 #define ECM_INT_RX_0 0x00000200 37 #define ECM_INT_TXRX_SHIFT 2 38 #define ECM_INT_ALL 0x7FFFFFFF 39 #define ECM_INT_DISABLE 0x80000000 40 41 /* reset */ 42 #define ECM_RESET 0x0020 43 #define ECM_RESET_COMMON 0x00000001 44 #define ECM_RESET_CHANNEL 0x00000100 45 #define ECM_RESET_TXRX 0x00010000 46 47 /* counter */ 48 #define ECM_COUNTER_LOW 0x0028 49 #define ECM_COUNTER_HIGH 0x002C 50 51 /* control and status */ 52 #define ECM_STATUS 0x0080 53 #define ECM_LINK_MODE_OFF 0x01000000 54 #define ECM_LINK_MODE_100 0x02000000 55 #define ECM_LINK_MODE_1000 0x04000000 56 #define ECM_NO_LINK 0x01000000 57 #define ECM_LINK_MODE_MASK 0x06000000 58 59 /* management data */ 60 #define ECM_MD_CONTROL 0x0084 61 #define ECM_MD_STATUS 0x0084 62 #define ECM_MD_PREAMBLE 0x00000001 63 #define ECM_MD_READ 0x00000004 64 #define ECM_MD_WRITE 0x00000002 65 #define ECM_MD_ADDR_MASK 0x000000F8 66 #define ECM_MD_ADDR_SHIFT 3 67 #define ECM_MD_PHY_ADDR_MASK 0x00001F00 68 #define ECM_MD_PHY_ADDR_SHIFT 8 69 #define ECM_MD_BUSY 0x00000001 70 #define ECM_MD_DATA_MASK 0xFFFF0000 71 #define ECM_MD_DATA_SHIFT 16 72 73 /* statistic */ 74 #define ECM_STAT 0x00B0 75 #define ECM_STAT_RX_ERR_MASK 0x000000FF 76 #define ECM_STAT_RX_ERR_SHIFT 0 77 #define ECM_STAT_INV_FRM_MASK 0x0000FF00 78 #define ECM_STAT_INV_FRM_SHIFT 8 79 #define ECM_STAT_FWD_RX_ERR_MASK 0x00FF0000 80 #define ECM_STAT_FWD_RX_ERR_SHIFT 16 81 82 /* tsnep */ 83 #define TSNEP_MAC_SIZE 0x4000 84 #define TSNEP_QUEUE_SIZE 0x1000 85 #define TSNEP_QUEUE(n) ({ typeof(n) __n = (n); \ 86 (__n) == 0 ? \ 87 0 : \ 88 TSNEP_MAC_SIZE + TSNEP_QUEUE_SIZE * ((__n) - 1); }) 89 #define TSNEP_MAX_QUEUES 8 90 #define TSNEP_MAX_FRAME_SIZE (2 * 1024) /* hardware supports actually 16k */ 91 #define TSNEP_DESC_SIZE 256 92 #define TSNEP_DESC_OFFSET 128 93 94 /* tsnep register */ 95 #define TSNEP_INFO 0x0100 96 #define TSNEP_INFO_TX_TIME 0x00010000 97 #define TSNEP_CONTROL 0x0108 98 #define TSNEP_CONTROL_TX_RESET 0x00000001 99 #define TSNEP_CONTROL_TX_ENABLE 0x00000002 100 #define TSNEP_CONTROL_TX_DMA_ERROR 0x00000010 101 #define TSNEP_CONTROL_TX_DESC_ERROR 0x00000020 102 #define TSNEP_CONTROL_RX_RESET 0x00000100 103 #define TSNEP_CONTROL_RX_ENABLE 0x00000200 104 #define TSNEP_CONTROL_RX_DISABLE 0x00000400 105 #define TSNEP_CONTROL_RX_DMA_ERROR 0x00001000 106 #define TSNEP_CONTROL_RX_DESC_ERROR 0x00002000 107 #define TSNEP_TX_DESC_ADDR_LOW 0x0140 108 #define TSNEP_TX_DESC_ADDR_HIGH 0x0144 109 #define TSNEP_RX_DESC_ADDR_LOW 0x0180 110 #define TSNEP_RX_DESC_ADDR_HIGH 0x0184 111 #define TSNEP_RESET_OWNER_COUNTER 0x01 112 #define TSNEP_RX_STATISTIC 0x0190 113 #define TSNEP_RX_STATISTIC_NO_DESC_MASK 0x000000FF 114 #define TSNEP_RX_STATISTIC_NO_DESC_SHIFT 0 115 #define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_MASK 0x0000FF00 116 #define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_SHIFT 8 117 #define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_MASK 0x00FF0000 118 #define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_SHIFT 16 119 #define TSNEP_RX_STATISTIC_INVALID_FRAME_MASK 0xFF000000 120 #define TSNEP_RX_STATISTIC_INVALID_FRAME_SHIFT 24 121 #define TSNEP_RX_STATISTIC_NO_DESC 0x0190 122 #define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL 0x0191 123 #define TSNEP_RX_STATISTIC_FIFO_OVERFLOW 0x0192 124 #define TSNEP_RX_STATISTIC_INVALID_FRAME 0x0193 125 #define TSNEP_MAC_ADDRESS_LOW 0x0800 126 #define TSNEP_MAC_ADDRESS_HIGH 0x0804 127 #define TSNEP_RX_FILTER 0x0806 128 #define TSNEP_RX_FILTER_ACCEPT_ALL_MULTICASTS 0x0001 129 #define TSNEP_RX_FILTER_ACCEPT_ALL_UNICASTS 0x0002 130 #define TSNEP_GC 0x0808 131 #define TSNEP_GC_ENABLE_A 0x00000002 132 #define TSNEP_GC_ENABLE_B 0x00000004 133 #define TSNEP_GC_DISABLE 0x00000008 134 #define TSNEP_GC_ENABLE_TIMEOUT 0x00000010 135 #define TSNEP_GC_ACTIVE_A 0x00000002 136 #define TSNEP_GC_ACTIVE_B 0x00000004 137 #define TSNEP_GC_CHANGE_AB 0x00000008 138 #define TSNEP_GC_TIMEOUT_ACTIVE 0x00000010 139 #define TSNEP_GC_TIMEOUT_SIGNAL 0x00000020 140 #define TSNEP_GC_LIST_ERROR 0x00000080 141 #define TSNEP_GC_OPEN 0x00FF0000 142 #define TSNEP_GC_OPEN_SHIFT 16 143 #define TSNEP_GC_NEXT_OPEN 0xFF000000 144 #define TSNEP_GC_NEXT_OPEN_SHIFT 24 145 #define TSNEP_GC_TIMEOUT 131072 146 #define TSNEP_GC_TIME 0x080C 147 #define TSNEP_GC_CHANGE 0x0810 148 #define TSNEP_GCL_A 0x2000 149 #define TSNEP_GCL_B 0x2800 150 #define TSNEP_GCL_SIZE SZ_2K 151 #define TSNEP_RX_ASSIGN 0x0840 152 #define TSNEP_RX_ASSIGN_ACTIVE 0x00000001 153 #define TSNEP_RX_ASSIGN_QUEUE_MASK 0x00000006 154 #define TSNEP_RX_ASSIGN_QUEUE_SHIFT 1 155 #define TSNEP_RX_ASSIGN_OFFSET 1 156 #define TSNEP_RX_ASSIGN_ETHER_TYPE 0x0880 157 #define TSNEP_RX_ASSIGN_ETHER_TYPE_OFFSET 2 158 #define TSNEP_RX_ASSIGN_ETHER_TYPE_COUNT 2 159 160 /* tsnep gate control list operation */ 161 struct tsnep_gcl_operation { 162 u32 properties; 163 u32 interval; 164 }; 165 166 #define TSNEP_GCL_COUNT (TSNEP_GCL_SIZE / sizeof(struct tsnep_gcl_operation)) 167 #define TSNEP_GCL_MASK 0x000000FF 168 #define TSNEP_GCL_INSERT 0x20000000 169 #define TSNEP_GCL_CHANGE 0x40000000 170 #define TSNEP_GCL_LAST 0x80000000 171 #define TSNEP_GCL_MIN_INTERVAL 32 172 173 /* tsnep TX/RX descriptor */ 174 #define TSNEP_DESC_SIZE 256 175 #define TSNEP_DESC_SIZE_DATA_AFTER 2048 176 #define TSNEP_DESC_OFFSET 128 177 #define TSNEP_DESC_OWNER_COUNTER_MASK 0xC0000000 178 #define TSNEP_DESC_OWNER_COUNTER_SHIFT 30 179 #define TSNEP_DESC_LENGTH_MASK 0x00003FFF 180 #define TSNEP_DESC_INTERRUPT_FLAG 0x00040000 181 #define TSNEP_DESC_EXTENDED_WRITEBACK_FLAG 0x00080000 182 #define TSNEP_DESC_NO_LINK_FLAG 0x01000000 183 184 /* tsnep TX descriptor */ 185 struct tsnep_tx_desc { 186 __le32 properties; 187 __le32 more_properties; 188 __le32 reserved[2]; 189 __le64 next; 190 __le64 tx; 191 }; 192 193 #define TSNEP_TX_DESC_OWNER_MASK 0xE0000000 194 #define TSNEP_TX_DESC_OWNER_USER_FLAG 0x20000000 195 #define TSNEP_TX_DESC_LAST_FRAGMENT_FLAG 0x00010000 196 #define TSNEP_TX_DESC_DATA_AFTER_DESC_FLAG 0x00020000 197 198 /* tsnep TX descriptor writeback */ 199 struct tsnep_tx_desc_wb { 200 __le32 properties; 201 __le32 reserved1; 202 __le64 counter; 203 __le64 timestamp; 204 __le32 dma_delay; 205 __le32 reserved2; 206 }; 207 208 #define TSNEP_TX_DESC_UNDERRUN_ERROR_FLAG 0x00010000 209 #define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_MASK 0x0000FFFC 210 #define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_SHIFT 2 211 #define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_MASK 0xFFFC0000 212 #define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_SHIFT 18 213 #define TSNEP_TX_DESC_DMA_DELAY_NS 64 214 215 /* tsnep RX descriptor */ 216 struct tsnep_rx_desc { 217 __le32 properties; 218 __le32 reserved[3]; 219 __le64 next; 220 __le64 rx; 221 }; 222 223 #define TSNEP_RX_DESC_BUFFER_SIZE_MASK 0x00003FFC 224 225 /* tsnep RX descriptor writeback */ 226 struct tsnep_rx_desc_wb { 227 __le32 properties; 228 __le32 reserved[7]; 229 }; 230 231 /* tsnep RX inline meta */ 232 struct tsnep_rx_inline { 233 __le64 counter; 234 __le64 timestamp; 235 }; 236 237 #define TSNEP_RX_INLINE_METADATA_SIZE (sizeof(struct tsnep_rx_inline)) 238 239 #endif /* _TSNEP_HW_H */ 240
