1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments System Control Interface Protocol
4 *
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6 * Nishanth Menon
7 */
8
9 #ifndef __TISCI_PROTOCOL_H
10 #define __TISCI_PROTOCOL_H
11
12 /**
13 * struct ti_sci_version_info - version information structure
14 * @abi_major: Major ABI version. Change here implies risk of backward
15 * compatibility break.
16 * @abi_minor: Minor ABI version. Change here implies new feature addition,
17 * or compatible change in ABI.
18 * @firmware_revision: Firmware revision (not usually used).
19 * @firmware_description: Firmware description (not usually used).
20 */
21 struct ti_sci_version_info {
22 u8 abi_major;
23 u8 abi_minor;
24 u16 firmware_revision;
25 char firmware_description[32];
26 };
27
28 struct ti_sci_handle;
29
30 /**
31 * struct ti_sci_core_ops - SoC Core Operations
32 * @reboot_device: Reboot the SoC
33 * Returns 0 for successful request(ideally should never return),
34 * else returns corresponding error value.
35 */
36 struct ti_sci_core_ops {
37 int (*reboot_device)(const struct ti_sci_handle *handle);
38 };
39
40 /**
41 * struct ti_sci_dev_ops - Device control operations
42 * @get_device: Command to request for device managed by TISCI
43 * Returns 0 for successful exclusive request, else returns
44 * corresponding error message.
45 * @idle_device: Command to idle a device managed by TISCI
46 * Returns 0 for successful exclusive request, else returns
47 * corresponding error message.
48 * @put_device: Command to release a device managed by TISCI
49 * Returns 0 for successful release, else returns corresponding
50 * error message.
51 * @is_valid: Check if the device ID is a valid ID.
52 * Returns 0 if the ID is valid, else returns corresponding error.
53 * @get_context_loss_count: Command to retrieve context loss counter - this
54 * increments every time the device looses context. Overflow
55 * is possible.
56 * - count: pointer to u32 which will retrieve counter
57 * Returns 0 for successful information request and count has
58 * proper data, else returns corresponding error message.
59 * @is_idle: Reports back about device idle state
60 * - req_state: Returns requested idle state
61 * Returns 0 for successful information request and req_state and
62 * current_state has proper data, else returns corresponding error
63 * message.
64 * @is_stop: Reports back about device stop state
65 * - req_state: Returns requested stop state
66 * - current_state: Returns current stop state
67 * Returns 0 for successful information request and req_state and
68 * current_state has proper data, else returns corresponding error
69 * message.
70 * @is_on: Reports back about device ON(or active) state
71 * - req_state: Returns requested ON state
72 * - current_state: Returns current ON state
73 * Returns 0 for successful information request and req_state and
74 * current_state has proper data, else returns corresponding error
75 * message.
76 * @is_transitioning: Reports back if the device is in the middle of transition
77 * of state.
78 * -current_state: Returns 'true' if currently transitioning.
79 * @set_device_resets: Command to configure resets for device managed by TISCI.
80 * -reset_state: Device specific reset bit field
81 * Returns 0 for successful request, else returns
82 * corresponding error message.
83 * @get_device_resets: Command to read state of resets for device managed
84 * by TISCI.
85 * -reset_state: pointer to u32 which will retrieve resets
86 * Returns 0 for successful request, else returns
87 * corresponding error message.
88 *
89 * NOTE: for all these functions, the following parameters are generic in
90 * nature:
91 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
92 * -id: Device Identifier
93 *
94 * Request for the device - NOTE: the client MUST maintain integrity of
95 * usage count by balancing get_device with put_device. No refcounting is
96 * managed by driver for that purpose.
97 */
98 struct ti_sci_dev_ops {
99 int (*get_device)(const struct ti_sci_handle *handle, u32 id);
100 int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
101 int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
102 int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
103 u32 id);
104 int (*put_device)(const struct ti_sci_handle *handle, u32 id);
105 int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
106 int (*get_context_loss_count)(const struct ti_sci_handle *handle,
107 u32 id, u32 *count);
108 int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
109 bool *requested_state);
110 int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
111 bool *req_state, bool *current_state);
112 int (*is_on)(const struct ti_sci_handle *handle, u32 id,
113 bool *req_state, bool *current_state);
114 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
115 bool *current_state);
116 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
117 u32 reset_state);
118 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
119 u32 *reset_state);
120 };
121
122 /**
123 * struct ti_sci_clk_ops - Clock control operations
124 * @get_clock: Request for activation of clock and manage by processor
125 * - needs_ssc: 'true' if Spread Spectrum clock is desired.
126 * - can_change_freq: 'true' if frequency change is desired.
127 * - enable_input_term: 'true' if input termination is desired.
128 * @idle_clock: Request for Idling a clock managed by processor
129 * @put_clock: Release the clock to be auto managed by TISCI
130 * @is_auto: Is the clock being auto managed
131 * - req_state: state indicating if the clock is auto managed
132 * @is_on: Is the clock ON
133 * - req_state: if the clock is requested to be forced ON
134 * - current_state: if the clock is currently ON
135 * @is_off: Is the clock OFF
136 * - req_state: if the clock is requested to be forced OFF
137 * - current_state: if the clock is currently Gated
138 * @set_parent: Set the clock source of a specific device clock
139 * - parent_id: Parent clock identifier to set.
140 * @get_parent: Get the current clock source of a specific device clock
141 * - parent_id: Parent clock identifier which is the parent.
142 * @get_num_parents: Get the number of parents of the current clock source
143 * - num_parents: returns the number of parent clocks.
144 * @get_best_match_freq: Find a best matching frequency for a frequency
145 * range.
146 * - match_freq: Best matching frequency in Hz.
147 * @set_freq: Set the Clock frequency
148 * @get_freq: Get the Clock frequency
149 * - current_freq: Frequency in Hz that the clock is at.
150 *
151 * NOTE: for all these functions, the following parameters are generic in
152 * nature:
153 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
154 * -did: Device identifier this request is for
155 * -cid: Clock identifier for the device for this request.
156 * Each device has it's own set of clock inputs. This indexes
157 * which clock input to modify.
158 * -min_freq: The minimum allowable frequency in Hz. This is the minimum
159 * allowable programmed frequency and does not account for clock
160 * tolerances and jitter.
161 * -target_freq: The target clock frequency in Hz. A frequency will be
162 * processed as close to this target frequency as possible.
163 * -max_freq: The maximum allowable frequency in Hz. This is the maximum
164 * allowable programmed frequency and does not account for clock
165 * tolerances and jitter.
166 *
167 * Request for the clock - NOTE: the client MUST maintain integrity of
168 * usage count by balancing get_clock with put_clock. No refcounting is
169 * managed by driver for that purpose.
170 */
171 struct ti_sci_clk_ops {
172 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid,
173 bool needs_ssc, bool can_change_freq,
174 bool enable_input_term);
175 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
176 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
177 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid,
178 bool *req_state);
179 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid,
180 bool *req_state, bool *current_state);
181 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid,
182 bool *req_state, bool *current_state);
183 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
184 u32 parent_id);
185 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
186 u32 *parent_id);
187 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
188 u32 cid, u32 *num_parents);
189 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
190 u32 cid, u64 min_freq, u64 target_freq,
191 u64 max_freq, u64 *match_freq);
192 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
193 u64 min_freq, u64 target_freq, u64 max_freq);
194 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
195 u64 *current_freq);
196 };
197
198 /**
199 * struct ti_sci_rm_core_ops - Resource management core operations
200 * @get_range: Get a range of resources belonging to ti sci host.
201 * @get_rage_from_shost: Get a range of resources belonging to
202 * specified host id.
203 * - s_host: Host processing entity to which the
204 * resources are allocated
205 *
206 * NOTE: for these functions, all the parameters are consolidated and defined
207 * as below:
208 * - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
209 * - dev_id: TISCI device ID.
210 * - subtype: Resource assignment subtype that is being requested
211 * from the given device.
212 * - range_start: Start index of the resource range
213 * - range_end: Number of resources in the range
214 */
215 struct ti_sci_rm_core_ops {
216 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
217 u8 subtype, u16 *range_start, u16 *range_num);
218 int (*get_range_from_shost)(const struct ti_sci_handle *handle,
219 u32 dev_id, u8 subtype, u8 s_host,
220 u16 *range_start, u16 *range_num);
221 };
222
223 #define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0
224 #define TI_SCI_RESASG_SUBTYPE_IA_VINT 0xa
225 #define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT 0xd
226 /**
227 * struct ti_sci_rm_irq_ops: IRQ management operations
228 * @set_irq: Set an IRQ route between the requested source
229 * and destination
230 * @set_event_map: Set an Event based peripheral irq to Interrupt
231 * Aggregator.
232 * @free_irq: Free an IRQ route between the requested source
233 * and destination.
234 * @free_event_map: Free an event based peripheral irq to Interrupt
235 * Aggregator.
236 */
237 struct ti_sci_rm_irq_ops {
238 int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
239 u16 src_index, u16 dst_id, u16 dst_host_irq);
240 int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
241 u16 src_index, u16 ia_id, u16 vint,
242 u16 global_event, u8 vint_status_bit);
243 int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
244 u16 src_index, u16 dst_id, u16 dst_host_irq);
245 int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
246 u16 src_index, u16 ia_id, u16 vint,
247 u16 global_event, u8 vint_status_bit);
248 };
249
250 /* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
251 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
252 /* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
253 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
254 /* RA config.count parameter is valid for RM ring configure TI_SCI message */
255 #define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
256 /* RA config.mode parameter is valid for RM ring configure TI_SCI message */
257 #define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
258 /* RA config.size parameter is valid for RM ring configure TI_SCI message */
259 #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
260 /* RA config.order_id parameter is valid for RM ring configure TISCI message */
261 #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
262
263 #define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
264 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
265 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
266 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
267 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
268 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
269
270 /**
271 * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
272 * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
273 * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
274 * configuration
275 */
276 struct ti_sci_rm_ringacc_ops {
277 int (*config)(const struct ti_sci_handle *handle,
278 u32 valid_params, u16 nav_id, u16 index,
279 u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
280 u8 size, u8 order_id
281 );
282 int (*get_config)(const struct ti_sci_handle *handle,
283 u32 nav_id, u32 index, u8 *mode,
284 u32 *addr_lo, u32 *addr_hi, u32 *count,
285 u8 *size, u8 *order_id);
286 };
287
288 /**
289 * struct ti_sci_rm_psil_ops - PSI-L thread operations
290 * @pair: pair PSI-L source thread to a destination thread.
291 * If the src_thread is mapped to UDMA tchan, the corresponding channel's
292 * TCHAN_THRD_ID register is updated.
293 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
294 * RCHAN_THRD_ID register is updated.
295 * @unpair: unpair PSI-L source thread from a destination thread.
296 * If the src_thread is mapped to UDMA tchan, the corresponding channel's
297 * TCHAN_THRD_ID register is cleared.
298 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
299 * RCHAN_THRD_ID register is cleared.
300 */
301 struct ti_sci_rm_psil_ops {
302 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
303 u32 src_thread, u32 dst_thread);
304 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
305 u32 src_thread, u32 dst_thread);
306 };
307
308 /* UDMAP channel types */
309 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
310 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
311 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
312 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
313 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
314 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
315
316 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
317 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
318
319 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
320 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
321 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
322
323 /* UDMAP TX/RX channel valid_params common declarations */
324 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
325 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
326 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
327 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
328 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
329 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
330 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
331 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
332 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
333 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
334
335 /**
336 * Configures a Navigator Subsystem UDMAP transmit channel
337 *
338 * Configures a Navigator Subsystem UDMAP transmit channel registers.
339 * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
340 */
341 struct ti_sci_msg_rm_udmap_tx_ch_cfg {
342 u32 valid_params;
343 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
344 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
345 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
346 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
347 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
348 u16 nav_id;
349 u16 index;
350 u8 tx_pause_on_err;
351 u8 tx_filt_einfo;
352 u8 tx_filt_pswords;
353 u8 tx_atype;
354 u8 tx_chan_type;
355 u8 tx_supr_tdpkt;
356 u16 tx_fetch_size;
357 u8 tx_credit_count;
358 u16 txcq_qnum;
359 u8 tx_priority;
360 u8 tx_qos;
361 u8 tx_orderid;
362 u16 fdepth;
363 u8 tx_sched_priority;
364 u8 tx_burst_size;
365 };
366
367 /**
368 * Configures a Navigator Subsystem UDMAP receive channel
369 *
370 * Configures a Navigator Subsystem UDMAP receive channel registers.
371 * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
372 */
373 struct ti_sci_msg_rm_udmap_rx_ch_cfg {
374 u32 valid_params;
375 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
376 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
377 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
378 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
379 u16 nav_id;
380 u16 index;
381 u16 rx_fetch_size;
382 u16 rxcq_qnum;
383 u8 rx_priority;
384 u8 rx_qos;
385 u8 rx_orderid;
386 u8 rx_sched_priority;
387 u16 flowid_start;
388 u16 flowid_cnt;
389 u8 rx_pause_on_err;
390 u8 rx_atype;
391 u8 rx_chan_type;
392 u8 rx_ignore_short;
393 u8 rx_ignore_long;
394 u8 rx_burst_size;
395 };
396
397 /**
398 * Configures a Navigator Subsystem UDMAP receive flow
399 *
400 * Configures a Navigator Subsystem UDMAP receive flow's registers.
401 * See @tis_ci_msg_rm_udmap_flow_cfg_req
402 */
403 struct ti_sci_msg_rm_udmap_flow_cfg {
404 u32 valid_params;
405 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
406 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
407 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
408 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
409 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
410 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
411 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
412 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
413 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
414 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
415 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
416 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
417 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
418 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
419 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
420 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
421 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
422 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
423 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
424 u16 nav_id;
425 u16 flow_index;
426 u8 rx_einfo_present;
427 u8 rx_psinfo_present;
428 u8 rx_error_handling;
429 u8 rx_desc_type;
430 u16 rx_sop_offset;
431 u16 rx_dest_qnum;
432 u8 rx_src_tag_hi;
433 u8 rx_src_tag_lo;
434 u8 rx_dest_tag_hi;
435 u8 rx_dest_tag_lo;
436 u8 rx_src_tag_hi_sel;
437 u8 rx_src_tag_lo_sel;
438 u8 rx_dest_tag_hi_sel;
439 u8 rx_dest_tag_lo_sel;
440 u16 rx_fdq0_sz0_qnum;
441 u16 rx_fdq1_qnum;
442 u16 rx_fdq2_qnum;
443 u16 rx_fdq3_qnum;
444 u8 rx_ps_location;
445 };
446
447 /**
448 * struct ti_sci_rm_udmap_ops - UDMA Management operations
449 * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
450 * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
451 * @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
452 */
453 struct ti_sci_rm_udmap_ops {
454 int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
455 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
456 int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
457 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
458 int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
459 const struct ti_sci_msg_rm_udmap_flow_cfg *params);
460 };
461
462 /**
463 * struct ti_sci_proc_ops - Processor Control operations
464 * @request: Request to control a physical processor. The requesting host
465 * should be in the processor access list
466 * @release: Relinquish a physical processor control
467 * @handover: Handover a physical processor control to another host
468 * in the permitted list
469 * @set_config: Set base configuration of a processor
470 * @set_control: Setup limited control flags in specific cases
471 * @get_status: Get the state of physical processor
472 *
473 * NOTE: The following paramteres are generic in nature for all these ops,
474 * -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
475 * -pid: Processor ID
476 * -hid: Host ID
477 */
478 struct ti_sci_proc_ops {
479 int (*request)(const struct ti_sci_handle *handle, u8 pid);
480 int (*release)(const struct ti_sci_handle *handle, u8 pid);
481 int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
482 int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
483 u64 boot_vector, u32 cfg_set, u32 cfg_clr);
484 int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
485 u32 ctrl_set, u32 ctrl_clr);
486 int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
487 u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
488 u32 *status_flags);
489 };
490
491 /**
492 * struct ti_sci_ops - Function support for TI SCI
493 * @dev_ops: Device specific operations
494 * @clk_ops: Clock specific operations
495 * @rm_core_ops: Resource management core operations.
496 * @rm_irq_ops: IRQ management specific operations
497 * @proc_ops: Processor Control specific operations
498 */
499 struct ti_sci_ops {
500 struct ti_sci_core_ops core_ops;
501 struct ti_sci_dev_ops dev_ops;
502 struct ti_sci_clk_ops clk_ops;
503 struct ti_sci_rm_core_ops rm_core_ops;
504 struct ti_sci_rm_irq_ops rm_irq_ops;
505 struct ti_sci_rm_ringacc_ops rm_ring_ops;
506 struct ti_sci_rm_psil_ops rm_psil_ops;
507 struct ti_sci_rm_udmap_ops rm_udmap_ops;
508 struct ti_sci_proc_ops proc_ops;
509 };
510
511 /**
512 * struct ti_sci_handle - Handle returned to TI SCI clients for usage.
513 * @version: structure containing version information
514 * @ops: operations that are made available to TI SCI clients
515 */
516 struct ti_sci_handle {
517 struct ti_sci_version_info version;
518 struct ti_sci_ops ops;
519 };
520
521 #define TI_SCI_RESOURCE_NULL 0xffff
522
523 /**
524 * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
525 * @start: Start index of the resource.
526 * @num: Number of resources.
527 * @res_map: Bitmap to manage the allocation of these resources.
528 */
529 struct ti_sci_resource_desc {
530 u16 start;
531 u16 num;
532 unsigned long *res_map;
533 };
534
535 /**
536 * struct ti_sci_resource - Structure representing a resource assigned
537 * to a device.
538 * @sets: Number of sets available from this resource type
539 * @lock: Lock to guard the res map in each set.
540 * @desc: Array of resource descriptors.
541 */
542 struct ti_sci_resource {
543 u16 sets;
544 raw_spinlock_t lock;
545 struct ti_sci_resource_desc *desc;
546 };
547
548 #if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
549 const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
550 int ti_sci_put_handle(const struct ti_sci_handle *handle);
551 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
552 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
553 const char *property);
554 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
555 const char *property);
556 u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
557 void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
558 u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
559 struct ti_sci_resource *
560 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
561 struct device *dev, u32 dev_id, char *of_prop);
562 struct ti_sci_resource *
563 devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
564 u32 dev_id, u32 sub_type);
565
566 #else /* CONFIG_TI_SCI_PROTOCOL */
567
ti_sci_get_handle(struct device * dev)568 static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
569 {
570 return ERR_PTR(-EINVAL);
571 }
572
ti_sci_put_handle(const struct ti_sci_handle * handle)573 static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
574 {
575 return -EINVAL;
576 }
577
578 static inline
devm_ti_sci_get_handle(struct device * dev)579 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
580 {
581 return ERR_PTR(-EINVAL);
582 }
583
584 static inline
ti_sci_get_by_phandle(struct device_node * np,const char * property)585 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
586 const char *property)
587 {
588 return ERR_PTR(-EINVAL);
589 }
590
591 static inline
devm_ti_sci_get_by_phandle(struct device * dev,const char * property)592 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
593 const char *property)
594 {
595 return ERR_PTR(-EINVAL);
596 }
597
ti_sci_get_free_resource(struct ti_sci_resource * res)598 static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
599 {
600 return TI_SCI_RESOURCE_NULL;
601 }
602
ti_sci_release_resource(struct ti_sci_resource * res,u16 id)603 static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
604 {
605 }
606
ti_sci_get_num_resources(struct ti_sci_resource * res)607 static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
608 {
609 return 0;
610 }
611
612 static inline struct ti_sci_resource *
devm_ti_sci_get_of_resource(const struct ti_sci_handle * handle,struct device * dev,u32 dev_id,char * of_prop)613 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
614 struct device *dev, u32 dev_id, char *of_prop)
615 {
616 return ERR_PTR(-EINVAL);
617 }
618
619 static inline struct ti_sci_resource *
620 devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
621 u32 dev_id, u32 sub_type);
622 {
623 return ERR_PTR(-EINVAL);
624 }
625 #endif /* CONFIG_TI_SCI_PROTOCOL */
626
627 #endif /* __TISCI_PROTOCOL_H */
628
