1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 25 #define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 26 27 // *** IMPORTANT *** 28 // SMU TEAM: Always increment the interface version if 29 // any structure is changed in this file 30 #define SMU11_DRIVER_IF_VERSION 0x3B 31 32 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 7 33 34 #define NUM_GFXCLK_DPM_LEVELS 16 35 #define NUM_SMNCLK_DPM_LEVELS 2 36 #define NUM_SOCCLK_DPM_LEVELS 8 37 #define NUM_MP0CLK_DPM_LEVELS 2 38 #define NUM_DCLK_DPM_LEVELS 8 39 #define NUM_VCLK_DPM_LEVELS 8 40 #define NUM_DCEFCLK_DPM_LEVELS 8 41 #define NUM_PHYCLK_DPM_LEVELS 8 42 #define NUM_DISPCLK_DPM_LEVELS 8 43 #define NUM_PIXCLK_DPM_LEVELS 8 44 #define NUM_DTBCLK_DPM_LEVELS 8 45 #define NUM_UCLK_DPM_LEVELS 4 46 #define NUM_MP1CLK_DPM_LEVELS 2 47 #define NUM_LINK_LEVELS 2 48 #define NUM_FCLK_DPM_LEVELS 8 49 #define NUM_XGMI_LEVELS 2 50 #define NUM_XGMI_PSTATE_LEVELS 4 51 #define NUM_OD_FAN_MAX_POINTS 6 52 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 63 #define MAX_DTBCLK_DPM_LEVEL (NUM_DTBCLK_DPM_LEVELS - 1) 64 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 65 #define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1) 66 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 67 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 68 69 //Gemini Modes 70 #define PPSMC_GeminiModeNone 0 //Single GPU board 71 #define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 72 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 73 74 // Feature Control Defines 75 // DPM 76 #define FEATURE_DPM_PREFETCHER_BIT 0 77 #define FEATURE_DPM_GFXCLK_BIT 1 78 #define FEATURE_DPM_GFX_GPO_BIT 2 79 #define FEATURE_DPM_UCLK_BIT 3 80 #define FEATURE_DPM_FCLK_BIT 4 81 #define FEATURE_DPM_SOCCLK_BIT 5 82 #define FEATURE_DPM_MP0CLK_BIT 6 83 #define FEATURE_DPM_LINK_BIT 7 84 #define FEATURE_DPM_DCEFCLK_BIT 8 85 #define FEATURE_DPM_XGMI_BIT 9 86 #define FEATURE_MEM_VDDCI_SCALING_BIT 10 87 #define FEATURE_MEM_MVDD_SCALING_BIT 11 88 89 //Idle 90 #define FEATURE_DS_GFXCLK_BIT 12 91 #define FEATURE_DS_SOCCLK_BIT 13 92 #define FEATURE_DS_FCLK_BIT 14 93 #define FEATURE_DS_LCLK_BIT 15 94 #define FEATURE_DS_DCEFCLK_BIT 16 95 #define FEATURE_DS_UCLK_BIT 17 96 #define FEATURE_GFX_ULV_BIT 18 97 #define FEATURE_FW_DSTATE_BIT 19 98 #define FEATURE_GFXOFF_BIT 20 99 #define FEATURE_BACO_BIT 21 100 #define FEATURE_MM_DPM_PG_BIT 22 101 #define FEATURE_SPARE_23_BIT 23 102 //Throttler/Response 103 #define FEATURE_PPT_BIT 24 104 #define FEATURE_TDC_BIT 25 105 #define FEATURE_APCC_PLUS_BIT 26 106 #define FEATURE_GTHR_BIT 27 107 #define FEATURE_ACDC_BIT 28 108 #define FEATURE_VR0HOT_BIT 29 109 #define FEATURE_VR1HOT_BIT 30 110 #define FEATURE_FW_CTF_BIT 31 111 #define FEATURE_FAN_CONTROL_BIT 32 112 #define FEATURE_THERMAL_BIT 33 113 #define FEATURE_GFX_DCS_BIT 34 114 //VF 115 #define FEATURE_RM_BIT 35 116 #define FEATURE_LED_DISPLAY_BIT 36 117 //Other 118 #define FEATURE_GFX_SS_BIT 37 119 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 120 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 121 122 #define FEATURE_MMHUB_PG_BIT 40 123 #define FEATURE_ATHUB_PG_BIT 41 124 #define FEATURE_APCC_DFLL_BIT 42 125 #define FEATURE_DF_SUPERV_BIT 43 126 #define FEATURE_RSMU_SMN_CG_BIT 44 127 #define FEATURE_DF_CSTATE_BIT 45 128 #define FEATURE_2_STEP_PSTATE_BIT 46 129 #define FEATURE_SMNCLK_DPM_BIT 47 130 #define FEATURE_PERLINK_GMIDOWN_BIT 48 131 #define FEATURE_GFX_EDC_BIT 49 132 #define FEATURE_GFX_PER_PART_VMIN_BIT 50 133 #define FEATURE_SMART_SHIFT_BIT 51 134 #define FEATURE_APT_BIT 52 135 #define FEATURE_SPARE_53_BIT 53 136 #define FEATURE_SPARE_54_BIT 54 137 #define FEATURE_SPARE_55_BIT 55 138 #define FEATURE_SPARE_56_BIT 56 139 #define FEATURE_SPARE_57_BIT 57 140 #define FEATURE_SPARE_58_BIT 58 141 #define FEATURE_SPARE_59_BIT 59 142 #define FEATURE_SPARE_60_BIT 60 143 #define FEATURE_SPARE_61_BIT 61 144 #define FEATURE_SPARE_62_BIT 62 145 #define FEATURE_SPARE_63_BIT 63 146 #define NUM_FEATURES 64 147 148 //For use with feature control messages 149 typedef enum { 150 FEATURE_PWR_ALL, 151 FEATURE_PWR_S5, 152 FEATURE_PWR_BACO, 153 FEATURE_PWR_SOC, 154 FEATURE_PWR_GFX, 155 FEATURE_PWR_DOMAIN_COUNT, 156 } FEATURE_PWR_DOMAIN_e; 157 158 159 // Debug Overrides Bitmask 160 #define DPM_OVERRIDE_DISABLE_FCLK_PID 0x00000001 161 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 162 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000004 163 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_FCLK 0x00000008 164 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_FCLK 0x00000010 165 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020 166 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040 167 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_FCLK 0x00000080 168 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100 169 #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200 170 #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400 171 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x00000800 172 #define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00001000 173 #define DPM_OVERRIDE_DISABLE_VCN_PG 0x00002000 174 #define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x00004000 175 176 // VR Mapping Bit Defines 177 #define VR_MAPPING_VR_SELECT_MASK 0x01 178 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 179 180 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 181 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 182 183 // PSI Bit Defines 184 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 185 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 186 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 187 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 188 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 189 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 190 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 191 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 192 193 // Throttler Control/Status Bits 194 #define THROTTLER_PADDING_BIT 0 195 #define THROTTLER_TEMP_EDGE_BIT 1 196 #define THROTTLER_TEMP_HOTSPOT_BIT 2 197 #define THROTTLER_TEMP_MEM_BIT 3 198 #define THROTTLER_TEMP_VR_GFX_BIT 4 199 #define THROTTLER_TEMP_VR_MEM0_BIT 5 200 #define THROTTLER_TEMP_VR_MEM1_BIT 6 201 #define THROTTLER_TEMP_VR_SOC_BIT 7 202 #define THROTTLER_TEMP_LIQUID0_BIT 8 203 #define THROTTLER_TEMP_LIQUID1_BIT 9 204 #define THROTTLER_TEMP_PLX_BIT 10 205 #define THROTTLER_TDC_GFX_BIT 11 206 #define THROTTLER_TDC_SOC_BIT 12 207 #define THROTTLER_PPT0_BIT 13 208 #define THROTTLER_PPT1_BIT 14 209 #define THROTTLER_PPT2_BIT 15 210 #define THROTTLER_PPT3_BIT 16 211 #define THROTTLER_FIT_BIT 17 212 #define THROTTLER_PPM_BIT 18 213 #define THROTTLER_APCC_BIT 19 214 #define THROTTLER_COUNT 20 215 216 // FW DState Features Control Bits 217 // FW DState Features Control Bits 218 #define FW_DSTATE_SOC_ULV_BIT 0 219 #define FW_DSTATE_G6_HSR_BIT 1 220 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2 221 #define FW_DSTATE_MP0_DS_BIT 3 222 #define FW_DSTATE_SMN_DS_BIT 4 223 #define FW_DSTATE_MP1_DS_BIT 5 224 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 225 #define FW_DSTATE_SOC_LIV_MIN_BIT 7 226 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 227 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 9 228 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10 229 #define FW_DSTATE_MEM_PSI_BIT 11 230 #define FW_DSTATE_HSR_NON_STROBE_BIT 12 231 #define FW_DSTATE_MP0_ENTER_WFI_BIT 13 232 233 #define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) 234 #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) 235 #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) 236 #define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) 237 #define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) 238 #define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) 239 #define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) 240 #define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT ) 241 #define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT ) 242 #define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 << FW_DSTATE_MEM_PLL_PWRDN_BIT ) 243 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 << FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT ) 244 #define FW_DSTATE_MEM_PSI_MASK (1 << FW_DSTATE_MEM_PSI_BIT ) 245 #define FW_DSTATE_HSR_NON_STROBE_MASK (1 << FW_DSTATE_HSR_NON_STROBE_BIT ) 246 #define FW_DSTATE_MP0_ENTER_WFI_MASK (1 << FW_DSTATE_MP0_ENTER_WFI_BIT ) 247 248 // GFX GPO Feature Contains PACE and DEM sub features 249 #define GFX_GPO_PACE_BIT 0 250 #define GFX_GPO_DEM_BIT 1 251 252 #define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT) 253 #define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT ) 254 255 #define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1 256 #define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2 257 #define GPO_UPDATE_REQ_MALLHIT_MASK 0x4 258 259 260 //LED Display Mask & Control Bits 261 #define LED_DISPLAY_GFX_DPM_BIT 0 262 #define LED_DISPLAY_PCIE_BIT 1 263 #define LED_DISPLAY_ERROR_BIT 2 264 265 //RLC Pace Table total number of levels 266 #define RLC_PACE_TABLE_NUM_LEVELS 16 267 268 typedef enum { 269 DRAM_BIT_WIDTH_DISABLED = 0, 270 DRAM_BIT_WIDTH_X_8, 271 DRAM_BIT_WIDTH_X_16, 272 DRAM_BIT_WIDTH_X_32, 273 DRAM_BIT_WIDTH_X_64, // NOT USED. 274 DRAM_BIT_WIDTH_X_128, 275 DRAM_BIT_WIDTH_COUNT, 276 } DRAM_BIT_WIDTH_TYPE_e; 277 278 //I2C Interface 279 #define NUM_I2C_CONTROLLERS 16 280 281 #define I2C_CONTROLLER_ENABLED 1 282 #define I2C_CONTROLLER_DISABLED 0 283 284 #define MAX_SW_I2C_COMMANDS 24 285 286 typedef enum { 287 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 288 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 289 I2C_CONTROLLER_PORT_COUNT, 290 } I2cControllerPort_e; 291 292 typedef enum { 293 I2C_CONTROLLER_NAME_VR_GFX = 0, 294 I2C_CONTROLLER_NAME_VR_SOC, 295 I2C_CONTROLLER_NAME_VR_VDDCI, 296 I2C_CONTROLLER_NAME_VR_MVDD, 297 I2C_CONTROLLER_NAME_LIQUID0, 298 I2C_CONTROLLER_NAME_LIQUID1, 299 I2C_CONTROLLER_NAME_PLX, 300 I2C_CONTROLLER_NAME_OTHER, 301 I2C_CONTROLLER_NAME_COUNT, 302 } I2cControllerName_e; 303 304 typedef enum { 305 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 306 I2C_CONTROLLER_THROTTLER_VR_GFX, 307 I2C_CONTROLLER_THROTTLER_VR_SOC, 308 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 309 I2C_CONTROLLER_THROTTLER_VR_MVDD, 310 I2C_CONTROLLER_THROTTLER_LIQUID0, 311 I2C_CONTROLLER_THROTTLER_LIQUID1, 312 I2C_CONTROLLER_THROTTLER_PLX, 313 I2C_CONTROLLER_THROTTLER_INA3221, 314 I2C_CONTROLLER_THROTTLER_COUNT, 315 } I2cControllerThrottler_e; 316 317 typedef enum { 318 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 319 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 320 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 321 I2C_CONTROLLER_PROTOCOL_INA3221, 322 I2C_CONTROLLER_PROTOCOL_COUNT, 323 } I2cControllerProtocol_e; 324 325 typedef struct { 326 uint8_t Enabled; 327 uint8_t Speed; 328 uint8_t SlaveAddress; 329 uint8_t ControllerPort; 330 uint8_t ControllerName; 331 uint8_t ThermalThrotter; 332 uint8_t I2cProtocol; 333 uint8_t PaddingConfig; 334 } I2cControllerConfig_t; 335 336 typedef enum { 337 I2C_PORT_SVD_SCL = 0, 338 I2C_PORT_GPIO, 339 } I2cPort_e; 340 341 typedef enum { 342 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 343 I2C_SPEED_FAST_100K, //100 Kbits/s 344 I2C_SPEED_FAST_400K, //400 Kbits/s 345 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 346 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 347 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 348 I2C_SPEED_COUNT, 349 } I2cSpeed_e; 350 351 typedef enum { 352 I2C_CMD_READ = 0, 353 I2C_CMD_WRITE, 354 I2C_CMD_COUNT, 355 } I2cCmdType_e; 356 357 typedef enum { 358 FAN_MODE_AUTO = 0, 359 FAN_MODE_MANUAL_LINEAR, 360 } FanMode_e; 361 362 #define CMDCONFIG_STOP_BIT 0 363 #define CMDCONFIG_RESTART_BIT 1 364 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 365 366 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 367 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 368 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 369 370 typedef struct { 371 uint8_t ReadWriteData; //Return data for read. Data to send for write 372 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 373 } SwI2cCmd_t; //SW I2C Command Table 374 375 typedef struct { 376 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 377 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 378 uint8_t SlaveAddress; //Slave address of device 379 uint8_t NumCmds; //Number of commands 380 381 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 382 } SwI2cRequest_t; // SW I2C Request Table 383 384 typedef struct { 385 SwI2cRequest_t SwI2cRequest; 386 387 uint32_t Spare[8]; 388 uint32_t MmHubPadding[8]; // SMU internal use 389 } SwI2cRequestExternal_t; 390 391 //D3HOT sequences 392 typedef enum { 393 BACO_SEQUENCE, 394 MSR_SEQUENCE, 395 BAMACO_SEQUENCE, 396 ULPS_SEQUENCE, 397 D3HOT_SEQUENCE_COUNT, 398 } D3HOTSequence_e; 399 400 //THis is aligned with RSMU PGFSM Register Mapping 401 typedef enum { 402 PG_DYNAMIC_MODE = 0, 403 PG_STATIC_MODE, 404 } PowerGatingMode_e; 405 406 //This is aligned with RSMU PGFSM Register Mapping 407 typedef enum { 408 PG_POWER_DOWN = 0, 409 PG_POWER_UP, 410 } PowerGatingSettings_e; 411 412 typedef struct { 413 uint32_t a; // store in IEEE float format in this variable 414 uint32_t b; // store in IEEE float format in this variable 415 uint32_t c; // store in IEEE float format in this variable 416 } QuadraticInt_t; 417 418 typedef struct { 419 uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 420 uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 421 uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 422 } QuadraticFixedPoint_t; 423 424 typedef struct { 425 uint32_t m; // store in IEEE float format in this variable 426 uint32_t b; // store in IEEE float format in this variable 427 } LinearInt_t; 428 429 typedef struct { 430 uint32_t a; // store in IEEE float format in this variable 431 uint32_t b; // store in IEEE float format in this variable 432 uint32_t c; // store in IEEE float format in this variable 433 } DroopInt_t; 434 435 //Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL 436 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5 437 typedef enum { 438 PIECEWISE_LINEAR_FUSED_MODEL = 0, 439 PIECEWISE_LINEAR_PP_MODEL, 440 QUADRATIC_PP_MODEL, 441 PERPART_PIECEWISE_LINEAR_PP_MODEL, 442 } DfllDroopModelSelect_e; 443 444 typedef struct { 445 uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in GHz, store in IEEE float format 446 uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in V , store in IEEE float format 447 }PiecewiseLinearDroopInt_t; 448 449 typedef enum { 450 GFXCLK_SOURCE_PLL = 0, 451 GFXCLK_SOURCE_DFLL, 452 GFXCLK_SOURCE_COUNT, 453 } GFXCLK_SOURCE_e; 454 455 //Only Clks that have DPM descriptors are listed here 456 typedef enum { 457 PPCLK_GFXCLK = 0, 458 PPCLK_SOCCLK, 459 PPCLK_UCLK, 460 PPCLK_FCLK, 461 PPCLK_DCLK_0, 462 PPCLK_VCLK_0, 463 PPCLK_DCLK_1, 464 PPCLK_VCLK_1, 465 PPCLK_DCEFCLK, 466 PPCLK_DISPCLK, 467 PPCLK_PIXCLK, 468 PPCLK_PHYCLK, 469 PPCLK_DTBCLK, 470 PPCLK_COUNT, 471 } PPCLK_e; 472 473 typedef enum { 474 VOLTAGE_MODE_AVFS = 0, 475 VOLTAGE_MODE_AVFS_SS, 476 VOLTAGE_MODE_SS, 477 VOLTAGE_MODE_COUNT, 478 } VOLTAGE_MODE_e; 479 480 481 typedef enum { 482 AVFS_VOLTAGE_GFX = 0, 483 AVFS_VOLTAGE_SOC, 484 AVFS_VOLTAGE_COUNT, 485 } AVFS_VOLTAGE_TYPE_e; 486 487 typedef enum { 488 UCLK_DIV_BY_1 = 0, 489 UCLK_DIV_BY_2, 490 UCLK_DIV_BY_4, 491 UCLK_DIV_BY_8, 492 } UCLK_DIV_e; 493 494 typedef enum { 495 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 496 GPIO_INT_POLARITY_ACTIVE_HIGH, 497 } GpioIntPolarity_e; 498 499 typedef enum { 500 PWR_CONFIG_TDP = 0, 501 PWR_CONFIG_TGP, 502 PWR_CONFIG_TCP_ESTIMATED, 503 PWR_CONFIG_TCP_MEASURED, 504 } PwrConfig_e; 505 506 typedef enum { 507 XGMI_LINK_RATE_2 = 2, // 2Gbps 508 XGMI_LINK_RATE_4 = 4, // 4Gbps 509 XGMI_LINK_RATE_8 = 8, // 8Gbps 510 XGMI_LINK_RATE_12 = 12, // 12Gbps 511 XGMI_LINK_RATE_16 = 16, // 16Gbps 512 XGMI_LINK_RATE_17 = 17, // 17Gbps 513 XGMI_LINK_RATE_18 = 18, // 18Gbps 514 XGMI_LINK_RATE_19 = 19, // 19Gbps 515 XGMI_LINK_RATE_20 = 20, // 20Gbps 516 XGMI_LINK_RATE_21 = 21, // 21Gbps 517 XGMI_LINK_RATE_22 = 22, // 22Gbps 518 XGMI_LINK_RATE_23 = 23, // 23Gbps 519 XGMI_LINK_RATE_24 = 24, // 24Gbps 520 XGMI_LINK_RATE_25 = 25, // 25Gbps 521 XGMI_LINK_RATE_COUNT 522 } XGMI_LINK_RATE_e; 523 524 typedef enum { 525 XGMI_LINK_WIDTH_1 = 0, // x1 526 XGMI_LINK_WIDTH_2, // x2 527 XGMI_LINK_WIDTH_4, // x4 528 XGMI_LINK_WIDTH_8, // x8 529 XGMI_LINK_WIDTH_9, // x9 530 XGMI_LINK_WIDTH_16, // x16 531 XGMI_LINK_WIDTH_COUNT 532 } XGMI_LINK_WIDTH_e; 533 534 typedef struct { 535 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 536 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 537 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 538 uint8_t Padding; 539 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 540 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 541 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 542 uint16_t Padding16; 543 } DpmDescriptor_t; 544 545 typedef enum { 546 PPT_THROTTLER_PPT0, 547 PPT_THROTTLER_PPT1, 548 PPT_THROTTLER_PPT2, 549 PPT_THROTTLER_PPT3, 550 PPT_THROTTLER_COUNT 551 } PPT_THROTTLER_e; 552 553 typedef enum { 554 TEMP_EDGE, 555 TEMP_HOTSPOT, 556 TEMP_MEM, 557 TEMP_VR_GFX, 558 TEMP_VR_MEM0, 559 TEMP_VR_MEM1, 560 TEMP_VR_SOC, 561 TEMP_LIQUID0, 562 TEMP_LIQUID1, 563 TEMP_PLX, 564 TEMP_COUNT, 565 } TEMP_e; 566 567 typedef enum { 568 TDC_THROTTLER_GFX, 569 TDC_THROTTLER_SOC, 570 TDC_THROTTLER_COUNT 571 } TDC_THROTTLER_e; 572 573 typedef enum { 574 CUSTOMER_VARIANT_ROW, 575 CUSTOMER_VARIANT_FALCON, 576 CUSTOMER_VARIANT_COUNT, 577 } CUSTOMER_VARIANT_e; 578 579 // Used for 2-step UCLK DPM change workaround 580 typedef struct { 581 uint16_t Fmin; 582 uint16_t Fmax; 583 } UclkDpmChangeRange_t; 584 585 typedef struct { 586 // MAJOR SECTION: SKU PARAMETERS 587 588 uint32_t Version; 589 590 // SECTION: Feature Enablement 591 uint32_t FeaturesToRun[NUM_FEATURES / 32]; 592 593 // SECTION: Infrastructure Limits 594 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts 595 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 596 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts 597 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 598 599 uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps 600 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms 601 602 uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius 603 604 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 605 606 // SECTION: Power Configuration 607 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e 608 uint8_t TotalPowerPadding[3]; 609 610 // SECTION: APCC Settings 611 uint32_t ApccPlusResidencyLimit; 612 613 //SECTION: SMNCLK DPM 614 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 615 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 616 617 uint32_t PaddingAPCC; 618 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) 619 uint16_t PaddingPerPartDroop; 620 621 // SECTION: Throttler settings 622 uint32_t ThrottlerControlMask; // See Throtter masks defines 623 624 // SECTION: FW DSTATE Settings 625 uint32_t FwDStateMask; // See FW DState masks defines 626 627 // SECTION: ULV Settings 628 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 629 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 630 631 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 632 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 633 634 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC 635 uint16_t PaddingLIVmin; 636 637 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events 638 uint8_t paddingRlcUlvParams[3]; 639 640 // SECTION: Voltage Control Parameters 641 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 642 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 643 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 644 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 645 646 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 647 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 648 649 // SECTION: Temperature Dependent Vmin 650 uint16_t VDDGFX_TVmin; //Celcius 651 uint16_t VDDSOC_TVmin; //Celcius 652 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 653 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 654 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 655 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 656 657 uint16_t VDDGFX_TVminHystersis; // Celcius 658 uint16_t VDDSOC_TVminHystersis; // Celcius 659 660 //SECTION: DPM Config 1 661 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 662 663 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 664 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 665 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 666 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 667 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 668 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 669 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 670 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 671 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 672 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 673 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 674 uint32_t Paddingclks; 675 676 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format 677 678 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 679 680 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 681 682 // Used for MALL performance boost 683 uint16_t FclkBoostFreq; // In Mhz 684 uint16_t FclkParamPadding; 685 686 // SECTION: DPM Config 2 687 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 688 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 689 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 690 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 691 // GFXCLK DPM 692 uint16_t GfxclkFgfxoffEntry; // in Mhz 693 uint16_t GfxclkFinit; // in Mhz 694 uint16_t GfxclkFidle; // in MHz 695 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 696 uint8_t GfxclkPadding; 697 698 // GFX GPO 699 uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM 700 uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled 701 uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled 702 uint8_t GfxGpoPadding[1]; 703 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation 704 705 uint32_t GfxGpoPadding32[4]; 706 707 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz 708 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz 709 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz 710 711 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 712 713 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 714 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 715 716 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 717 718 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 719 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 720 721 uint32_t DcsParamPadding[5]; 722 723 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 724 725 // UCLK section 726 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 727 uint8_t PaddingMem[3]; 728 729 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 730 731 // Used for 2-Step UCLK change workaround 732 UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz 733 UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz 734 uint16_t UclkDpmMidstepFreq; // In Mhz 735 uint16_t UclkMidstepPadding; 736 737 // Link DPM Settings 738 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 739 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 740 uint16_t LclkFreq[NUM_LINK_LEVELS]; 741 742 // SECTION: Fan Control 743 uint16_t FanStopTemp; //Celcius 744 uint16_t FanStartTemp; //Celcius 745 746 uint16_t FanGain[TEMP_COUNT]; 747 748 uint16_t FanPwmMin; 749 uint16_t FanAcousticLimitRpm; 750 uint16_t FanThrottlingRpm; 751 uint16_t FanMaximumRpm; 752 uint16_t MGpuFanBoostLimitRpm; 753 uint16_t FanTargetTemperature; 754 uint16_t FanTargetGfxclk; 755 uint16_t FanPadding16; 756 uint8_t FanTempInputSelect; 757 uint8_t FanPadding; 758 uint8_t FanZeroRpmEnable; 759 uint8_t FanTachEdgePerRev; 760 761 // The following are AFC override parameters. Leave at 0 to use FW defaults. 762 int16_t FuzzyFan_ErrorSetDelta; 763 int16_t FuzzyFan_ErrorRateSetDelta; 764 int16_t FuzzyFan_PwmSetDelta; 765 uint16_t FuzzyFan_Reserved; 766 767 // SECTION: AVFS 768 // Overrides 769 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 770 uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) 771 uint8_t Padding8_Avfs; 772 773 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 774 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 775 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 776 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 777 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 778 779 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format 780 781 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 782 783 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 784 785 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 786 uint8_t Padding8_GfxBtc[2]; 787 788 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 789 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 790 791 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 792 793 // SECTION: XGMI 794 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 795 uint8_t XgmiDpmSpare[2]; 796 797 // SECTION: Advanced Options 798 uint32_t DebugOverrides; 799 QuadraticInt_t ReservedEquation0; 800 QuadraticInt_t ReservedEquation1; 801 QuadraticInt_t ReservedEquation2; 802 QuadraticInt_t ReservedEquation3; 803 804 // SECTION: Sku Reserved 805 uint8_t CustomerVariant; 806 807 //VC BTC parameters are only applicable to VDD_GFX domain 808 uint8_t VcBtcEnabled; 809 uint16_t VcBtcVminT0; // T0_VMIN 810 uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET 811 uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB 812 uint32_t VcBtcPsmA; // A_PSM 813 uint32_t VcBtcPsmB; // B_PSM 814 uint32_t VcBtcVminA; // A_VMIN 815 uint32_t VcBtcVminB; // B_VMIN 816 817 //GPIO Board feature 818 uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs 819 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 820 821 uint32_t SkuReserved[8]; 822 823 824 // MAJOR SECTION: BOARD PARAMETERS 825 826 //SECTION: Gaming Clocks 827 uint32_t GamingClk[6]; 828 829 // SECTION: I2C Control 830 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 831 832 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 833 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 834 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 835 uint8_t I2cSpare[1]; 836 837 // SECTION: SVI2 Board Parameters 838 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 839 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 840 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 841 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 842 843 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 844 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 845 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 846 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 847 848 // SECTION: Telemetry Settings 849 uint16_t GfxMaxCurrent; // in Amps 850 int8_t GfxOffset; // in Amps 851 uint8_t Padding_TelemetryGfx; 852 853 uint16_t SocMaxCurrent; // in Amps 854 int8_t SocOffset; // in Amps 855 uint8_t Padding_TelemetrySoc; 856 857 uint16_t Mem0MaxCurrent; // in Amps 858 int8_t Mem0Offset; // in Amps 859 uint8_t Padding_TelemetryMem0; 860 861 uint16_t Mem1MaxCurrent; // in Amps 862 int8_t Mem1Offset; // in Amps 863 uint8_t Padding_TelemetryMem1; 864 865 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 866 867 // SECTION: GPIO Settings 868 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 869 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 870 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 871 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 872 873 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 874 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 875 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 876 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 877 878 // LED Display Settings 879 uint8_t LedPin0; // GPIO number for LedPin[0] 880 uint8_t LedPin1; // GPIO number for LedPin[1] 881 uint8_t LedPin2; // GPIO number for LedPin[2] 882 uint8_t LedEnableMask; 883 884 uint8_t LedPcie; // GPIO number for PCIE results 885 uint8_t LedError; // GPIO number for Error Cases 886 uint8_t LedSpare1[2]; 887 888 // SECTION: Clock Spread Spectrum 889 890 // GFXCLK PLL Spread Spectrum 891 uint8_t PllGfxclkSpreadEnabled; // on or off 892 uint8_t PllGfxclkSpreadPercent; // Q4.4 893 uint16_t PllGfxclkSpreadFreq; // kHz 894 895 // GFXCLK DFLL Spread Spectrum 896 uint8_t DfllGfxclkSpreadEnabled; // on or off 897 uint8_t DfllGfxclkSpreadPercent; // Q4.4 898 uint16_t DfllGfxclkSpreadFreq; // kHz 899 900 // UCLK Spread Spectrum 901 uint16_t UclkSpreadPadding; 902 uint16_t UclkSpreadFreq; // kHz 903 904 // FCLK Spread Spectrum 905 uint8_t FclkSpreadEnabled; // on or off 906 uint8_t FclkSpreadPercent; // Q4.4 907 uint16_t FclkSpreadFreq; // kHz 908 909 // Section: Memory Config 910 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 911 912 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 913 uint8_t PaddingMem1[3]; 914 915 // Section: Total Board Power 916 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 917 uint16_t BoardPowerPadding; 918 919 // SECTION: XGMI Training 920 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 921 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 922 923 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 924 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 925 926 // SECTION: UMC feature flags 927 uint8_t HsrEnabled; 928 uint8_t VddqOffEnabled; 929 uint8_t PaddingUmcFlags[2]; 930 931 // UCLK Spread Spectrum 932 uint8_t UclkSpreadPercent[16]; 933 934 // SECTION: Board Reserved 935 uint32_t BoardReserved[11]; 936 937 // SECTION: Structure Padding 938 939 // Padding for MMHUB - do not modify this 940 uint32_t MmHubPadding[8]; // SMU internal use 941 942 } PPTable_t; 943 944 typedef struct { 945 // MAJOR SECTION: SKU PARAMETERS 946 947 uint32_t Version; 948 949 // SECTION: Feature Enablement 950 uint32_t FeaturesToRun[NUM_FEATURES / 32]; 951 952 // SECTION: Infrastructure Limits 953 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts 954 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 955 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts 956 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 957 958 uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps 959 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms 960 961 uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius 962 963 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 964 965 // SECTION: Power Configuration 966 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e 967 uint8_t TotalPowerPadding[3]; 968 969 // SECTION: APCC Settings 970 uint32_t ApccPlusResidencyLimit; 971 972 //SECTION: SMNCLK DPM 973 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 974 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 975 976 uint32_t PaddingAPCC; 977 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) 978 uint16_t PaddingPerPartDroop; 979 980 // SECTION: Throttler settings 981 uint32_t ThrottlerControlMask; // See Throtter masks defines 982 983 // SECTION: FW DSTATE Settings 984 uint32_t FwDStateMask; // See FW DState masks defines 985 986 // SECTION: ULV Settings 987 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 988 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 989 990 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 991 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 992 993 uint16_t SocLIVmin; 994 uint16_t SocLIVminoffset; 995 996 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events 997 uint8_t paddingRlcUlvParams[3]; 998 999 // SECTION: Voltage Control Parameters 1000 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 1001 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 1002 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 1003 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 1004 1005 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 1006 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 1007 1008 // SECTION: Temperature Dependent Vmin 1009 uint16_t VDDGFX_TVmin; //Celcius 1010 uint16_t VDDSOC_TVmin; //Celcius 1011 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 1012 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 1013 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 1014 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 1015 1016 uint16_t VDDGFX_TVminHystersis; // Celcius 1017 uint16_t VDDSOC_TVminHystersis; // Celcius 1018 1019 //SECTION: DPM Config 1 1020 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1021 1022 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1023 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1024 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1025 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1026 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1027 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 1028 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1029 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 1030 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 1031 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1032 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1033 uint32_t Paddingclks; 1034 1035 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format 1036 1037 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1038 1039 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1040 1041 // Used for MALL performance boost 1042 uint16_t FclkBoostFreq; // In Mhz 1043 uint16_t FclkParamPadding; 1044 1045 // SECTION: DPM Config 2 1046 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1047 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1048 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1049 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1050 // GFXCLK DPM 1051 uint16_t GfxclkFgfxoffEntry; // in Mhz 1052 uint16_t GfxclkFinit; // in Mhz 1053 uint16_t GfxclkFidle; // in MHz 1054 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 1055 uint8_t GfxclkPadding; 1056 1057 // GFX GPO 1058 uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM 1059 uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled 1060 uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled 1061 uint8_t GfxGpoPadding[1]; 1062 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation 1063 1064 uint32_t GfxGpoPadding32[4]; 1065 1066 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz 1067 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz 1068 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz 1069 1070 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1071 1072 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1073 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1074 1075 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1076 1077 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1078 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1079 1080 uint32_t DcsParamPadding[5]; 1081 1082 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 1083 1084 // UCLK section 1085 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 1086 uint8_t PaddingMem[3]; 1087 1088 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1089 1090 // Used for 2-Step UCLK change workaround 1091 UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz 1092 UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz 1093 uint16_t UclkDpmMidstepFreq; // In Mhz 1094 uint16_t UclkMidstepPadding; 1095 1096 // Link DPM Settings 1097 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1098 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1099 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1100 1101 // SECTION: Fan Control 1102 uint16_t FanStopTemp; //Celcius 1103 uint16_t FanStartTemp; //Celcius 1104 1105 uint16_t FanGain[TEMP_COUNT]; 1106 1107 uint16_t FanPwmMin; 1108 uint16_t FanAcousticLimitRpm; 1109 uint16_t FanThrottlingRpm; 1110 uint16_t FanMaximumRpm; 1111 uint16_t MGpuFanBoostLimitRpm; 1112 uint16_t FanTargetTemperature; 1113 uint16_t FanTargetGfxclk; 1114 uint16_t FanPadding16; 1115 uint8_t FanTempInputSelect; 1116 uint8_t FanPadding; 1117 uint8_t FanZeroRpmEnable; 1118 uint8_t FanTachEdgePerRev; 1119 1120 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1121 int16_t FuzzyFan_ErrorSetDelta; 1122 int16_t FuzzyFan_ErrorRateSetDelta; 1123 int16_t FuzzyFan_PwmSetDelta; 1124 uint16_t FuzzyFan_Reserved; 1125 1126 // SECTION: AVFS 1127 // Overrides 1128 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1129 uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) 1130 uint8_t Padding8_Avfs; 1131 1132 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 1133 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 1134 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 1135 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 1136 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 1137 1138 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format 1139 1140 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 1141 1142 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 1143 1144 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 1145 uint8_t Padding8_GfxBtc[2]; 1146 1147 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 1148 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 1149 1150 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 1151 1152 // SECTION: XGMI 1153 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 1154 uint8_t XgmiDpmSpare[2]; 1155 1156 // SECTION: Advanced Options 1157 uint32_t DebugOverrides; 1158 QuadraticInt_t ReservedEquation0; 1159 QuadraticInt_t ReservedEquation1; 1160 QuadraticInt_t ReservedEquation2; 1161 QuadraticInt_t ReservedEquation3; 1162 1163 // SECTION: Sku Reserved 1164 uint8_t CustomerVariant; 1165 1166 //VC BTC parameters are only applicable to VDD_GFX domain 1167 uint8_t VcBtcEnabled; 1168 uint16_t VcBtcVminT0; // T0_VMIN 1169 uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET 1170 uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB 1171 uint32_t VcBtcPsmA; // A_PSM 1172 uint32_t VcBtcPsmB; // B_PSM 1173 uint32_t VcBtcVminA; // A_VMIN 1174 uint32_t VcBtcVminB; // B_VMIN 1175 1176 //GPIO Board feature 1177 uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs 1178 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1179 1180 uint32_t SkuReserved[63]; 1181 1182 1183 1184 // MAJOR SECTION: BOARD PARAMETERS 1185 1186 //SECTION: Gaming Clocks 1187 uint32_t GamingClk[6]; 1188 1189 // SECTION: I2C Control 1190 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1191 1192 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 1193 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 1194 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 1195 uint8_t I2cSpare[1]; 1196 1197 // SECTION: SVI2 Board Parameters 1198 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1199 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1200 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1201 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1202 1203 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1204 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1205 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1206 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1207 1208 // SECTION: Telemetry Settings 1209 uint16_t GfxMaxCurrent; // in Amps 1210 int8_t GfxOffset; // in Amps 1211 uint8_t Padding_TelemetryGfx; 1212 1213 uint16_t SocMaxCurrent; // in Amps 1214 int8_t SocOffset; // in Amps 1215 uint8_t Padding_TelemetrySoc; 1216 1217 uint16_t Mem0MaxCurrent; // in Amps 1218 int8_t Mem0Offset; // in Amps 1219 uint8_t Padding_TelemetryMem0; 1220 1221 uint16_t Mem1MaxCurrent; // in Amps 1222 int8_t Mem1Offset; // in Amps 1223 uint8_t Padding_TelemetryMem1; 1224 1225 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1226 1227 // SECTION: GPIO Settings 1228 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1229 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1230 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1231 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1232 1233 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 1234 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 1235 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1236 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1237 1238 // LED Display Settings 1239 uint8_t LedPin0; // GPIO number for LedPin[0] 1240 uint8_t LedPin1; // GPIO number for LedPin[1] 1241 uint8_t LedPin2; // GPIO number for LedPin[2] 1242 uint8_t LedEnableMask; 1243 1244 uint8_t LedPcie; // GPIO number for PCIE results 1245 uint8_t LedError; // GPIO number for Error Cases 1246 uint8_t LedSpare1[2]; 1247 1248 // SECTION: Clock Spread Spectrum 1249 1250 // GFXCLK PLL Spread Spectrum 1251 uint8_t PllGfxclkSpreadEnabled; // on or off 1252 uint8_t PllGfxclkSpreadPercent; // Q4.4 1253 uint16_t PllGfxclkSpreadFreq; // kHz 1254 1255 // GFXCLK DFLL Spread Spectrum 1256 uint8_t DfllGfxclkSpreadEnabled; // on or off 1257 uint8_t DfllGfxclkSpreadPercent; // Q4.4 1258 uint16_t DfllGfxclkSpreadFreq; // kHz 1259 1260 // UCLK Spread Spectrum 1261 uint16_t UclkSpreadPadding; 1262 uint16_t UclkSpreadFreq; // kHz 1263 1264 // FCLK Spread Spectrum 1265 uint8_t FclkSpreadEnabled; // on or off 1266 uint8_t FclkSpreadPercent; // Q4.4 1267 uint16_t FclkSpreadFreq; // kHz 1268 1269 // Section: Memory Config 1270 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 1271 1272 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 1273 uint8_t PaddingMem1[3]; 1274 1275 // Section: Total Board Power 1276 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1277 uint16_t BoardPowerPadding; 1278 1279 // SECTION: XGMI Training 1280 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 1281 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 1282 1283 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 1284 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 1285 1286 // SECTION: UMC feature flags 1287 uint8_t HsrEnabled; 1288 uint8_t VddqOffEnabled; 1289 uint8_t PaddingUmcFlags[2]; 1290 1291 // UCLK Spread Spectrum 1292 uint8_t UclkSpreadPercent[16]; 1293 1294 // SECTION: Board Reserved 1295 uint32_t BoardReserved[11]; 1296 1297 // SECTION: Structure Padding 1298 1299 // Padding for MMHUB - do not modify this 1300 uint32_t MmHubPadding[8]; // SMU internal use 1301 1302 1303 } PPTable_beige_goby_t; 1304 1305 typedef struct { 1306 // Time constant parameters for clock averages in ms 1307 uint16_t GfxclkAverageLpfTau; 1308 uint16_t FclkAverageLpfTau; 1309 uint16_t UclkAverageLpfTau; 1310 uint16_t GfxActivityLpfTau; 1311 uint16_t UclkActivityLpfTau; 1312 uint16_t SocketPowerLpfTau; 1313 uint16_t VcnClkAverageLpfTau; 1314 uint16_t padding16; 1315 } DriverSmuConfig_t; 1316 1317 typedef struct { 1318 DriverSmuConfig_t DriverSmuConfig; 1319 1320 uint32_t Spare[7]; 1321 // Padding - ignore 1322 uint32_t MmHubPadding[8]; // SMU internal use 1323 } DriverSmuConfigExternal_t; 1324 1325 typedef struct { 1326 uint16_t GfxclkFmin; // MHz 1327 uint16_t GfxclkFmax; // MHz 1328 QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV 1329 uint16_t CustomCurveFmin; // MHz 1330 uint16_t UclkFmin; // MHz 1331 uint16_t UclkFmax; // MHz 1332 int16_t OverDrivePct; // % 1333 uint16_t FanMaximumRpm; 1334 uint16_t FanMinimumPwm; 1335 uint16_t FanAcousticLimitRpm; 1336 uint16_t FanTargetTemperature; // Degree Celcius 1337 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 1338 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 1339 uint16_t MaxOpTemp; // Degree Celcius 1340 int16_t VddGfxOffset; // in mV 1341 uint8_t FanZeroRpmEnable; 1342 uint8_t FanZeroRpmStopTemp; 1343 uint8_t FanMode; 1344 uint8_t Padding[1]; 1345 } OverDriveTable_t; 1346 1347 typedef struct { 1348 OverDriveTable_t OverDriveTable; 1349 uint32_t Spare[8]; 1350 1351 uint32_t MmHubPadding[8]; // SMU internal use 1352 } OverDriveTableExternal_t; 1353 1354 typedef struct { 1355 uint32_t CurrClock[PPCLK_COUNT]; 1356 1357 uint16_t AverageGfxclkFrequencyPreDs; 1358 uint16_t AverageGfxclkFrequencyPostDs; 1359 uint16_t AverageFclkFrequencyPreDs; 1360 uint16_t AverageFclkFrequencyPostDs; 1361 uint16_t AverageUclkFrequencyPreDs ; 1362 uint16_t AverageUclkFrequencyPostDs ; 1363 1364 1365 uint16_t AverageGfxActivity ; 1366 uint16_t AverageUclkActivity ; 1367 uint8_t CurrSocVoltageOffset ; 1368 uint8_t CurrGfxVoltageOffset ; 1369 uint8_t CurrMemVidOffset ; 1370 uint8_t Padding8 ; 1371 uint16_t AverageSocketPower ; 1372 uint16_t TemperatureEdge ; 1373 uint16_t TemperatureHotspot ; 1374 uint16_t TemperatureMem ; 1375 uint16_t TemperatureVrGfx ; 1376 uint16_t TemperatureVrMem0 ; 1377 uint16_t TemperatureVrMem1 ; 1378 uint16_t TemperatureVrSoc ; 1379 uint16_t TemperatureLiquid0 ; 1380 uint16_t TemperatureLiquid1 ; 1381 uint16_t TemperaturePlx ; 1382 uint16_t Padding16 ; 1383 uint32_t ThrottlerStatus ; 1384 1385 uint8_t LinkDpmLevel; 1386 uint8_t CurrFanPwm; 1387 uint16_t CurrFanSpeed; 1388 1389 //BACO metrics, PMFW-1721 1390 //metrics for D3hot entry/exit and driver ARM msgs 1391 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1392 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1393 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1394 1395 //PMFW-4362 1396 uint32_t EnergyAccumulator; 1397 uint16_t AverageVclk0Frequency ; 1398 uint16_t AverageDclk0Frequency ; 1399 uint16_t AverageVclk1Frequency ; 1400 uint16_t AverageDclk1Frequency ; 1401 uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1402 uint8_t PcieRate ; 1403 uint8_t PcieWidth ; 1404 uint16_t AverageGfxclkFrequencyTarget; 1405 uint16_t Padding16_2; 1406 1407 } SmuMetrics_t; 1408 1409 typedef struct { 1410 uint32_t CurrClock[PPCLK_COUNT]; 1411 1412 uint16_t AverageGfxclkFrequencyPreDs; 1413 uint16_t AverageGfxclkFrequencyPostDs; 1414 uint16_t AverageFclkFrequencyPreDs; 1415 uint16_t AverageFclkFrequencyPostDs; 1416 uint16_t AverageUclkFrequencyPreDs ; 1417 uint16_t AverageUclkFrequencyPostDs ; 1418 1419 1420 uint16_t AverageGfxActivity ; 1421 uint16_t AverageUclkActivity ; 1422 uint8_t CurrSocVoltageOffset ; 1423 uint8_t CurrGfxVoltageOffset ; 1424 uint8_t CurrMemVidOffset ; 1425 uint8_t Padding8 ; 1426 uint16_t AverageSocketPower ; 1427 uint16_t TemperatureEdge ; 1428 uint16_t TemperatureHotspot ; 1429 uint16_t TemperatureMem ; 1430 uint16_t TemperatureVrGfx ; 1431 uint16_t TemperatureVrMem0 ; 1432 uint16_t TemperatureVrMem1 ; 1433 uint16_t TemperatureVrSoc ; 1434 uint16_t TemperatureLiquid0 ; 1435 uint16_t TemperatureLiquid1 ; 1436 uint16_t TemperaturePlx ; 1437 uint16_t Padding16 ; 1438 uint32_t AccCnt ; 1439 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1440 1441 1442 uint8_t LinkDpmLevel; 1443 uint8_t CurrFanPwm; 1444 uint16_t CurrFanSpeed; 1445 1446 //BACO metrics, PMFW-1721 1447 //metrics for D3hot entry/exit and driver ARM msgs 1448 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1449 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1450 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1451 1452 //PMFW-4362 1453 uint32_t EnergyAccumulator; 1454 uint16_t AverageVclk0Frequency ; 1455 uint16_t AverageDclk0Frequency ; 1456 uint16_t AverageVclk1Frequency ; 1457 uint16_t AverageDclk1Frequency ; 1458 uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1459 uint8_t PcieRate ; 1460 uint8_t PcieWidth ; 1461 uint16_t AverageGfxclkFrequencyTarget; 1462 uint16_t Padding16_2; 1463 1464 } SmuMetrics_V2_t; 1465 1466 typedef struct { 1467 union { 1468 SmuMetrics_t SmuMetrics; 1469 SmuMetrics_V2_t SmuMetrics_V2; 1470 }; 1471 uint32_t Spare[1]; 1472 1473 // Padding - ignore 1474 uint32_t MmHubPadding[8]; // SMU internal use 1475 } SmuMetricsExternal_t; 1476 1477 typedef struct { 1478 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 1479 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 1480 uint16_t MinUclk; 1481 uint16_t MaxUclk; 1482 1483 uint8_t WmSetting; 1484 uint8_t Flags; 1485 uint8_t Padding[2]; 1486 1487 } WatermarkRowGeneric_t; 1488 1489 #define NUM_WM_RANGES 4 1490 1491 typedef enum { 1492 WM_SOCCLK = 0, 1493 WM_DCEFCLK, 1494 WM_COUNT, 1495 } WM_CLOCK_e; 1496 1497 typedef enum { 1498 WATERMARKS_CLOCK_RANGE = 0, 1499 WATERMARKS_DUMMY_PSTATE, 1500 WATERMARKS_MALL, 1501 WATERMARKS_COUNT, 1502 } WATERMARKS_FLAGS_e; 1503 1504 typedef struct { 1505 // Watermarks 1506 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 1507 } Watermarks_t; 1508 1509 typedef struct { 1510 Watermarks_t Watermarks; 1511 1512 uint32_t MmHubPadding[8]; // SMU internal use 1513 } WatermarksExternal_t; 1514 1515 typedef struct { 1516 uint16_t avgPsmCount[67]; 1517 uint16_t minPsmCount[67]; 1518 float avgPsmVoltage[67]; 1519 float minPsmVoltage[67]; 1520 } AvfsDebugTable_t; 1521 1522 typedef struct { 1523 AvfsDebugTable_t AvfsDebugTable; 1524 1525 uint32_t MmHubPadding[8]; // SMU internal use 1526 } AvfsDebugTableExternal_t; 1527 1528 typedef struct { 1529 uint8_t AvfsVersion; 1530 uint8_t Padding; 1531 1532 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 1533 1534 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 1535 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1536 1537 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 1538 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 1539 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 1540 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 1541 1542 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1543 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1544 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 1545 1546 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1547 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1548 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 1549 1550 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1551 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1552 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 1553 1554 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1555 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1556 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 1557 1558 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1559 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1560 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 1561 1562 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 1563 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 1564 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 1565 1566 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 1567 1568 1569 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1570 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1571 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 1572 1573 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 1574 1575 uint32_t EnabledAvfsModules[3]; //Sienna_Cichlid - 67 AVFS modules 1576 } AvfsFuseOverride_t; 1577 1578 typedef struct { 1579 AvfsFuseOverride_t AvfsFuseOverride; 1580 1581 uint32_t MmHubPadding[8]; // SMU internal use 1582 } AvfsFuseOverrideExternal_t; 1583 1584 typedef struct { 1585 uint8_t Gfx_ActiveHystLimit; 1586 uint8_t Gfx_IdleHystLimit; 1587 uint8_t Gfx_FPS; 1588 uint8_t Gfx_MinActiveFreqType; 1589 uint8_t Gfx_BoosterFreqType; 1590 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1591 uint16_t Gfx_MinActiveFreq; // MHz 1592 uint16_t Gfx_BoosterFreq; // MHz 1593 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1594 uint32_t Gfx_PD_Data_limit_a; // Q16 1595 uint32_t Gfx_PD_Data_limit_b; // Q16 1596 uint32_t Gfx_PD_Data_limit_c; // Q16 1597 uint32_t Gfx_PD_Data_error_coeff; // Q16 1598 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1599 1600 uint8_t Fclk_ActiveHystLimit; 1601 uint8_t Fclk_IdleHystLimit; 1602 uint8_t Fclk_FPS; 1603 uint8_t Fclk_MinActiveFreqType; 1604 uint8_t Fclk_BoosterFreqType; 1605 uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1606 uint16_t Fclk_MinActiveFreq; // MHz 1607 uint16_t Fclk_BoosterFreq; // MHz 1608 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1609 uint32_t Fclk_PD_Data_limit_a; // Q16 1610 uint32_t Fclk_PD_Data_limit_b; // Q16 1611 uint32_t Fclk_PD_Data_limit_c; // Q16 1612 uint32_t Fclk_PD_Data_error_coeff; // Q16 1613 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1614 1615 uint8_t Mem_ActiveHystLimit; 1616 uint8_t Mem_IdleHystLimit; 1617 uint8_t Mem_FPS; 1618 uint8_t Mem_MinActiveFreqType; 1619 uint8_t Mem_BoosterFreqType; 1620 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1621 uint16_t Mem_MinActiveFreq; // MHz 1622 uint16_t Mem_BoosterFreq; // MHz 1623 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 1624 uint32_t Mem_PD_Data_limit_a; // Q16 1625 uint32_t Mem_PD_Data_limit_b; // Q16 1626 uint32_t Mem_PD_Data_limit_c; // Q16 1627 uint32_t Mem_PD_Data_error_coeff; // Q16 1628 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 1629 1630 uint32_t Mem_UpThreshold_Limit; // Q16 1631 uint8_t Mem_UpHystLimit; 1632 uint8_t Mem_DownHystLimit; 1633 uint16_t Mem_Fps; 1634 1635 } DpmActivityMonitorCoeffInt_t; 1636 1637 1638 typedef struct { 1639 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1640 uint32_t MmHubPadding[8]; // SMU internal use 1641 } DpmActivityMonitorCoeffIntExternal_t; 1642 1643 // Workload bits 1644 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1645 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1646 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1647 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1648 #define WORKLOAD_PPLIB_VR_BIT 4 1649 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1650 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1651 #define WORKLOAD_PPLIB_W3D_BIT 7 1652 #define WORKLOAD_PPLIB_COUNT 8 1653 1654 1655 // These defines are used with the following messages: 1656 // SMC_MSG_TransferTableDram2Smu 1657 // SMC_MSG_TransferTableSmu2Dram 1658 1659 // Table transfer status 1660 #define TABLE_TRANSFER_OK 0x0 1661 #define TABLE_TRANSFER_FAILED 0xFF 1662 1663 // Table types 1664 #define TABLE_PPTABLE 0 1665 #define TABLE_WATERMARKS 1 1666 #define TABLE_AVFS_PSM_DEBUG 2 1667 #define TABLE_AVFS_FUSE_OVERRIDE 3 1668 #define TABLE_PMSTATUSLOG 4 1669 #define TABLE_SMU_METRICS 5 1670 #define TABLE_DRIVER_SMU_CONFIG 6 1671 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1672 #define TABLE_OVERDRIVE 8 1673 #define TABLE_I2C_COMMANDS 9 1674 #define TABLE_PACE 10 1675 #define TABLE_COUNT 11 1676 1677 typedef struct { 1678 float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; 1679 } RlcPaceFlopsPerByteOverride_t; 1680 1681 typedef struct { 1682 RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride; 1683 1684 uint32_t MmHubPadding[8]; // SMU internal use 1685 } RlcPaceFlopsPerByteOverrideExternal_t; 1686 1687 // These defines are used with the SMC_MSG_SetUclkFastSwitch message. 1688 #define UCLK_SWITCH_SLOW 0 1689 #define UCLK_SWITCH_FAST 1 1690 #define UCLK_SWITCH_DUMMY 2 1691 #endif 1692
