1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11 #ifndef __SOF_INTEL_HDA_H
12 #define __SOF_INTEL_HDA_H
13
14 #include <linux/soundwire/sdw.h>
15 #include <linux/soundwire/sdw_intel.h>
16 #include <sound/compress_driver.h>
17 #include <sound/hda_codec.h>
18 #include <sound/hdaudio_ext.h>
19 #include "../sof-client-probes.h"
20 #include "../sof-audio.h"
21 #include "shim.h"
22
23 /* PCI registers */
24 #define PCI_TCSEL 0x44
25 #define PCI_PGCTL PCI_TCSEL
26 #define PCI_CGCTL 0x48
27
28 /* PCI_PGCTL bits */
29 #define PCI_PGCTL_ADSPPGD BIT(2)
30 #define PCI_PGCTL_LSRMD_MASK BIT(4)
31
32 /* PCI_CGCTL bits */
33 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
34 #define PCI_CGCTL_ADSPDCGE BIT(1)
35
36 /* Legacy HDA registers and bits used - widths are variable */
37 #define SOF_HDA_GCAP 0x0
38 #define SOF_HDA_GCTL 0x8
39 /* accept unsol. response enable */
40 #define SOF_HDA_GCTL_UNSOL BIT(8)
41 #define SOF_HDA_LLCH 0x14
42 #define SOF_HDA_INTCTL 0x20
43 #define SOF_HDA_INTSTS 0x24
44 #define SOF_HDA_WAKESTS 0x0E
45 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
46 #define SOF_HDA_RIRBSTS 0x5d
47
48 /* SOF_HDA_GCTL register bist */
49 #define SOF_HDA_GCTL_RESET BIT(0)
50
51 /* SOF_HDA_INCTL regs */
52 #define SOF_HDA_INT_GLOBAL_EN BIT(31)
53 #define SOF_HDA_INT_CTRL_EN BIT(30)
54 #define SOF_HDA_INT_ALL_STREAM 0xff
55
56 /* SOF_HDA_INTSTS regs */
57 #define SOF_HDA_INTSTS_GIS BIT(31)
58
59 #define SOF_HDA_MAX_CAPS 10
60 #define SOF_HDA_CAP_ID_OFF 16
61 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
62 SOF_HDA_CAP_ID_OFF)
63 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF
64
65 #define SOF_HDA_GTS_CAP_ID 0x1
66 #define SOF_HDA_ML_CAP_ID 0x2
67
68 #define SOF_HDA_PP_CAP_ID 0x3
69 #define SOF_HDA_REG_PP_PPCH 0x10
70 #define SOF_HDA_REG_PP_PPCTL 0x04
71 #define SOF_HDA_REG_PP_PPSTS 0x08
72 #define SOF_HDA_PPCTL_PIE BIT(31)
73 #define SOF_HDA_PPCTL_GPROCEN BIT(30)
74
75 /*Vendor Specific Registers*/
76 #define SOF_HDA_VS_D0I3C 0x104A
77
78 /* D0I3C Register fields */
79 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
80 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */
81
82 /* DPIB entry size: 8 Bytes = 2 DWords */
83 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8
84
85 #define SOF_HDA_SPIB_CAP_ID 0x4
86 #define SOF_HDA_DRSM_CAP_ID 0x5
87
88 #define SOF_HDA_SPIB_BASE 0x08
89 #define SOF_HDA_SPIB_INTERVAL 0x08
90 #define SOF_HDA_SPIB_SPIB 0x00
91 #define SOF_HDA_SPIB_MAXFIFO 0x04
92
93 #define SOF_HDA_PPHC_BASE 0x10
94 #define SOF_HDA_PPHC_INTERVAL 0x10
95
96 #define SOF_HDA_PPLC_BASE 0x10
97 #define SOF_HDA_PPLC_MULTI 0x10
98 #define SOF_HDA_PPLC_INTERVAL 0x10
99
100 #define SOF_HDA_DRSM_BASE 0x08
101 #define SOF_HDA_DRSM_INTERVAL 0x08
102
103 /* Descriptor error interrupt */
104 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
105
106 /* FIFO error interrupt */
107 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
108
109 /* Buffer completion interrupt */
110 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
111
112 #define SOF_HDA_CL_DMA_SD_INT_MASK \
113 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
114 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
115 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
116 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
117
118 /* Intel HD Audio Code Loader DMA Registers */
119 #define SOF_HDA_ADSP_LOADER_BASE 0x80
120 #define SOF_HDA_ADSP_DPLBASE 0x70
121 #define SOF_HDA_ADSP_DPUBASE 0x74
122 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
123
124 /* Stream Registers */
125 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
126 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
127 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
128 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
129 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
130 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
131 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
132 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
133 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
134 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
135 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
136 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
137
138 /* CL: Software Position Based FIFO Capability Registers */
139 #define SOF_DSP_REG_CL_SPBFIFO \
140 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
143 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
144 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
145
146 /* Stream Number */
147 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
148 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
149 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
150 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
151
152 #define HDA_DSP_HDA_BAR 0
153 #define HDA_DSP_PP_BAR 1
154 #define HDA_DSP_SPIB_BAR 2
155 #define HDA_DSP_DRSM_BAR 3
156 #define HDA_DSP_BAR 4
157
158 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
159
160 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
161
162 #define HDA_DSP_PANIC_OFFSET(x) \
163 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
164
165 /* SRAM window 0 FW "registers" */
166 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
167 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
168 /* FW and ROM share offset 4 */
169 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
170 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
171 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
172
173 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
174
175 #define HDA_DSP_STREAM_RESET_TIMEOUT 300
176 /*
177 * Timeout in us, for setting the stream RUN bit, during
178 * start/stop the stream. The timeout expires if new RUN bit
179 * value cannot be read back within the specified time.
180 */
181 #define HDA_DSP_STREAM_RUN_TIMEOUT 300
182
183 #define HDA_DSP_SPIB_ENABLE 1
184 #define HDA_DSP_SPIB_DISABLE 0
185
186 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
187
188 #define HDA_DSP_STACK_DUMP_SIZE 32
189
190 /* ROM/FW status register */
191 #define FSR_STATE_MASK GENMASK(23, 0)
192 #define FSR_WAIT_STATE_MASK GENMASK(27, 24)
193 #define FSR_MODULE_MASK GENMASK(30, 28)
194 #define FSR_HALTED BIT(31)
195 #define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK)
196 #define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24)
197 #define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28)
198
199 /* Wait states */
200 #define FSR_WAIT_FOR_IPC_BUSY 0x1
201 #define FSR_WAIT_FOR_IPC_DONE 0x2
202 #define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3
203 #define FSR_WAIT_FOR_LP_SRAM_OFF 0x4
204 #define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5
205 #define FSR_WAIT_FOR_CSE_CSR 0x6
206
207 /* Module codes */
208 #define FSR_MOD_ROM 0x0
209 #define FSR_MOD_ROM_BYP 0x1
210 #define FSR_MOD_BASE_FW 0x2
211 #define FSR_MOD_LP_BOOT 0x3
212 #define FSR_MOD_BRNGUP 0x4
213 #define FSR_MOD_ROM_EXT 0x5
214
215 /* State codes (module dependent) */
216 /* Module independent states */
217 #define FSR_STATE_INIT 0x0
218 #define FSR_STATE_INIT_DONE 0x1
219 #define FSR_STATE_FW_ENTERED 0x5
220
221 /* ROM states */
222 #define FSR_STATE_ROM_INIT FSR_STATE_INIT
223 #define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE
224 #define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2
225 #define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3
226 #define FSR_STATE_ROM_FW_FW_LOADED 0x4
227 #define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED
228 #define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6
229 #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7
230 #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8
231 #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9
232 #define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */
233
234 /* (ROM) CSE states */
235 #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10
236 #define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11
237 #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12
238 #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13
239
240 #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20
241 #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21
242 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22
243 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23
244 #define FSR_STATE_ROM_CSE_IPC_DOWN 0x24
245
246 /* BRINGUP (or BRNGUP) states */
247 #define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT
248 #define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE
249 #define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2
250 #define FSR_STATE_BRINGUP_UNPACK_START 0X3
251 #define FSR_STATE_BRINGUP_IMR_RESTORE 0x4
252 #define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED
253
254 /* ROM status/error values */
255 #define HDA_DSP_ROM_CSE_ERROR 40
256 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
257 #define HDA_DSP_ROM_IMR_TO_SMALL 42
258 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
259 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
260 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45
261 #define HDA_DSP_ROM_L2_CACHE_ERROR 46
262 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
263 #define HDA_DSP_ROM_API_PTR_INVALID 50
264 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51
265 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
266 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
267 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
268 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
269 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
270 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
271
272 #define HDA_DSP_ROM_IPC_CONTROL 0x01000000
273 #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000
274
275 /* various timeout values */
276 #define HDA_DSP_PU_TIMEOUT 50
277 #define HDA_DSP_PD_TIMEOUT 50
278 #define HDA_DSP_RESET_TIMEOUT_US 50000
279 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000
280 #define HDA_DSP_INIT_TIMEOUT_US 500000
281 #define HDA_DSP_CTRL_RESET_TIMEOUT 100
282 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
283 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
284 #define HDA_DSP_REG_POLL_RETRY_COUNT 50
285
286 #define HDA_DSP_ADSPIC_IPC BIT(0)
287 #define HDA_DSP_ADSPIS_IPC BIT(0)
288
289 /* Intel HD Audio General DSP Registers */
290 #define HDA_DSP_GEN_BASE 0x0
291 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
292 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
293 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
294 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
295 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
296
297 #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
298
299 /* Intel HD Audio Inter-Processor Communication Registers */
300 #define HDA_DSP_IPC_BASE 0x40
301 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
302 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
303 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
304 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
305 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
306
307 /* Intel Vendor Specific Registers */
308 #define HDA_VS_INTEL_EM2 0x1030
309 #define HDA_VS_INTEL_EM2_L1SEN BIT(13)
310 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
311
312 /* HIPCI */
313 #define HDA_DSP_REG_HIPCI_BUSY BIT(31)
314 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
315
316 /* HIPCIE */
317 #define HDA_DSP_REG_HIPCIE_DONE BIT(30)
318 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
319
320 /* HIPCCTL */
321 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
322 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
323
324 /* HIPCT */
325 #define HDA_DSP_REG_HIPCT_BUSY BIT(31)
326 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
327
328 /* HIPCTE */
329 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
330
331 #define HDA_DSP_ADSPIC_CL_DMA BIT(1)
332 #define HDA_DSP_ADSPIS_CL_DMA BIT(1)
333
334 /* Delay before scheduling D0i3 entry */
335 #define BXT_D0I3_DELAY 5000
336
337 #define FW_CL_STREAM_NUMBER 0x1
338 #define HDA_FW_BOOT_ATTEMPTS 3
339
340 /* ADSPCS - Audio DSP Control & Status */
341
342 /*
343 * Core Reset - asserted high
344 * CRST Mask for a given core mask pattern, cm
345 */
346 #define HDA_DSP_ADSPCS_CRST_SHIFT 0
347 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
348
349 /*
350 * Core run/stall - when set to '1' core is stalled
351 * CSTALL Mask for a given core mask pattern, cm
352 */
353 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
354 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
355
356 /*
357 * Set Power Active - when set to '1' turn cores on
358 * SPA Mask for a given core mask pattern, cm
359 */
360 #define HDA_DSP_ADSPCS_SPA_SHIFT 16
361 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
362
363 /*
364 * Current Power Active - power status of cores, set by hardware
365 * CPA Mask for a given core mask pattern, cm
366 */
367 #define HDA_DSP_ADSPCS_CPA_SHIFT 24
368 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
369
370 /*
371 * Mask for a given number of cores
372 * nc = number of supported cores
373 */
374 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
375
376 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
377 #define CNL_DSP_IPC_BASE 0xc0
378 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
379 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
380 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
381 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
382 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
383 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
384 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
385
386 /* HIPCI */
387 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
388 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
389
390 /* HIPCIE */
391 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
392 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
393
394 /* HIPCCTL */
395 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
396 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
397
398 /* HIPCT */
399 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
400 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
401
402 /* HIPCTDA */
403 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
404 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
405
406 /* HIPCTDD */
407 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
408
409 /* BDL */
410 #define HDA_DSP_BDL_SIZE 4096
411 #define HDA_DSP_MAX_BDL_ENTRIES \
412 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
413
414 /* Number of DAIs */
415 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
416 #define SOF_SKL_NUM_DAIS 15
417 #else
418 #define SOF_SKL_NUM_DAIS 8
419 #endif
420
421 /* Intel HD Audio SRAM Window 0*/
422 #define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000
423 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000
424
425 /* Firmware status window */
426 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
427 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
428
429 /* Host Device Memory Space */
430 #define APL_SSP_BASE_OFFSET 0x2000
431 #define CNL_SSP_BASE_OFFSET 0x10000
432
433 /* Host Device Memory Size of a Single SSP */
434 #define SSP_DEV_MEM_SIZE 0x1000
435
436 /* SSP Count of the Platform */
437 #define APL_SSP_COUNT 6
438 #define CNL_SSP_COUNT 3
439 #define ICL_SSP_COUNT 6
440 #define TGL_SSP_COUNT 3
441 #define MTL_SSP_COUNT 3
442
443 /* SSP Registers */
444 #define SSP_SSC1_OFFSET 0x4
445 #define SSP_SET_SCLK_CONSUMER BIT(25)
446 #define SSP_SET_SFRM_CONSUMER BIT(24)
447 #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER)
448
449 #define HDA_IDISP_ADDR 2
450 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
451
452 struct sof_intel_dsp_bdl {
453 __le32 addr_l;
454 __le32 addr_h;
455 __le32 size;
456 __le32 ioc;
457 } __attribute((packed));
458
459 #define SOF_HDA_PLAYBACK_STREAMS 16
460 #define SOF_HDA_CAPTURE_STREAMS 16
461 #define SOF_HDA_PLAYBACK 0
462 #define SOF_HDA_CAPTURE 1
463
464 /* stream flags */
465 #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1
466
467 /*
468 * Time in ms for opportunistic D0I3 entry delay.
469 * This has been deliberately chosen to be long to avoid race conditions.
470 * Could be optimized in future.
471 */
472 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000
473
474 /* HDA DSP D0 substate */
475 enum sof_hda_D0_substate {
476 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */
477 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */
478 };
479
480 /* represents DSP HDA controller frontend - i.e. host facing control */
481 struct sof_intel_hda_dev {
482 bool imrboot_supported;
483 bool skip_imr_boot;
484
485 int boot_iteration;
486
487 struct hda_bus hbus;
488
489 /* hw config */
490 const struct sof_intel_dsp_desc *desc;
491
492 /* trace */
493 struct hdac_ext_stream *dtrace_stream;
494
495 /* if position update IPC needed */
496 u32 no_ipc_position;
497
498 /* the maximum number of streams (playback + capture) supported */
499 u32 stream_max;
500
501 /* PM related */
502 bool l1_support_changed;/* during suspend, is L1SEN changed or not */
503
504 /* DMIC device */
505 struct platform_device *dmic_dev;
506
507 /* delayed work to enter D0I3 opportunistically */
508 struct delayed_work d0i3_work;
509
510 /* ACPI information stored between scan and probe steps */
511 struct sdw_intel_acpi_info info;
512
513 /* sdw context allocated by SoundWire driver */
514 struct sdw_intel_ctx *sdw;
515
516 /* FW clock config, 0:HPRO, 1:LPRO */
517 bool clk_config_lpro;
518
519 wait_queue_head_t waitq;
520 bool code_loading;
521
522 /* Intel NHLT information */
523 struct nhlt_acpi_table *nhlt;
524 };
525
sof_to_bus(struct snd_sof_dev * s)526 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
527 {
528 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
529
530 return &hda->hbus.core;
531 }
532
sof_to_hbus(struct snd_sof_dev * s)533 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
534 {
535 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
536
537 return &hda->hbus;
538 }
539
540 struct sof_intel_hda_stream {
541 struct snd_sof_dev *sdev;
542 struct hdac_ext_stream hext_stream;
543 struct sof_intel_stream sof_intel_stream;
544 int host_reserved; /* reserve host DMA channel */
545 u32 flags;
546 };
547
548 #define hstream_to_sof_hda_stream(hstream) \
549 container_of(hstream, struct sof_intel_hda_stream, hext_stream)
550
551 #define bus_to_sof_hda(bus) \
552 container_of(bus, struct sof_intel_hda_dev, hbus.core)
553
554 #define SOF_STREAM_SD_OFFSET(s) \
555 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
556 + SOF_HDA_ADSP_LOADER_BASE)
557
558 #define SOF_STREAM_SD_OFFSET_CRST 0x1
559
560 /*
561 * DSP Core services.
562 */
563 int hda_dsp_probe(struct snd_sof_dev *sdev);
564 int hda_dsp_remove(struct snd_sof_dev *sdev);
565 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
566 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
567 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
568 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
569 unsigned int core_mask);
570 int hda_power_down_dsp(struct snd_sof_dev *sdev);
571 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core);
572 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
573 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
574 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask);
575
576 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
577 const struct sof_dsp_power_state *target_state);
578
579 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
580 int hda_dsp_resume(struct snd_sof_dev *sdev);
581 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
582 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
583 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
584 int hda_dsp_shutdown(struct snd_sof_dev *sdev);
585 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
586 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
587 void hda_ipc_dump(struct snd_sof_dev *sdev);
588 void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
589 void hda_dsp_d0i3_work(struct work_struct *work);
590 int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev);
591
592 /*
593 * DSP PCM Operations.
594 */
595 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
596 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
597 int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
598 struct snd_pcm_substream *substream);
599 int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
600 struct snd_pcm_substream *substream);
601 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
602 struct snd_pcm_substream *substream,
603 struct snd_pcm_hw_params *params,
604 struct snd_sof_platform_stream_params *platform_params);
605 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
606 struct snd_pcm_substream *substream);
607 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
608 struct snd_pcm_substream *substream, int cmd);
609 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
610 struct snd_pcm_substream *substream);
611 int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
612
613 /*
614 * DSP Stream Operations.
615 */
616
617 int hda_dsp_stream_init(struct snd_sof_dev *sdev);
618 void hda_dsp_stream_free(struct snd_sof_dev *sdev);
619 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
620 struct hdac_ext_stream *hext_stream,
621 struct snd_dma_buffer *dmab,
622 struct snd_pcm_hw_params *params);
623 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev,
624 struct hdac_ext_stream *hext_stream,
625 struct snd_dma_buffer *dmab,
626 struct snd_pcm_hw_params *params);
627 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
628 struct hdac_ext_stream *hext_stream, int cmd);
629 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
630 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
631 struct snd_dma_buffer *dmab,
632 struct hdac_stream *hstream);
633 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
634 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
635
636 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
637 int direction, bool can_sleep);
638
639 struct hdac_ext_stream *
640 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
641 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
642 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
643 struct hdac_ext_stream *hext_stream,
644 int enable, u32 size);
645
646 int hda_ipc_msg_data(struct snd_sof_dev *sdev,
647 struct snd_pcm_substream *substream,
648 void *p, size_t sz);
649 int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
650 struct snd_pcm_substream *substream,
651 size_t posn_offset);
652
653 /*
654 * DSP IPC Operations.
655 */
656 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
657 struct snd_sof_ipc_msg *msg);
658 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
659 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
660 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
661
662 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
663 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
664
665 /*
666 * DSP Code loader.
667 */
668 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
669 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
670 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream);
671 struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
672 unsigned int size, struct snd_dma_buffer *dmab,
673 int direction);
674 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
675 struct hdac_ext_stream *hext_stream);
676 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
677 #define HDA_CL_STREAM_FORMAT 0x40
678
679 /* pre and post fw run ops */
680 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
681 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
682
683 /* parse platform specific ext manifest ops */
684 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
685 const struct sof_ext_man_elem_header *hdr);
686
687 /*
688 * HDA Controller Operations.
689 */
690 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
691 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
692 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
693 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
694 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
695 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
696 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
697 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
698 /*
699 * HDA bus operations.
700 */
701 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
702
703 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
704 /*
705 * HDA Codec operations.
706 */
707 void hda_codec_probe_bus(struct snd_sof_dev *sdev,
708 bool hda_codec_use_common_hdmi);
709 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
710 void hda_codec_jack_check(struct snd_sof_dev *sdev);
711
712 #endif /* CONFIG_SND_SOC_SOF_HDA */
713
714 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
715 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
716 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
717
718 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
719 int hda_codec_i915_init(struct snd_sof_dev *sdev);
720 int hda_codec_i915_exit(struct snd_sof_dev *sdev);
721
722 #else
723
hda_codec_i915_display_power(struct snd_sof_dev * sdev,bool enable)724 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
725 bool enable) { }
hda_codec_i915_init(struct snd_sof_dev * sdev)726 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
hda_codec_i915_exit(struct snd_sof_dev * sdev)727 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
728
729 #endif
730
731 /*
732 * Trace Control.
733 */
734 int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
735 struct sof_ipc_dma_trace_params_ext *dtrace_params);
736 int hda_dsp_trace_release(struct snd_sof_dev *sdev);
737 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
738
739 /*
740 * SoundWire support
741 */
742 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
743
744 int hda_sdw_startup(struct snd_sof_dev *sdev);
745 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
746 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
747 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
748
749 #else
750
hda_sdw_startup(struct snd_sof_dev * sdev)751 static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
752 {
753 return 0;
754 }
755
hda_sdw_int_enable(struct snd_sof_dev * sdev,bool enable)756 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
757 {
758 }
759
hda_sdw_process_wakeen(struct snd_sof_dev * sdev)760 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
761 {
762 }
763
hda_common_check_sdw_irq(struct snd_sof_dev * sdev)764 static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
765 {
766 return false;
767 }
768
769 #endif
770
771 /* common dai driver */
772 extern struct snd_soc_dai_driver skl_dai[];
773 int hda_dsp_dais_suspend(struct snd_sof_dev *sdev);
774
775 /*
776 * Platform Specific HW abstraction Ops.
777 */
778 extern struct snd_sof_dsp_ops sof_hda_common_ops;
779
780 extern struct snd_sof_dsp_ops sof_skl_ops;
781 int sof_skl_ops_init(struct snd_sof_dev *sdev);
782 extern struct snd_sof_dsp_ops sof_apl_ops;
783 int sof_apl_ops_init(struct snd_sof_dev *sdev);
784 extern struct snd_sof_dsp_ops sof_cnl_ops;
785 int sof_cnl_ops_init(struct snd_sof_dev *sdev);
786 extern struct snd_sof_dsp_ops sof_tgl_ops;
787 int sof_tgl_ops_init(struct snd_sof_dev *sdev);
788 extern struct snd_sof_dsp_ops sof_icl_ops;
789 int sof_icl_ops_init(struct snd_sof_dev *sdev);
790 extern struct snd_sof_dsp_ops sof_mtl_ops;
791 int sof_mtl_ops_init(struct snd_sof_dev *sdev);
792
793 extern const struct sof_intel_dsp_desc skl_chip_info;
794 extern const struct sof_intel_dsp_desc apl_chip_info;
795 extern const struct sof_intel_dsp_desc cnl_chip_info;
796 extern const struct sof_intel_dsp_desc icl_chip_info;
797 extern const struct sof_intel_dsp_desc tgl_chip_info;
798 extern const struct sof_intel_dsp_desc tglh_chip_info;
799 extern const struct sof_intel_dsp_desc ehl_chip_info;
800 extern const struct sof_intel_dsp_desc jsl_chip_info;
801 extern const struct sof_intel_dsp_desc adls_chip_info;
802 extern const struct sof_intel_dsp_desc mtl_chip_info;
803
804 /* Probes support */
805 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
806 int hda_probes_register(struct snd_sof_dev *sdev);
807 void hda_probes_unregister(struct snd_sof_dev *sdev);
808 #else
hda_probes_register(struct snd_sof_dev * sdev)809 static inline int hda_probes_register(struct snd_sof_dev *sdev)
810 {
811 return 0;
812 }
813
hda_probes_unregister(struct snd_sof_dev * sdev)814 static inline void hda_probes_unregister(struct snd_sof_dev *sdev)
815 {
816 }
817 #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */
818
819 /* SOF client registration for HDA platforms */
820 int hda_register_clients(struct snd_sof_dev *sdev);
821 void hda_unregister_clients(struct snd_sof_dev *sdev);
822
823 /* machine driver select */
824 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev);
825 void hda_set_mach_params(struct snd_soc_acpi_mach *mach,
826 struct snd_sof_dev *sdev);
827
828 /* PCI driver selection and probe */
829 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
830
831 struct snd_sof_dai;
832 struct sof_ipc_dai_config;
833 int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags,
834 struct snd_sof_dai_config_data *data);
835 int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags,
836 struct snd_sof_dai_config_data *data);
837
838 #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */
839 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */
840 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */
841
842 extern int sof_hda_position_quirk;
843
844 void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops);
845 void hda_ops_free(struct snd_sof_dev *sdev);
846
847 /* SKL/KBL */
848 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
849 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
850
851 /* IPC4 */
852 irqreturn_t cnl_ipc4_irq_thread(int irq, void *context);
853 int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
854 irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context);
855 int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
856 void hda_ipc4_dump(struct snd_sof_dev *sdev);
857 extern struct sdw_intel_ops sdw_callback;
858
859 #endif
860
