1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009-2016 Cavium, Inc.
7 */
8
9 enum cavium_mdiobus_mode {
10 UNINIT = 0,
11 C22,
12 C45
13 };
14
15 #define SMI_CMD 0x0
16 #define SMI_WR_DAT 0x8
17 #define SMI_RD_DAT 0x10
18 #define SMI_CLK 0x18
19 #define SMI_EN 0x20
20
21 #ifdef __BIG_ENDIAN_BITFIELD
22 #define OCT_MDIO_BITFIELD_FIELD(field, more) \
23 field; \
24 more
25
26 #else
27 #define OCT_MDIO_BITFIELD_FIELD(field, more) \
28 more \
29 field;
30
31 #endif
32
33 union cvmx_smix_clk {
34 u64 u64;
35 struct cvmx_smix_clk_s {
36 OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
37 OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
38 OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
39 OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
40 OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
41 OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
42 OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
43 OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
44 OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
45 OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
46 ;))))))))))
47 } s;
48 };
49
50 union cvmx_smix_cmd {
51 u64 u64;
52 struct cvmx_smix_cmd_s {
53 OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
54 OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
55 OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
56 OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
57 OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
58 OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
59 ;))))))
60 } s;
61 };
62
63 union cvmx_smix_en {
64 u64 u64;
65 struct cvmx_smix_en_s {
66 OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
67 OCT_MDIO_BITFIELD_FIELD(u64 en:1,
68 ;))
69 } s;
70 };
71
72 union cvmx_smix_rd_dat {
73 u64 u64;
74 struct cvmx_smix_rd_dat_s {
75 OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
76 OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
77 OCT_MDIO_BITFIELD_FIELD(u64 val:1,
78 OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
79 ;))))
80 } s;
81 };
82
83 union cvmx_smix_wr_dat {
84 u64 u64;
85 struct cvmx_smix_wr_dat_s {
86 OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
87 OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
88 OCT_MDIO_BITFIELD_FIELD(u64 val:1,
89 OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
90 ;))))
91 } s;
92 };
93
94 struct cavium_mdiobus {
95 struct mii_bus *mii_bus;
96 u64 register_base;
97 enum cavium_mdiobus_mode mode;
98 };
99
100 #ifdef CONFIG_CAVIUM_OCTEON_SOC
101
102 #include <asm/octeon/octeon.h>
103
oct_mdio_writeq(u64 val,u64 addr)104 static inline void oct_mdio_writeq(u64 val, u64 addr)
105 {
106 cvmx_write_csr(addr, val);
107 }
108
oct_mdio_readq(u64 addr)109 static inline u64 oct_mdio_readq(u64 addr)
110 {
111 return cvmx_read_csr(addr);
112 }
113 #else
114 #define oct_mdio_writeq(val, addr) writeq(val, (void *)addr)
115 #define oct_mdio_readq(addr) readq((void *)addr)
116 #endif
117
118 int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum);
119 int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val);
120
