1 /* 2 * SuperH Pin Function Controller Support 3 * 4 * Copyright (c) 2008 Magnus Damm 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #ifndef __SH_PFC_H 12 #define __SH_PFC_H 13 14 #include <linux/bug.h> 15 #include <linux/pinctrl/pinconf-generic.h> 16 #include <linux/spinlock.h> 17 #include <linux/stringify.h> 18 19 enum { 20 PINMUX_TYPE_NONE, 21 PINMUX_TYPE_FUNCTION, 22 PINMUX_TYPE_GPIO, 23 PINMUX_TYPE_OUTPUT, 24 PINMUX_TYPE_INPUT, 25 }; 26 27 #define SH_PFC_PIN_CFG_INPUT (1 << 0) 28 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) 29 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) 30 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) 31 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) 32 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) 33 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) 34 35 struct sh_pfc_pin { 36 u16 pin; 37 u16 enum_id; 38 const char *name; 39 unsigned int configs; 40 }; 41 42 #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ 43 { \ 44 .name = #alias, \ 45 .pins = n##_pins, \ 46 .mux = n##_mux, \ 47 .nr_pins = ARRAY_SIZE(n##_pins), \ 48 } 49 #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) 50 51 struct sh_pfc_pin_group { 52 const char *name; 53 const unsigned int *pins; 54 const unsigned int *mux; 55 unsigned int nr_pins; 56 }; 57 58 /* 59 * Using union vin_data saves memory occupied by the VIN data pins. 60 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups 61 * in this case. 62 */ 63 #define VIN_DATA_PIN_GROUP(n, s) \ 64 { \ 65 .name = #n#s, \ 66 .pins = n##_pins.data##s, \ 67 .mux = n##_mux.data##s, \ 68 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ 69 } 70 71 union vin_data { 72 unsigned int data24[24]; 73 unsigned int data20[20]; 74 unsigned int data16[16]; 75 unsigned int data12[12]; 76 unsigned int data10[10]; 77 unsigned int data8[8]; 78 unsigned int data4[4]; 79 }; 80 81 #define SH_PFC_FUNCTION(n) \ 82 { \ 83 .name = #n, \ 84 .groups = n##_groups, \ 85 .nr_groups = ARRAY_SIZE(n##_groups), \ 86 } 87 88 struct sh_pfc_function { 89 const char *name; 90 const char * const *groups; 91 unsigned int nr_groups; 92 }; 93 94 struct pinmux_func { 95 u16 enum_id; 96 const char *name; 97 }; 98 99 struct pinmux_cfg_reg { 100 u32 reg; 101 u8 reg_width, field_width; 102 const u16 *enum_ids; 103 const u8 *var_field_width; 104 }; 105 106 /* 107 * Describe a config register consisting of several fields of the same width 108 * - name: Register name (unused, for documentation purposes only) 109 * - r: Physical register address 110 * - r_width: Width of the register (in bits) 111 * - f_width: Width of the fixed-width register fields (in bits) 112 * This macro must be followed by initialization data: For each register field 113 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified, 114 * one for each possible combination of the register field bit values. 115 */ 116 #define PINMUX_CFG_REG(name, r, r_width, f_width) \ 117 .reg = r, .reg_width = r_width, .field_width = f_width, \ 118 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) 119 120 /* 121 * Describe a config register consisting of several fields of different widths 122 * - name: Register name (unused, for documentation purposes only) 123 * - r: Physical register address 124 * - r_width: Width of the register (in bits) 125 * - var_fw0, var_fwn...: List of widths of the register fields (in bits), 126 * From left to right (i.e. MSB to LSB) 127 * This macro must be followed by initialization data: For each register field 128 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified, 129 * one for each possible combination of the register field bit values. 130 */ 131 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ 132 .reg = r, .reg_width = r_width, \ 133 .var_field_width = (const u8 [r_width]) \ 134 { var_fw0, var_fwn, 0 }, \ 135 .enum_ids = (const u16 []) 136 137 struct pinmux_drive_reg_field { 138 u16 pin; 139 u8 offset; 140 u8 size; 141 }; 142 143 struct pinmux_drive_reg { 144 u32 reg; 145 const struct pinmux_drive_reg_field fields[8]; 146 }; 147 148 #define PINMUX_DRIVE_REG(name, r) \ 149 .reg = r, \ 150 .fields = 151 152 struct pinmux_bias_reg { 153 u32 puen; /* Pull-enable or pull-up control register */ 154 u32 pud; /* Pull-up/down control register (optional) */ 155 const u16 pins[32]; 156 }; 157 158 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \ 159 .puen = r1, \ 160 .pud = r2, \ 161 .pins = 162 163 struct pinmux_ioctrl_reg { 164 u32 reg; 165 }; 166 167 struct pinmux_data_reg { 168 u32 reg; 169 u8 reg_width; 170 const u16 *enum_ids; 171 }; 172 173 /* 174 * Describe a data register 175 * - name: Register name (unused, for documentation purposes only) 176 * - r: Physical register address 177 * - r_width: Width of the register (in bits) 178 * This macro must be followed by initialization data: For each register bit 179 * (from left to right, i.e. MSB to LSB), one enum ID must be specified. 180 */ 181 #define PINMUX_DATA_REG(name, r, r_width) \ 182 .reg = r, .reg_width = r_width, \ 183 .enum_ids = (const u16 [r_width]) \ 184 185 struct pinmux_irq { 186 const short *gpios; 187 }; 188 189 /* 190 * Describe the mapping from GPIOs to a single IRQ 191 * - ids...: List of GPIOs that are mapped to the same IRQ 192 */ 193 #define PINMUX_IRQ(ids...) \ 194 { .gpios = (const short []) { ids, -1 } } 195 196 struct pinmux_range { 197 u16 begin; 198 u16 end; 199 u16 force; 200 }; 201 202 struct sh_pfc_window { 203 phys_addr_t phys; 204 void __iomem *virt; 205 unsigned long size; 206 }; 207 208 struct sh_pfc_pin_range; 209 210 struct sh_pfc { 211 struct device *dev; 212 const struct sh_pfc_soc_info *info; 213 spinlock_t lock; 214 215 unsigned int num_windows; 216 struct sh_pfc_window *windows; 217 unsigned int num_irqs; 218 unsigned int *irqs; 219 220 struct sh_pfc_pin_range *ranges; 221 unsigned int nr_ranges; 222 223 unsigned int nr_gpio_pins; 224 225 struct sh_pfc_chip *gpio; 226 u32 *saved_regs; 227 }; 228 229 struct sh_pfc_soc_operations { 230 int (*init)(struct sh_pfc *pfc); 231 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 232 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 233 unsigned int bias); 234 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); 235 }; 236 237 struct sh_pfc_soc_info { 238 const char *name; 239 const struct sh_pfc_soc_operations *ops; 240 241 struct pinmux_range input; 242 struct pinmux_range output; 243 struct pinmux_range function; 244 245 const struct sh_pfc_pin *pins; 246 unsigned int nr_pins; 247 const struct sh_pfc_pin_group *groups; 248 unsigned int nr_groups; 249 const struct sh_pfc_function *functions; 250 unsigned int nr_functions; 251 252 #ifdef CONFIG_SUPERH 253 const struct pinmux_func *func_gpios; 254 unsigned int nr_func_gpios; 255 #endif 256 257 const struct pinmux_cfg_reg *cfg_regs; 258 const struct pinmux_drive_reg *drive_regs; 259 const struct pinmux_bias_reg *bias_regs; 260 const struct pinmux_ioctrl_reg *ioctrl_regs; 261 const struct pinmux_data_reg *data_regs; 262 263 const u16 *pinmux_data; 264 unsigned int pinmux_data_size; 265 266 const struct pinmux_irq *gpio_irq; 267 unsigned int gpio_irq_size; 268 269 u32 unlock_reg; 270 }; 271 272 extern const struct sh_pfc_soc_info emev2_pinmux_info; 273 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; 274 extern const struct sh_pfc_soc_info r8a7740_pinmux_info; 275 extern const struct sh_pfc_soc_info r8a7743_pinmux_info; 276 extern const struct sh_pfc_soc_info r8a7745_pinmux_info; 277 extern const struct sh_pfc_soc_info r8a77470_pinmux_info; 278 extern const struct sh_pfc_soc_info r8a7778_pinmux_info; 279 extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 280 extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 281 extern const struct sh_pfc_soc_info r8a7791_pinmux_info; 282 extern const struct sh_pfc_soc_info r8a7792_pinmux_info; 283 extern const struct sh_pfc_soc_info r8a7793_pinmux_info; 284 extern const struct sh_pfc_soc_info r8a7794_pinmux_info; 285 extern const struct sh_pfc_soc_info r8a7795_pinmux_info; 286 extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; 287 extern const struct sh_pfc_soc_info r8a7796_pinmux_info; 288 extern const struct sh_pfc_soc_info r8a77965_pinmux_info; 289 extern const struct sh_pfc_soc_info r8a77970_pinmux_info; 290 extern const struct sh_pfc_soc_info r8a77980_pinmux_info; 291 extern const struct sh_pfc_soc_info r8a77990_pinmux_info; 292 extern const struct sh_pfc_soc_info r8a77995_pinmux_info; 293 extern const struct sh_pfc_soc_info sh7203_pinmux_info; 294 extern const struct sh_pfc_soc_info sh7264_pinmux_info; 295 extern const struct sh_pfc_soc_info sh7269_pinmux_info; 296 extern const struct sh_pfc_soc_info sh73a0_pinmux_info; 297 extern const struct sh_pfc_soc_info sh7720_pinmux_info; 298 extern const struct sh_pfc_soc_info sh7722_pinmux_info; 299 extern const struct sh_pfc_soc_info sh7723_pinmux_info; 300 extern const struct sh_pfc_soc_info sh7724_pinmux_info; 301 extern const struct sh_pfc_soc_info sh7734_pinmux_info; 302 extern const struct sh_pfc_soc_info sh7757_pinmux_info; 303 extern const struct sh_pfc_soc_info sh7785_pinmux_info; 304 extern const struct sh_pfc_soc_info sh7786_pinmux_info; 305 extern const struct sh_pfc_soc_info shx3_pinmux_info; 306 307 /* ----------------------------------------------------------------------------- 308 * Helper macros to create pin and port lists 309 */ 310 311 /* 312 * sh_pfc_soc_info pinmux_data array macros 313 */ 314 315 /* 316 * Describe generic pinmux data 317 * - data_or_mark: *_DATA or *_MARK enum ID 318 * - ids...: List of enum IDs to associate with data_or_mark 319 */ 320 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 321 322 /* 323 * Describe a pinmux configuration without GPIO function that needs 324 * configuration in a Peripheral Function Select Register (IPSR) 325 * - ipsr: IPSR field (unused, for documentation purposes only) 326 * - fn: Function name, referring to a field in the IPSR 327 */ 328 #define PINMUX_IPSR_NOGP(ipsr, fn) \ 329 PINMUX_DATA(fn##_MARK, FN_##fn) 330 331 /* 332 * Describe a pinmux configuration with GPIO function that needs configuration 333 * in both a Peripheral Function Select Register (IPSR) and in a 334 * GPIO/Peripheral Function Select Register (GPSR) 335 * - ipsr: IPSR field 336 * - fn: Function name, also referring to the IPSR field 337 */ 338 #define PINMUX_IPSR_GPSR(ipsr, fn) \ 339 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) 340 341 /* 342 * Describe a pinmux configuration without GPIO function that needs 343 * configuration in a Peripheral Function Select Register (IPSR), and where the 344 * pinmux function has a representation in a Module Select Register (MOD_SEL). 345 * - ipsr: IPSR field (unused, for documentation purposes only) 346 * - fn: Function name, also referring to the IPSR field 347 * - msel: Module selector 348 */ 349 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \ 350 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel) 351 352 /* 353 * Describe a pinmux configuration with GPIO function where the pinmux function 354 * has no representation in a Peripheral Function Select Register (IPSR), but 355 * instead solely depends on a group selection. 356 * - gpsr: GPSR field 357 * - fn: Function name, also referring to the GPSR field 358 * - gsel: Group selector 359 */ 360 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \ 361 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel) 362 363 /* 364 * Describe a pinmux configuration with GPIO function that needs configuration 365 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral 366 * Function Select Register (GPSR), and where the pinmux function has a 367 * representation in a Module Select Register (MOD_SEL). 368 * - ipsr: IPSR field 369 * - fn: Function name, also referring to the IPSR field 370 * - msel: Module selector 371 */ 372 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ 373 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) 374 375 /* 376 * Describe a pinmux configuration for a single-function pin with GPIO 377 * capability. 378 * - fn: Function name 379 */ 380 #define PINMUX_SINGLE(fn) \ 381 PINMUX_DATA(fn##_MARK, FN_##fn) 382 383 /* 384 * GP port style (32 ports banks) 385 */ 386 387 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ 388 fn(bank, pin, GP_##bank##_##pin, sfx, cfg) 389 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) 390 391 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ 392 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ 393 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ 394 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ 395 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) 396 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) 397 398 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ 399 PORT_GP_CFG_4(bank, fn, sfx, cfg), \ 400 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ 401 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) 402 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) 403 404 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ 405 PORT_GP_CFG_6(bank, fn, sfx, cfg), \ 406 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ 407 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) 408 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) 409 410 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ 411 PORT_GP_CFG_8(bank, fn, sfx, cfg), \ 412 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) 413 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) 414 415 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \ 416 PORT_GP_CFG_9(bank, fn, sfx, cfg), \ 417 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) 418 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) 419 420 #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ 421 PORT_GP_CFG_10(bank, fn, sfx, cfg), \ 422 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) 423 #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) 424 425 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ 426 PORT_GP_CFG_11(bank, fn, sfx, cfg), \ 427 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) 428 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) 429 430 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ 431 PORT_GP_CFG_12(bank, fn, sfx, cfg), \ 432 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ 433 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) 434 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) 435 436 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ 437 PORT_GP_CFG_14(bank, fn, sfx, cfg), \ 438 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) 439 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) 440 441 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ 442 PORT_GP_CFG_15(bank, fn, sfx, cfg), \ 443 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) 444 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) 445 446 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ 447 PORT_GP_CFG_16(bank, fn, sfx, cfg), \ 448 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) 449 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) 450 451 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ 452 PORT_GP_CFG_17(bank, fn, sfx, cfg), \ 453 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) 454 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) 455 456 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ 457 PORT_GP_CFG_18(bank, fn, sfx, cfg), \ 458 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ 459 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) 460 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) 461 462 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \ 463 PORT_GP_CFG_20(bank, fn, sfx, cfg), \ 464 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) 465 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) 466 467 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \ 468 PORT_GP_CFG_21(bank, fn, sfx, cfg), \ 469 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) 470 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0) 471 472 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ 473 PORT_GP_CFG_22(bank, fn, sfx, cfg), \ 474 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) 475 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) 476 477 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ 478 PORT_GP_CFG_23(bank, fn, sfx, cfg), \ 479 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) 480 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) 481 482 #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \ 483 PORT_GP_CFG_24(bank, fn, sfx, cfg), \ 484 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg) 485 #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0) 486 487 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ 488 PORT_GP_CFG_25(bank, fn, sfx, cfg), \ 489 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) 490 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) 491 492 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ 493 PORT_GP_CFG_26(bank, fn, sfx, cfg), \ 494 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \ 495 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) 496 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) 497 498 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ 499 PORT_GP_CFG_28(bank, fn, sfx, cfg), \ 500 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) 501 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) 502 503 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ 504 PORT_GP_CFG_29(bank, fn, sfx, cfg), \ 505 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) 506 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) 507 508 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ 509 PORT_GP_CFG_30(bank, fn, sfx, cfg), \ 510 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \ 511 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) 512 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) 513 514 #define PORT_GP_32_REV(bank, fn, sfx) \ 515 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ 516 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ 517 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ 518 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ 519 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ 520 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ 521 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ 522 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ 523 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ 524 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ 525 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ 526 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ 527 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ 528 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ 529 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ 530 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) 531 532 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ 533 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx 534 #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) 535 536 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ 537 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ 538 { \ 539 .pin = (bank * 32) + _pin, \ 540 .name = __stringify(_name), \ 541 .enum_id = _name##_DATA, \ 542 .configs = cfg, \ 543 } 544 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) 545 546 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ 547 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) 548 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) 549 550 /* 551 * PORT style (linear pin space) 552 */ 553 554 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) 555 556 #define PORT_10(pn, fn, pfx, sfx) \ 557 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ 558 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ 559 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ 560 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ 561 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) 562 563 #define PORT_90(pn, fn, pfx, sfx) \ 564 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ 565 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ 566 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ 567 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ 568 PORT_10(pn+90, fn, pfx##9, sfx) 569 570 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ 571 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx 572 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 573 574 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ 575 #define PINMUX_GPIO(_pin) \ 576 [GPIO_##_pin] = { \ 577 .pin = (u16)-1, \ 578 .name = __stringify(GPIO_##_pin), \ 579 .enum_id = _pin##_DATA, \ 580 } 581 582 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ 583 #define SH_PFC_PIN_CFG(_pin, cfgs) \ 584 { \ 585 .pin = _pin, \ 586 .name = __stringify(PORT##_pin), \ 587 .enum_id = PORT##_pin##_DATA, \ 588 .configs = cfgs, \ 589 } 590 591 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ 592 #define SH_PFC_PIN_NAMED(row, col, _name) \ 593 { \ 594 .pin = PIN_NUMBER(row, col), \ 595 .name = __stringify(PIN_##_name), \ 596 .configs = SH_PFC_PIN_CFG_NO_GPIO, \ 597 } 598 599 /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */ 600 #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \ 601 { \ 602 .pin = PIN_NUMBER(row, col), \ 603 .name = __stringify(PIN_##_name), \ 604 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \ 605 } 606 607 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, 608 * PORT_name_OUT, PORT_name_IN marks 609 */ 610 #define _PORT_DATA(pn, pfx, sfx) \ 611 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ 612 PORT##pfx##_OUT, PORT##pfx##_IN) 613 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) 614 615 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ 616 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ 617 [gpio - (base)] = { \ 618 .name = __stringify(gpio), \ 619 .enum_id = data_or_mark, \ 620 } 621 #define GPIO_FN(str) \ 622 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) 623 624 /* 625 * PORTnCR helper macro for SH-Mobile/R-Mobile 626 */ 627 #define PORTCR(nr, reg) \ 628 { \ 629 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ 630 /* PULMD[1:0], handled by .set_bias() */ \ 631 0, 0, 0, 0, \ 632 /* IE and OE */ \ 633 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ 634 /* SEC, not supported */ \ 635 0, 0, \ 636 /* PTMD[2:0] */ \ 637 PORT##nr##_FN0, PORT##nr##_FN1, \ 638 PORT##nr##_FN2, PORT##nr##_FN3, \ 639 PORT##nr##_FN4, PORT##nr##_FN5, \ 640 PORT##nr##_FN6, PORT##nr##_FN7 \ 641 } \ 642 } 643 644 /* 645 * GPIO number helper macro for R-Car 646 */ 647 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) 648 649 #endif /* __SH_PFC_H */ 650
