1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_SH_CPU_SH5_CACHE_H 3 #define __ASM_SH_CPU_SH5_CACHE_H 4 5 /* 6 * include/asm-sh/cpu-sh5/cache.h 7 * 8 * Copyright (C) 2000, 2001 Paolo Alberelli 9 * Copyright (C) 2003, 2004 Paul Mundt 10 */ 11 12 #define L1_CACHE_SHIFT 5 13 14 /* Valid and Dirty bits */ 15 #define SH_CACHE_VALID (1LL<<0) 16 #define SH_CACHE_UPDATED (1LL<<57) 17 18 /* Unimplemented compat bits.. */ 19 #define SH_CACHE_COMBINED 0 20 #define SH_CACHE_ASSOC 0 21 22 /* Cache flags */ 23 #define SH_CACHE_MODE_WT (1LL<<0) 24 #define SH_CACHE_MODE_WB (1LL<<1) 25 26 /* 27 * Control Registers. 28 */ 29 #define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */ 30 #define ICCR_REG0 0 /* Register 0 offset */ 31 #define ICCR_REG1 1 /* Register 1 offset */ 32 #define ICCR0 ICCR_BASE+ICCR_REG0 33 #define ICCR1 ICCR_BASE+ICCR_REG1 34 35 #define ICCR0_OFF 0x0 /* Set ICACHE off */ 36 #define ICCR0_ON 0x1 /* Set ICACHE on */ 37 #define ICCR0_ICI 0x2 /* Invalidate all in IC */ 38 39 #define ICCR1_NOLOCK 0x0 /* Set No Locking */ 40 41 #define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */ 42 #define OCCR_REG0 0 /* Register 0 offset */ 43 #define OCCR_REG1 1 /* Register 1 offset */ 44 #define OCCR0 OCCR_BASE+OCCR_REG0 45 #define OCCR1 OCCR_BASE+OCCR_REG1 46 47 #define OCCR0_OFF 0x0 /* Set OCACHE off */ 48 #define OCCR0_ON 0x1 /* Set OCACHE on */ 49 #define OCCR0_OCI 0x2 /* Invalidate all in OC */ 50 #define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */ 51 #define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */ 52 53 #define OCCR1_NOLOCK 0x0 /* Set No Locking */ 54 55 /* 56 * SH-5 57 * A bit of description here, for neff=32. 58 * 59 * |<--- tag (19 bits) --->| 60 * +-----------------------------+-----------------+------+----------+------+ 61 * | | | ways |set index |offset| 62 * +-----------------------------+-----------------+------+----------+------+ 63 * ^ 2 bits 8 bits 5 bits 64 * +- Bit 31 65 * 66 * Cacheline size is based on offset: 5 bits = 32 bytes per line 67 * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG 68 * have a broader space for registers. These are outlined by 69 * CACHE_?C_*_STEP below. 70 * 71 */ 72 73 /* Instruction cache */ 74 #define CACHE_IC_ADDRESS_ARRAY 0x01000000 75 76 /* Operand Cache */ 77 #define CACHE_OC_ADDRESS_ARRAY 0x01800000 78 79 /* These declarations relate to cache 'synonyms' in the operand cache. A 80 'synonym' occurs where effective address bits overlap between those used for 81 indexing the cache sets and those passed to the MMU for translation. In the 82 case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */ 83 84 #define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */ 85 #define CACHE_OC_SYN_SHIFT 12 86 /* Mask to select synonym bit(s) */ 87 #define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT) 88 89 /* 90 * Instruction cache can't be invalidated based on physical addresses. 91 * No Instruction Cache defines required, then. 92 */ 93 94 #endif /* __ASM_SH_CPU_SH5_CACHE_H */ 95
