1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Driver for Realtek PCI-Express card reader 4 * 5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 * 7 * Author: 8 * Wei WANG (wei_wang@realsil.com.cn) 9 * Micky Ching (micky_ching@realsil.com.cn) 10 */ 11 12 #ifndef __REALTEK_RTSX_SD_H 13 #define __REALTEK_RTSX_SD_H 14 15 #include "rtsx_chip.h" 16 17 #define SUPPORT_VOLTAGE 0x003C0000 18 19 /* Error Code */ 20 #define SD_NO_ERROR 0x0 21 #define SD_CRC_ERR 0x80 22 #define SD_TO_ERR 0x40 23 #define SD_NO_CARD 0x20 24 #define SD_BUSY 0x10 25 #define SD_STS_ERR 0x08 26 #define SD_RSP_TIMEOUT 0x04 27 #define SD_IO_ERR 0x02 28 29 /* Return code for MMC switch bus */ 30 #define SWITCH_SUCCESS 0 31 #define SWITCH_ERR 1 32 #define SWITCH_FAIL 2 33 34 /* MMC/SD Command Index */ 35 /* Basic command (class 0) */ 36 #define GO_IDLE_STATE 0 37 #define SEND_OP_COND 1 38 #define ALL_SEND_CID 2 39 #define SET_RELATIVE_ADDR 3 40 #define SEND_RELATIVE_ADDR 3 41 #define SET_DSR 4 42 #define IO_SEND_OP_COND 5 43 #define SWITCH 6 44 #define SELECT_CARD 7 45 #define DESELECT_CARD 7 46 /* CMD8 is "SEND_EXT_CSD" for MMC4.x Spec 47 * while is "SEND_IF_COND" for SD 2.0 48 */ 49 #define SEND_EXT_CSD 8 50 #define SEND_IF_COND 8 51 52 #define SEND_CSD 9 53 #define SEND_CID 10 54 #define VOLTAGE_SWITCH 11 55 #define READ_DAT_UTIL_STOP 11 56 #define STOP_TRANSMISSION 12 57 #define SEND_STATUS 13 58 #define GO_INACTIVE_STATE 15 59 60 #define SET_BLOCKLEN 16 61 #define READ_SINGLE_BLOCK 17 62 #define READ_MULTIPLE_BLOCK 18 63 #define SEND_TUNING_PATTERN 19 64 65 #define BUSTEST_R 14 66 #define BUSTEST_W 19 67 68 #define WRITE_BLOCK 24 69 #define WRITE_MULTIPLE_BLOCK 25 70 #define PROGRAM_CSD 27 71 72 #define ERASE_WR_BLK_START 32 73 #define ERASE_WR_BLK_END 33 74 #define ERASE_CMD 38 75 76 #define LOCK_UNLOCK 42 77 #define IO_RW_DIRECT 52 78 79 #define APP_CMD 55 80 #define GEN_CMD 56 81 82 #define SET_BUS_WIDTH 6 83 #define SD_STATUS 13 84 #define SEND_NUM_WR_BLOCKS 22 85 #define SET_WR_BLK_ERASE_COUNT 23 86 #define SD_APP_OP_COND 41 87 #define SET_CLR_CARD_DETECT 42 88 #define SEND_SCR 51 89 90 #define SD_READ_COMPLETE 0x00 91 #define SD_READ_TO 0x01 92 #define SD_READ_ADVENCE 0x02 93 94 #define SD_CHECK_MODE 0x00 95 #define SD_SWITCH_MODE 0x80 96 #define SD_FUNC_GROUP_1 0x01 97 #define SD_FUNC_GROUP_2 0x02 98 #define SD_FUNC_GROUP_3 0x03 99 #define SD_FUNC_GROUP_4 0x04 100 #define SD_CHECK_SPEC_V1_1 0xFF 101 102 #define NO_ARGUMENT 0x00 103 #define CHECK_PATTERN 0x000000AA 104 #define VOLTAGE_SUPPLY_RANGE 0x00000100 105 #define SUPPORT_HIGH_AND_EXTENDED_CAPACITY 0x40000000 106 #define SUPPORT_MAX_POWER_PERMANCE 0x10000000 107 #define SUPPORT_1V8 0x01000000 108 109 #define SWITCH_NO_ERR 0x00 110 #define CARD_NOT_EXIST 0x01 111 #define SPEC_NOT_SUPPORT 0x02 112 #define CHECK_MODE_ERR 0x03 113 #define CHECK_NOT_READY 0x04 114 #define SWITCH_CRC_ERR 0x05 115 #define SWITCH_MODE_ERR 0x06 116 #define SWITCH_PASS 0x07 117 118 #ifdef SUPPORT_SD_LOCK 119 #define SD_ERASE 0x08 120 #define SD_LOCK 0x04 121 #define SD_UNLOCK 0x00 122 #define SD_CLR_PWD 0x02 123 #define SD_SET_PWD 0x01 124 125 #define SD_PWD_LEN 0x10 126 127 #define SD_LOCKED 0x80 128 #define SD_LOCK_1BIT_MODE 0x40 129 #define SD_PWD_EXIST 0x20 130 #define SD_UNLOCK_POW_ON 0x01 131 #define SD_SDR_RST 0x02 132 133 #define SD_NOT_ERASE 0x00 134 #define SD_UNDER_ERASING 0x01 135 #define SD_COMPLETE_ERASE 0x02 136 137 #define SD_RW_FORBIDDEN 0x0F 138 139 #endif 140 141 #define HS_SUPPORT 0x01 142 #define SDR50_SUPPORT 0x02 143 #define SDR104_SUPPORT 0x03 144 #define DDR50_SUPPORT 0x04 145 146 #define HS_SUPPORT_MASK 0x02 147 #define SDR50_SUPPORT_MASK 0x04 148 #define SDR104_SUPPORT_MASK 0x08 149 #define DDR50_SUPPORT_MASK 0x10 150 151 #define HS_QUERY_SWITCH_OK 0x01 152 #define SDR50_QUERY_SWITCH_OK 0x02 153 #define SDR104_QUERY_SWITCH_OK 0x03 154 #define DDR50_QUERY_SWITCH_OK 0x04 155 156 #define HS_SWITCH_BUSY 0x02 157 #define SDR50_SWITCH_BUSY 0x04 158 #define SDR104_SWITCH_BUSY 0x08 159 #define DDR50_SWITCH_BUSY 0x10 160 161 #define FUNCTION_GROUP1_SUPPORT_OFFSET 0x0D 162 #define FUNCTION_GROUP1_QUERY_SWITCH_OFFSET 0x10 163 #define FUNCTION_GROUP1_CHECK_BUSY_OFFSET 0x1D 164 165 #define DRIVING_TYPE_A 0x01 166 #define DRIVING_TYPE_B 0x00 167 #define DRIVING_TYPE_C 0x02 168 #define DRIVING_TYPE_D 0x03 169 170 #define DRIVING_TYPE_A_MASK 0x02 171 #define DRIVING_TYPE_B_MASK 0x01 172 #define DRIVING_TYPE_C_MASK 0x04 173 #define DRIVING_TYPE_D_MASK 0x08 174 175 #define TYPE_A_QUERY_SWITCH_OK 0x01 176 #define TYPE_B_QUERY_SWITCH_OK 0x00 177 #define TYPE_C_QUERY_SWITCH_OK 0x02 178 #define TYPE_D_QUERY_SWITCH_OK 0x03 179 180 #define TYPE_A_SWITCH_BUSY 0x02 181 #define TYPE_B_SWITCH_BUSY 0x01 182 #define TYPE_C_SWITCH_BUSY 0x04 183 #define TYPE_D_SWITCH_BUSY 0x08 184 185 #define FUNCTION_GROUP3_SUPPORT_OFFSET 0x09 186 #define FUNCTION_GROUP3_QUERY_SWITCH_OFFSET 0x0F 187 #define FUNCTION_GROUP3_CHECK_BUSY_OFFSET 0x19 188 189 #define CURRENT_LIMIT_200 0x00 190 #define CURRENT_LIMIT_400 0x01 191 #define CURRENT_LIMIT_600 0x02 192 #define CURRENT_LIMIT_800 0x03 193 194 #define CURRENT_LIMIT_200_MASK 0x01 195 #define CURRENT_LIMIT_400_MASK 0x02 196 #define CURRENT_LIMIT_600_MASK 0x04 197 #define CURRENT_LIMIT_800_MASK 0x08 198 199 #define CURRENT_LIMIT_200_QUERY_SWITCH_OK 0x00 200 #define CURRENT_LIMIT_400_QUERY_SWITCH_OK 0x01 201 #define CURRENT_LIMIT_600_QUERY_SWITCH_OK 0x02 202 #define CURRENT_LIMIT_800_QUERY_SWITCH_OK 0x03 203 204 #define CURRENT_LIMIT_200_SWITCH_BUSY 0x01 205 #define CURRENT_LIMIT_400_SWITCH_BUSY 0x02 206 #define CURRENT_LIMIT_600_SWITCH_BUSY 0x04 207 #define CURRENT_LIMIT_800_SWITCH_BUSY 0x08 208 209 #define FUNCTION_GROUP4_SUPPORT_OFFSET 0x07 210 #define FUNCTION_GROUP4_QUERY_SWITCH_OFFSET 0x0F 211 #define FUNCTION_GROUP4_CHECK_BUSY_OFFSET 0x17 212 213 #define DATA_STRUCTURE_VER_OFFSET 0x11 214 215 #define MAX_PHASE 31 216 217 #define MMC_8BIT_BUS 0x0010 218 #define MMC_4BIT_BUS 0x0020 219 220 #define MMC_SWITCH_ERR 0x80 221 222 #define SD_IO_3V3 0 223 #define SD_IO_1V8 1 224 225 #define TUNE_TX 0x00 226 #define TUNE_RX 0x01 227 228 #define CHANGE_TX 0x00 229 #define CHANGE_RX 0x01 230 231 #define DCM_HIGH_FREQUENCY_MODE 0x00 232 #define DCM_LOW_FREQUENCY_MODE 0x01 233 234 #define DCM_HIGH_FREQUENCY_MODE_SET 0x0C 235 #define DCM_Low_FREQUENCY_MODE_SET 0x00 236 237 #define MULTIPLY_BY_1 0x00 238 #define MULTIPLY_BY_2 0x01 239 #define MULTIPLY_BY_3 0x02 240 #define MULTIPLY_BY_4 0x03 241 #define MULTIPLY_BY_5 0x04 242 #define MULTIPLY_BY_6 0x05 243 #define MULTIPLY_BY_7 0x06 244 #define MULTIPLY_BY_8 0x07 245 #define MULTIPLY_BY_9 0x08 246 #define MULTIPLY_BY_10 0x09 247 248 #define DIVIDE_BY_2 0x01 249 #define DIVIDE_BY_3 0x02 250 #define DIVIDE_BY_4 0x03 251 #define DIVIDE_BY_5 0x04 252 #define DIVIDE_BY_6 0x05 253 #define DIVIDE_BY_7 0x06 254 #define DIVIDE_BY_8 0x07 255 #define DIVIDE_BY_9 0x08 256 #define DIVIDE_BY_10 0x09 257 258 struct timing_phase_path { 259 int start; 260 int end; 261 int mid; 262 int len; 263 }; 264 265 int sd_select_card(struct rtsx_chip *chip, int select); 266 int sd_pull_ctl_enable(struct rtsx_chip *chip); 267 int reset_sd_card(struct rtsx_chip *chip); 268 int sd_switch_clock(struct rtsx_chip *chip); 269 void sd_stop_seq_mode(struct rtsx_chip *chip); 270 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 271 u32 start_sector, u16 sector_cnt); 272 void sd_cleanup_work(struct rtsx_chip *chip); 273 int sd_power_off_card3v3(struct rtsx_chip *chip); 274 int release_sd_card(struct rtsx_chip *chip); 275 #ifdef SUPPORT_CPRM 276 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, 277 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, 278 bool special_check); 279 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type); 280 281 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip); 282 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 283 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 284 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 285 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip); 286 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip); 287 #endif 288 289 #endif /* __REALTEK_RTSX_SD_H */ 290
