1 /* irq.h
2  *
3  * Copyright (c) 2012 Samsung Electronics Co., Ltd
4  *              http://www.samsung.com
5  *
6  *  This program is free software; you can redistribute  it and/or modify it
7  *  under  the terms of  the GNU General  Public License as published by the
8  *  Free Software Foundation;  either version 2 of the  License, or (at your
9  *  option) any later version.
10  *
11  */
12 
13 #ifndef __LINUX_MFD_SEC_IRQ_H
14 #define __LINUX_MFD_SEC_IRQ_H
15 
16 enum s2mpa01_irq {
17 	S2MPA01_IRQ_PWRONF,
18 	S2MPA01_IRQ_PWRONR,
19 	S2MPA01_IRQ_JIGONBF,
20 	S2MPA01_IRQ_JIGONBR,
21 	S2MPA01_IRQ_ACOKBF,
22 	S2MPA01_IRQ_ACOKBR,
23 	S2MPA01_IRQ_PWRON1S,
24 	S2MPA01_IRQ_MRB,
25 
26 	S2MPA01_IRQ_RTC60S,
27 	S2MPA01_IRQ_RTCA1,
28 	S2MPA01_IRQ_RTCA0,
29 	S2MPA01_IRQ_SMPL,
30 	S2MPA01_IRQ_RTC1S,
31 	S2MPA01_IRQ_WTSR,
32 
33 	S2MPA01_IRQ_INT120C,
34 	S2MPA01_IRQ_INT140C,
35 	S2MPA01_IRQ_LDO3_TSD,
36 	S2MPA01_IRQ_B16_TSD,
37 	S2MPA01_IRQ_B24_TSD,
38 	S2MPA01_IRQ_B35_TSD,
39 
40 	S2MPA01_IRQ_NR,
41 };
42 
43 #define S2MPA01_IRQ_PWRONF_MASK		(1 << 0)
44 #define S2MPA01_IRQ_PWRONR_MASK		(1 << 1)
45 #define S2MPA01_IRQ_JIGONBF_MASK	(1 << 2)
46 #define S2MPA01_IRQ_JIGONBR_MASK	(1 << 3)
47 #define S2MPA01_IRQ_ACOKBF_MASK		(1 << 4)
48 #define S2MPA01_IRQ_ACOKBR_MASK		(1 << 5)
49 #define S2MPA01_IRQ_PWRON1S_MASK	(1 << 6)
50 #define S2MPA01_IRQ_MRB_MASK		(1 << 7)
51 
52 #define S2MPA01_IRQ_RTC60S_MASK		(1 << 0)
53 #define S2MPA01_IRQ_RTCA1_MASK		(1 << 1)
54 #define S2MPA01_IRQ_RTCA0_MASK		(1 << 2)
55 #define S2MPA01_IRQ_SMPL_MASK		(1 << 3)
56 #define S2MPA01_IRQ_RTC1S_MASK		(1 << 4)
57 #define S2MPA01_IRQ_WTSR_MASK		(1 << 5)
58 
59 #define S2MPA01_IRQ_INT120C_MASK	(1 << 0)
60 #define S2MPA01_IRQ_INT140C_MASK	(1 << 1)
61 #define S2MPA01_IRQ_LDO3_TSD_MASK	(1 << 2)
62 #define S2MPA01_IRQ_B16_TSD_MASK	(1 << 3)
63 #define S2MPA01_IRQ_B24_TSD_MASK	(1 << 4)
64 #define S2MPA01_IRQ_B35_TSD_MASK	(1 << 5)
65 
66 enum s2mps11_irq {
67 	S2MPS11_IRQ_PWRONF,
68 	S2MPS11_IRQ_PWRONR,
69 	S2MPS11_IRQ_JIGONBF,
70 	S2MPS11_IRQ_JIGONBR,
71 	S2MPS11_IRQ_ACOKBF,
72 	S2MPS11_IRQ_ACOKBR,
73 	S2MPS11_IRQ_PWRON1S,
74 	S2MPS11_IRQ_MRB,
75 
76 	S2MPS11_IRQ_RTC60S,
77 	S2MPS11_IRQ_RTCA1,
78 	S2MPS11_IRQ_RTCA0,
79 	S2MPS11_IRQ_SMPL,
80 	S2MPS11_IRQ_RTC1S,
81 	S2MPS11_IRQ_WTSR,
82 
83 	S2MPS11_IRQ_INT120C,
84 	S2MPS11_IRQ_INT140C,
85 
86 	S2MPS11_IRQ_NR,
87 };
88 
89 #define S2MPS11_IRQ_PWRONF_MASK		(1 << 0)
90 #define S2MPS11_IRQ_PWRONR_MASK		(1 << 1)
91 #define S2MPS11_IRQ_JIGONBF_MASK	(1 << 2)
92 #define S2MPS11_IRQ_JIGONBR_MASK	(1 << 3)
93 #define S2MPS11_IRQ_ACOKBF_MASK		(1 << 4)
94 #define S2MPS11_IRQ_ACOKBR_MASK		(1 << 5)
95 #define S2MPS11_IRQ_PWRON1S_MASK	(1 << 6)
96 #define S2MPS11_IRQ_MRB_MASK		(1 << 7)
97 
98 #define S2MPS11_IRQ_RTC60S_MASK		(1 << 0)
99 #define S2MPS11_IRQ_RTCA1_MASK		(1 << 1)
100 #define S2MPS11_IRQ_RTCA0_MASK		(1 << 2)
101 #define S2MPS11_IRQ_SMPL_MASK		(1 << 3)
102 #define S2MPS11_IRQ_RTC1S_MASK		(1 << 4)
103 #define S2MPS11_IRQ_WTSR_MASK		(1 << 5)
104 
105 #define S2MPS11_IRQ_INT120C_MASK	(1 << 0)
106 #define S2MPS11_IRQ_INT140C_MASK	(1 << 1)
107 
108 enum s2mps14_irq {
109 	S2MPS14_IRQ_PWRONF,
110 	S2MPS14_IRQ_PWRONR,
111 	S2MPS14_IRQ_JIGONBF,
112 	S2MPS14_IRQ_JIGONBR,
113 	S2MPS14_IRQ_ACOKBF,
114 	S2MPS14_IRQ_ACOKBR,
115 	S2MPS14_IRQ_PWRON1S,
116 	S2MPS14_IRQ_MRB,
117 
118 	S2MPS14_IRQ_RTC60S,
119 	S2MPS14_IRQ_RTCA1,
120 	S2MPS14_IRQ_RTCA0,
121 	S2MPS14_IRQ_SMPL,
122 	S2MPS14_IRQ_RTC1S,
123 	S2MPS14_IRQ_WTSR,
124 
125 	S2MPS14_IRQ_INT120C,
126 	S2MPS14_IRQ_INT140C,
127 	S2MPS14_IRQ_TSD,
128 
129 	S2MPS14_IRQ_NR,
130 };
131 
132 enum s2mpu02_irq {
133 	S2MPU02_IRQ_PWRONF,
134 	S2MPU02_IRQ_PWRONR,
135 	S2MPU02_IRQ_JIGONBF,
136 	S2MPU02_IRQ_JIGONBR,
137 	S2MPU02_IRQ_ACOKBF,
138 	S2MPU02_IRQ_ACOKBR,
139 	S2MPU02_IRQ_PWRON1S,
140 	S2MPU02_IRQ_MRB,
141 
142 	S2MPU02_IRQ_RTC60S,
143 	S2MPU02_IRQ_RTCA1,
144 	S2MPU02_IRQ_RTCA0,
145 	S2MPU02_IRQ_SMPL,
146 	S2MPU02_IRQ_RTC1S,
147 	S2MPU02_IRQ_WTSR,
148 
149 	S2MPU02_IRQ_INT120C,
150 	S2MPU02_IRQ_INT140C,
151 	S2MPU02_IRQ_TSD,
152 
153 	S2MPU02_IRQ_NR,
154 };
155 
156 /* Masks for interrupts are the same as in s2mps11 */
157 #define S2MPS14_IRQ_TSD_MASK		(1 << 2)
158 
159 enum s5m8767_irq {
160 	S5M8767_IRQ_PWRR,
161 	S5M8767_IRQ_PWRF,
162 	S5M8767_IRQ_PWR1S,
163 	S5M8767_IRQ_JIGR,
164 	S5M8767_IRQ_JIGF,
165 	S5M8767_IRQ_LOWBAT2,
166 	S5M8767_IRQ_LOWBAT1,
167 
168 	S5M8767_IRQ_MRB,
169 	S5M8767_IRQ_DVSOK2,
170 	S5M8767_IRQ_DVSOK3,
171 	S5M8767_IRQ_DVSOK4,
172 
173 	S5M8767_IRQ_RTC60S,
174 	S5M8767_IRQ_RTCA1,
175 	S5M8767_IRQ_RTCA2,
176 	S5M8767_IRQ_SMPL,
177 	S5M8767_IRQ_RTC1S,
178 	S5M8767_IRQ_WTSR,
179 
180 	S5M8767_IRQ_NR,
181 };
182 
183 #define S5M8767_IRQ_PWRR_MASK		(1 << 0)
184 #define S5M8767_IRQ_PWRF_MASK		(1 << 1)
185 #define S5M8767_IRQ_PWR1S_MASK		(1 << 3)
186 #define S5M8767_IRQ_JIGR_MASK		(1 << 4)
187 #define S5M8767_IRQ_JIGF_MASK		(1 << 5)
188 #define S5M8767_IRQ_LOWBAT2_MASK	(1 << 6)
189 #define S5M8767_IRQ_LOWBAT1_MASK	(1 << 7)
190 
191 #define S5M8767_IRQ_MRB_MASK		(1 << 2)
192 #define S5M8767_IRQ_DVSOK2_MASK		(1 << 3)
193 #define S5M8767_IRQ_DVSOK3_MASK		(1 << 4)
194 #define S5M8767_IRQ_DVSOK4_MASK		(1 << 5)
195 
196 #define S5M8767_IRQ_RTC60S_MASK		(1 << 0)
197 #define S5M8767_IRQ_RTCA1_MASK		(1 << 1)
198 #define S5M8767_IRQ_RTCA2_MASK		(1 << 2)
199 #define S5M8767_IRQ_SMPL_MASK		(1 << 3)
200 #define S5M8767_IRQ_RTC1S_MASK		(1 << 4)
201 #define S5M8767_IRQ_WTSR_MASK		(1 << 5)
202 
203 enum s5m8763_irq {
204 	S5M8763_IRQ_DCINF,
205 	S5M8763_IRQ_DCINR,
206 	S5M8763_IRQ_JIGF,
207 	S5M8763_IRQ_JIGR,
208 	S5M8763_IRQ_PWRONF,
209 	S5M8763_IRQ_PWRONR,
210 
211 	S5M8763_IRQ_WTSREVNT,
212 	S5M8763_IRQ_SMPLEVNT,
213 	S5M8763_IRQ_ALARM1,
214 	S5M8763_IRQ_ALARM0,
215 
216 	S5M8763_IRQ_ONKEY1S,
217 	S5M8763_IRQ_TOPOFFR,
218 	S5M8763_IRQ_DCINOVPR,
219 	S5M8763_IRQ_CHGRSTF,
220 	S5M8763_IRQ_DONER,
221 	S5M8763_IRQ_CHGFAULT,
222 
223 	S5M8763_IRQ_LOBAT1,
224 	S5M8763_IRQ_LOBAT2,
225 
226 	S5M8763_IRQ_NR,
227 };
228 
229 #define S5M8763_IRQ_DCINF_MASK		(1 << 2)
230 #define S5M8763_IRQ_DCINR_MASK		(1 << 3)
231 #define S5M8763_IRQ_JIGF_MASK		(1 << 4)
232 #define S5M8763_IRQ_JIGR_MASK		(1 << 5)
233 #define S5M8763_IRQ_PWRONF_MASK		(1 << 6)
234 #define S5M8763_IRQ_PWRONR_MASK		(1 << 7)
235 
236 #define S5M8763_IRQ_WTSREVNT_MASK	(1 << 0)
237 #define S5M8763_IRQ_SMPLEVNT_MASK	(1 << 1)
238 #define S5M8763_IRQ_ALARM1_MASK		(1 << 2)
239 #define S5M8763_IRQ_ALARM0_MASK		(1 << 3)
240 
241 #define S5M8763_IRQ_ONKEY1S_MASK	(1 << 0)
242 #define S5M8763_IRQ_TOPOFFR_MASK	(1 << 2)
243 #define S5M8763_IRQ_DCINOVPR_MASK	(1 << 3)
244 #define S5M8763_IRQ_CHGRSTF_MASK	(1 << 4)
245 #define S5M8763_IRQ_DONER_MASK		(1 << 5)
246 #define S5M8763_IRQ_CHGFAULT_MASK	(1 << 7)
247 
248 #define S5M8763_IRQ_LOBAT1_MASK		(1 << 0)
249 #define S5M8763_IRQ_LOBAT2_MASK		(1 << 1)
250 
251 #define S5M8763_ENRAMP                  (1 << 4)
252 
253 #endif /*  __LINUX_MFD_SEC_IRQ_H */
254