1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * 6 * S3C2410 Memory Control register definitions 7 */ 8 9 #ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H 10 #define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__ 11 12 #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) 13 14 #define S3C2410_BWSCON S3C2410_MEMREG(0x00) 15 #define S3C2410_BANKCON0 S3C2410_MEMREG(0x04) 16 #define S3C2410_BANKCON1 S3C2410_MEMREG(0x08) 17 #define S3C2410_BANKCON2 S3C2410_MEMREG(0x0C) 18 #define S3C2410_BANKCON3 S3C2410_MEMREG(0x10) 19 #define S3C2410_BANKCON4 S3C2410_MEMREG(0x14) 20 #define S3C2410_BANKCON5 S3C2410_MEMREG(0x18) 21 #define S3C2410_BANKCON6 S3C2410_MEMREG(0x1C) 22 #define S3C2410_BANKCON7 S3C2410_MEMREG(0x20) 23 #define S3C2410_REFRESH S3C2410_MEMREG(0x24) 24 #define S3C2410_BANKSIZE S3C2410_MEMREG(0x28) 25 26 #define S3C2410_BWSCON_ST1 (1 << 7) 27 #define S3C2410_BWSCON_ST2 (1 << 11) 28 #define S3C2410_BWSCON_ST3 (1 << 15) 29 #define S3C2410_BWSCON_ST4 (1 << 19) 30 #define S3C2410_BWSCON_ST5 (1 << 23) 31 32 #define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) 33 34 #define S3C2410_BWSCON_WS (1 << 2) 35 36 #define S3C2410_BANKCON_PMC16 (0x3) 37 38 #define S3C2410_BANKCON_Tacp_SHIFT (2) 39 #define S3C2410_BANKCON_Tcah_SHIFT (4) 40 #define S3C2410_BANKCON_Tcoh_SHIFT (6) 41 #define S3C2410_BANKCON_Tacc_SHIFT (8) 42 #define S3C2410_BANKCON_Tcos_SHIFT (11) 43 #define S3C2410_BANKCON_Tacs_SHIFT (13) 44 45 #define S3C2410_BANKCON_SDRAM (0x3 << 15) 46 47 #define S3C2410_REFRESH_SELF (1 << 22) 48 49 #define S3C2410_BANKSIZE_MASK (0x7 << 0) 50 51 #endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */ 52
