1 /*
2 * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
3 * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #ifndef RXE_PARAM_H
35 #define RXE_PARAM_H
36
rxe_mtu_int_to_enum(int mtu)37 static inline enum ib_mtu rxe_mtu_int_to_enum(int mtu)
38 {
39 if (mtu < 256)
40 return 0;
41 else if (mtu < 512)
42 return IB_MTU_256;
43 else if (mtu < 1024)
44 return IB_MTU_512;
45 else if (mtu < 2048)
46 return IB_MTU_1024;
47 else if (mtu < 4096)
48 return IB_MTU_2048;
49 else
50 return IB_MTU_4096;
51 }
52
53 /* Find the IB mtu for a given network MTU. */
eth_mtu_int_to_enum(int mtu)54 static inline enum ib_mtu eth_mtu_int_to_enum(int mtu)
55 {
56 mtu -= RXE_MAX_HDR_LENGTH;
57
58 return rxe_mtu_int_to_enum(mtu);
59 }
60
61 /* default/initial rxe device parameter settings */
62 enum rxe_device_param {
63 RXE_FW_VER = 0,
64 RXE_MAX_MR_SIZE = -1ull,
65 RXE_PAGE_SIZE_CAP = 0xfffff000,
66 RXE_VENDOR_ID = 0,
67 RXE_VENDOR_PART_ID = 0,
68 RXE_HW_VER = 0,
69 RXE_MAX_QP = 0x10000,
70 RXE_MAX_QP_WR = 0x4000,
71 RXE_MAX_INLINE_DATA = 400,
72 RXE_DEVICE_CAP_FLAGS = IB_DEVICE_BAD_PKEY_CNTR
73 | IB_DEVICE_BAD_QKEY_CNTR
74 | IB_DEVICE_AUTO_PATH_MIG
75 | IB_DEVICE_CHANGE_PHY_PORT
76 | IB_DEVICE_UD_AV_PORT_ENFORCE
77 | IB_DEVICE_PORT_ACTIVE_EVENT
78 | IB_DEVICE_SYS_IMAGE_GUID
79 | IB_DEVICE_RC_RNR_NAK_GEN
80 | IB_DEVICE_SRQ_RESIZE
81 | IB_DEVICE_MEM_MGT_EXTENSIONS,
82 RXE_MAX_SGE = 32,
83 RXE_MAX_SGE_RD = 32,
84 RXE_MAX_CQ = 16384,
85 RXE_MAX_LOG_CQE = 15,
86 RXE_MAX_MR = 256 * 1024,
87 RXE_MAX_PD = 0x7ffc,
88 RXE_MAX_QP_RD_ATOM = 128,
89 RXE_MAX_EE_RD_ATOM = 0,
90 RXE_MAX_RES_RD_ATOM = 0x3f000,
91 RXE_MAX_QP_INIT_RD_ATOM = 128,
92 RXE_MAX_EE_INIT_RD_ATOM = 0,
93 RXE_ATOMIC_CAP = 1,
94 RXE_MAX_EE = 0,
95 RXE_MAX_RDD = 0,
96 RXE_MAX_MW = 0,
97 RXE_MAX_RAW_IPV6_QP = 0,
98 RXE_MAX_RAW_ETHY_QP = 0,
99 RXE_MAX_MCAST_GRP = 8192,
100 RXE_MAX_MCAST_QP_ATTACH = 56,
101 RXE_MAX_TOT_MCAST_QP_ATTACH = 0x70000,
102 RXE_MAX_AH = 100,
103 RXE_MAX_FMR = 0,
104 RXE_MAX_MAP_PER_FMR = 0,
105 RXE_MAX_SRQ = 960,
106 RXE_MAX_SRQ_WR = 0x4000,
107 RXE_MIN_SRQ_WR = 1,
108 RXE_MAX_SRQ_SGE = 27,
109 RXE_MIN_SRQ_SGE = 1,
110 RXE_MAX_FMR_PAGE_LIST_LEN = 512,
111 RXE_MAX_PKEYS = 64,
112 RXE_LOCAL_CA_ACK_DELAY = 15,
113
114 RXE_MAX_UCONTEXT = 512,
115
116 RXE_NUM_PORT = 1,
117
118 RXE_MIN_QP_INDEX = 16,
119 RXE_MAX_QP_INDEX = 0x00020000,
120
121 RXE_MIN_SRQ_INDEX = 0x00020001,
122 RXE_MAX_SRQ_INDEX = 0x00040000,
123
124 RXE_MIN_MR_INDEX = 0x00000001,
125 RXE_MAX_MR_INDEX = 0x00040000,
126 RXE_MIN_MW_INDEX = 0x00040001,
127 RXE_MAX_MW_INDEX = 0x00060000,
128 RXE_MAX_PKT_PER_ACK = 64,
129
130 RXE_MAX_UNACKED_PSNS = 128,
131
132 /* Max inflight SKBs per queue pair */
133 RXE_INFLIGHT_SKBS_PER_QP_HIGH = 64,
134 RXE_INFLIGHT_SKBS_PER_QP_LOW = 16,
135
136 /* Delay before calling arbiter timer */
137 RXE_NSEC_ARB_TIMER_DELAY = 200,
138 };
139
140 /* default/initial rxe port parameters */
141 enum rxe_port_param {
142 RXE_PORT_STATE = IB_PORT_DOWN,
143 RXE_PORT_MAX_MTU = IB_MTU_4096,
144 RXE_PORT_ACTIVE_MTU = IB_MTU_256,
145 RXE_PORT_GID_TBL_LEN = 1024,
146 RXE_PORT_PORT_CAP_FLAGS = RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP,
147 RXE_PORT_MAX_MSG_SZ = 0x800000,
148 RXE_PORT_BAD_PKEY_CNTR = 0,
149 RXE_PORT_QKEY_VIOL_CNTR = 0,
150 RXE_PORT_LID = 0,
151 RXE_PORT_SM_LID = 0,
152 RXE_PORT_SM_SL = 0,
153 RXE_PORT_LMC = 0,
154 RXE_PORT_MAX_VL_NUM = 1,
155 RXE_PORT_SUBNET_TIMEOUT = 0,
156 RXE_PORT_INIT_TYPE_REPLY = 0,
157 RXE_PORT_ACTIVE_WIDTH = IB_WIDTH_1X,
158 RXE_PORT_ACTIVE_SPEED = 1,
159 RXE_PORT_PKEY_TBL_LEN = 64,
160 RXE_PORT_PHYS_STATE = 2,
161 RXE_PORT_SUBNET_PREFIX = 0xfe80000000000000ULL,
162 };
163
164 /* default/initial port info parameters */
165 enum rxe_port_info_param {
166 RXE_PORT_INFO_VL_CAP = 4, /* 1-8 */
167 RXE_PORT_INFO_MTU_CAP = 5, /* 4096 */
168 RXE_PORT_INFO_OPER_VL = 1, /* 1 */
169 };
170
171 #endif /* RXE_PARAM_H */
172
