1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #ifndef __HAL_DATA_H__ 8 #define __HAL_DATA_H__ 9 10 #include "odm_precomp.h" 11 #include <hal_btcoex.h> 12 13 #include <hal_sdio.h> 14 15 /* */ 16 /* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */ 17 /* */ 18 enum RT_MULTI_FUNC { 19 RT_MULTI_FUNC_NONE = 0x00, 20 RT_MULTI_FUNC_WIFI = 0x01, 21 RT_MULTI_FUNC_BT = 0x02, 22 RT_MULTI_FUNC_GPS = 0x04, 23 }; 24 /* */ 25 /* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */ 26 /* */ 27 enum RT_POLARITY_CTL { 28 RT_POLARITY_LOW_ACT = 0, 29 RT_POLARITY_HIGH_ACT = 1, 30 }; 31 32 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ 33 enum RT_REGULATOR_MODE { 34 RT_SWITCHING_REGULATOR = 0, 35 RT_LDO_REGULATOR = 1, 36 }; 37 38 enum RT_AMPDU_BURST { 39 RT_AMPDU_BURST_NONE = 0, 40 RT_AMPDU_BURST_92D = 1, 41 RT_AMPDU_BURST_88E = 2, 42 RT_AMPDU_BURST_8812_4 = 3, 43 RT_AMPDU_BURST_8812_8 = 4, 44 RT_AMPDU_BURST_8812_12 = 5, 45 RT_AMPDU_BURST_8812_15 = 6, 46 RT_AMPDU_BURST_8723B = 7, 47 }; 48 49 #define CHANNEL_MAX_NUMBER 14+24+21 /* 14 is the max channel number */ 50 #define CHANNEL_MAX_NUMBER_2G 14 51 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A" */ 52 #define CHANNEL_MAX_NUMBER_5G_80M 7 53 #define CHANNEL_GROUP_MAX 3+9 /* ch1~3, ch4~9, ch10~14 total three groups */ 54 #define MAX_PG_GROUP 13 55 56 /* Tx Power Limit Table Size */ 57 #define MAX_REGULATION_NUM 4 58 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 59 #define MAX_2_4G_BANDWIDTH_NUM 4 60 #define MAX_RATE_SECTION_NUM 10 61 #define MAX_5G_BANDWIDTH_NUM 4 62 63 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ 64 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ 65 66 67 /* duplicate code, will move to ODM ######### */ 68 /* define IQK_MAC_REG_NUM 4 */ 69 /* define IQK_ADDA_REG_NUM 16 */ 70 71 /* define IQK_BB_REG_NUM 10 */ 72 #define IQK_BB_REG_NUM_92C 9 73 #define IQK_BB_REG_NUM_92D 10 74 #define IQK_BB_REG_NUM_test 6 75 76 #define IQK_Matrix_Settings_NUM_92D 1+24+21 77 78 /* define HP_THERMAL_NUM 8 */ 79 /* duplicate code, will move to ODM ######### */ 80 81 enum { 82 SINGLEMAC_SINGLEPHY, /* SMSP */ 83 DUALMAC_DUALPHY, /* DMDP */ 84 DUALMAC_SINGLEPHY, /* DMSP */ 85 }; 86 87 #define PAGE_SIZE_128 128 88 #define PAGE_SIZE_256 256 89 #define PAGE_SIZE_512 512 90 91 struct dm_priv { 92 u8 DM_Type; 93 94 #define DYNAMIC_FUNC_BT BIT0 95 96 u8 DMFlag; 97 u8 InitDMFlag; 98 /* u8 RSVD_1; */ 99 100 u32 InitODMFlag; 101 /* Upper and Lower Signal threshold for Rate Adaptive */ 102 int UndecoratedSmoothedPWDB; 103 int UndecoratedSmoothedCCK; 104 int EntryMinUndecoratedSmoothedPWDB; 105 int EntryMaxUndecoratedSmoothedPWDB; 106 int MinUndecoratedPWDBForDM; 107 int LastMinUndecoratedPWDBForDM; 108 109 s32 UndecoratedSmoothedBeacon; 110 111 /* duplicate code, will move to ODM ######### */ 112 /* for High Power */ 113 u8 bDynamicTxPowerEnable; 114 u8 LastDTPLvl; 115 u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */ 116 117 /* for tx power tracking */ 118 u8 bTXPowerTracking; 119 u8 TXPowercount; 120 u8 bTXPowerTrackingInit; 121 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 122 u8 TM_Trigger; 123 124 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 125 u8 ThermalValue; 126 u8 ThermalValue_LCK; 127 u8 ThermalValue_IQK; 128 u8 ThermalValue_DPK; 129 u8 bRfPiEnable; 130 /* u8 RSVD_2; */ 131 132 /* for APK */ 133 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 134 u8 bAPKdone; 135 u8 bAPKThermalMeterIgnore; 136 u8 bDPdone; 137 u8 bDPPathAOK; 138 u8 bDPPathBOK; 139 /* u8 RSVD_3; */ 140 /* u8 RSVD_4; */ 141 /* u8 RSVD_5; */ 142 143 /* for IQK */ 144 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 145 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 146 u32 IQK_BB_backup_recover[9]; 147 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 148 149 u8 PowerIndex_backup[6]; 150 u8 OFDM_index[2]; 151 152 u8 bCCKinCH14; 153 u8 CCK_index; 154 u8 bDoneTxpower; 155 u8 CCK_index_HP; 156 157 u8 OFDM_index_HP[2]; 158 u8 ThermalValue_HP[HP_THERMAL_NUM]; 159 u8 ThermalValue_HP_index; 160 /* u8 RSVD_6; */ 161 162 /* for TxPwrTracking2 */ 163 s32 RegE94; 164 s32 RegE9C; 165 s32 RegEB4; 166 s32 RegEBC; 167 168 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 169 170 u32 prv_traffic_idx; /* edca turbo */ 171 /* duplicate code, will move to ODM ######### */ 172 173 /* Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas */ 174 u8 INIDATA_RATE[32]; 175 }; 176 177 178 struct hal_com_data { 179 HAL_VERSION VersionID; 180 enum RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ 181 enum RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ 182 enum RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ 183 184 u16 FirmwareVersion; 185 u16 FirmwareVersionRev; 186 u16 FirmwareSubVersion; 187 u16 FirmwareSignature; 188 189 /* current WIFI_PHY values */ 190 enum WIRELESS_MODE CurrentWirelessMode; 191 enum CHANNEL_WIDTH CurrentChannelBW; 192 enum BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */ 193 enum BAND_TYPE BandSet; 194 u8 CurrentChannel; 195 u8 CurrentCenterFrequencyIndex1; 196 u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ 197 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 198 199 u16 CustomerID; 200 u16 BasicRateSet; 201 u16 ForcedDataRate;/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 202 u32 ReceiveConfig; 203 204 /* rf_ctrl */ 205 u8 rf_chip; 206 u8 rf_type; 207 u8 PackageType; 208 u8 NumTotalRFPath; 209 210 u8 InterfaceSel; 211 u8 framesync; 212 u32 framesyncC34; 213 u8 framesyncMonitor; 214 u8 DefaultInitialGain[4]; 215 /* EEPROM setting. */ 216 u16 EEPROMVID; 217 u16 EEPROMSVID; 218 219 u8 EEPROMCustomerID; 220 u8 EEPROMSubCustomerID; 221 u8 EEPROMVersion; 222 u8 EEPROMRegulatory; 223 u8 EEPROMThermalMeter; 224 u8 EEPROMBluetoothCoexist; 225 u8 EEPROMBluetoothType; 226 u8 EEPROMBluetoothAntNum; 227 u8 EEPROMBluetoothAntIsolation; 228 u8 EEPROMBluetoothRadioShared; 229 u8 bTXPowerDataReadFromEEPORM; 230 u8 bAPKThermalMeterIgnore; 231 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 232 233 bool EepromOrEfuse; 234 u8 EfuseUsedPercentage; 235 u16 EfuseUsedBytes; 236 EFUSE_HAL EfuseHal; 237 238 /* 3 [2.4G] */ 239 u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 240 u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 241 /* If only one tx, only BW20 and OFDM are used. */ 242 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 243 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 244 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 245 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 246 /* 3 [5G] */ 247 u8 Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 248 u8 Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 249 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 250 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 251 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 252 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 253 254 u8 Regulation2_4G; 255 u8 Regulation5G; 256 257 u8 TxPwrInPercentage; 258 259 u8 TxPwrCalibrateRate; 260 /* TX power by rate table at most 4RF path. */ 261 /* The register is */ 262 /* VHT TX power by rate off setArray = */ 263 /* Band:-2G&5G = 0 / 1 */ 264 /* RF: at most 4*4 = ABCD = 0/1/2/3 */ 265 /* CCK = 0 OFDM = 1/2 HT-MCS 0-15 =3/4/56 VHT =7/8/9/10/11 */ 266 u8 TxPwrByRateTable; 267 u8 TxPwrByRateBand; 268 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] 269 [TX_PWR_BY_RATE_NUM_RF] 270 [TX_PWR_BY_RATE_NUM_RF] 271 [TX_PWR_BY_RATE_NUM_RATE]; 272 /* */ 273 274 /* 2 Power Limit Table */ 275 u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 276 u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ 277 u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ 278 s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */ 279 u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */ 280 281 /* Power Limit Table for 2.4G */ 282 s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] 283 [MAX_2_4G_BANDWIDTH_NUM] 284 [MAX_RATE_SECTION_NUM] 285 [CHANNEL_MAX_NUMBER_2G] 286 [MAX_RF_PATH_NUM]; 287 288 /* Power Limit Table for 5G */ 289 s8 TxPwrLimit_5G[MAX_REGULATION_NUM] 290 [MAX_5G_BANDWIDTH_NUM] 291 [MAX_RATE_SECTION_NUM] 292 [CHANNEL_MAX_NUMBER_5G] 293 [MAX_RF_PATH_NUM]; 294 295 296 /* Store the original power by rate value of the base of each rate section of rf path A & B */ 297 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] 298 [TX_PWR_BY_RATE_NUM_RF] 299 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; 300 u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] 301 [TX_PWR_BY_RATE_NUM_RF] 302 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 303 304 /* For power group */ 305 u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 306 u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 307 308 309 310 311 u8 PGMaxGroup; 312 u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */ 313 /* The current Tx Power Level */ 314 u8 CurrentCckTxPwrIdx; 315 u8 CurrentOfdm24GTxPwrIdx; 316 u8 CurrentBW2024GTxPwrIdx; 317 u8 CurrentBW4024GTxPwrIdx; 318 319 /* Read/write are allow for following hardware information variables */ 320 u8 pwrGroupCnt; 321 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; 322 u32 CCKTxPowerLevelOriginalOffset; 323 324 u8 CrystalCap; 325 u32 AntennaTxPath; /* Antenna path Tx */ 326 u32 AntennaRxPath; /* Antenna path Rx */ 327 328 u8 PAType_2G; 329 u8 PAType_5G; 330 u8 LNAType_2G; 331 u8 LNAType_5G; 332 u8 ExternalPA_2G; 333 u8 ExternalLNA_2G; 334 u8 ExternalPA_5G; 335 u8 ExternalLNA_5G; 336 u8 TypeGLNA; 337 u8 TypeGPA; 338 u8 TypeALNA; 339 u8 TypeAPA; 340 u8 RFEType; 341 u8 BoardType; 342 u8 ExternalPA; 343 u8 bIQKInitialized; 344 bool bLCKInProgress; 345 346 bool bSwChnl; 347 bool bSetChnlBW; 348 bool bChnlBWInitialized; 349 bool bNeedIQK; 350 351 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 352 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 353 u8 b1x1RecvCombine; /* for 1T1R receive combining */ 354 355 u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ 356 357 struct bb_register_def PHYRegDef[4]; /* Radio A/B/C/D */ 358 359 u32 RfRegChnlVal[2]; 360 361 /* RDG enable */ 362 bool bRDGEnable; 363 364 /* for host message to fw */ 365 u8 LastHMEBoxNum; 366 367 u8 fw_ractrl; 368 u8 RegTxPause; 369 /* Beacon function related global variable. */ 370 u8 RegBcnCtrlVal; 371 u8 RegFwHwTxQCtrl; 372 u8 RegReg542; 373 u8 RegCR_1; 374 u8 Reg837; 375 u8 RegRFPathS1; 376 u16 RegRRSR; 377 378 u8 CurAntenna; 379 u8 AntDivCfg; 380 u8 AntDetection; 381 u8 TRxAntDivType; 382 u8 ant_path; /* for 8723B s0/s1 selection */ 383 384 u8 u1ForcedIgiLb; /* forced IGI lower bound */ 385 386 u8 bDumpRxPkt;/* for debug */ 387 u8 bDumpTxPkt;/* for debug */ 388 u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */ 389 390 /* 2010/08/09 MH Add CU power down mode. */ 391 bool pwrdown; 392 393 /* Add for dual MAC 0--Mac0 1--Mac1 */ 394 u32 interfaceIndex; 395 396 u8 OutEpQueueSel; 397 u8 OutEpNumber; 398 399 /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ 400 bool UsbRxHighSpeedMode; 401 402 /* 2010/11/22 MH Add for slim combo debug mode selective. */ 403 /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */ 404 bool SlimComboDbg; 405 406 /* u8 AMPDUDensity; */ 407 408 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 409 u8 bMacPwrCtrlOn; 410 411 u8 RegIQKFWOffload; 412 struct submit_ctx iqk_sctx; 413 414 enum RT_AMPDU_BURST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ 415 416 u32 sdio_himr; 417 u32 sdio_hisr; 418 419 /* SDIO Tx FIFO related. */ 420 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ 421 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 422 _lock SdioTxFIFOFreePageLock; 423 u8 SdioTxOQTMaxFreeSpace; 424 u8 SdioTxOQTFreeSpace; 425 426 427 /* SDIO Rx FIFO related. */ 428 u8 SdioRxFIFOCnt; 429 u16 SdioRxFIFOSize; 430 431 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ 432 433 struct dm_priv dmpriv; 434 DM_ODM_T odmpriv; 435 436 /* For bluetooth co-existance */ 437 BT_COEXIST bt_coexist; 438 439 /* Interrupt related register information. */ 440 u32 SysIntrStatus; 441 u32 SysIntrMask; 442 443 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 444 s16 noise[ODM_MAX_CHANNEL_NUM]; 445 #endif 446 447 }; 448 449 #define GET_HAL_DATA(__padapter) ((struct hal_com_data *)((__padapter)->HalData)) 450 #define GET_HAL_RFPATH_NUM(__padapter) (((struct hal_com_data *)((__padapter)->HalData))->NumTotalRFPath) 451 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 452 #define GET_RF_TYPE(__padapter) (GET_HAL_DATA(__padapter)->rf_type) 453 454 #endif /* __HAL_DATA_H__ */ 455
