1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 #ifndef __HAL8188EPWRSEQ_H__ 9 #define __HAL8188EPWRSEQ_H__ 10 11 #include "pwrseqcmd.h" 12 13 /* 14 * Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd 15 * There are 6 HW Power States: 16 * 0: POFF--Power Off 17 * 1: PDN--Power Down 18 * 2: CARDEMU--Card Emulation 19 * 3: ACT--Active Mode 20 * 4: LPS--Low Power State 21 * 5: SUS--Suspend 22 * 23 * The transition from different states are defined below 24 * TRANS_CARDEMU_TO_ACT 25 * TRANS_ACT_TO_CARDEMU 26 * TRANS_CARDEMU_TO_SUS 27 * TRANS_SUS_TO_CARDEMU 28 * TRANS_CARDEMU_TO_PDN 29 * TRANS_ACT_TO_LPS 30 * TRANS_LPS_TO_ACT 31 * 32 * TRANS_END 33 * 34 * PWR SEQ Version: rtl8188E_PwrSeq_V09.h 35 */ 36 #define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 37 #define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 38 #define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 39 #define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 40 #define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 41 #define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 42 #define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 43 #define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 44 #define RTL8188E_TRANS_END_STEPS 1 45 46 47 #define RTL8188E_TRANS_CARDEMU_TO_ACT \ 48 /* format 49 * { offset, cut_msk, cmd, msk, value 50 * }, 51 * comment here 52 */ \ 53 {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 54 /* wait till 0x04[17] = 1 power ready*/ \ 55 {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \ 56 /* 0x02[1:0] = 0 reset BB*/ \ 57 {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ 58 /*0x24[23] = 2b'01 schmit trigger */ \ 59 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \ 60 /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \ 61 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \ 62 /*0x04[12:11] = 2b'00 disable WL suspend*/ \ 63 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 64 /*0x04[8] = 1 polling until return 0*/ \ 65 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \ 66 /*wait till 0x04[8] = 0*/ \ 67 {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ 68 /*LDO normal mode*/ 69 70 #define RTL8188E_TRANS_ACT_TO_CARDEMU \ 71 /* format 72 * { offset, cut_msk, cmd, msk, value 73 * }, 74 * comments here 75 */ \ 76 {0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \ 77 /*0x1F[7:0] = 0 turn off RF*/ \ 78 {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 79 /*LDO Sleep mode*/ \ 80 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 81 /*0x04[9] = 1 turn off MAC by HW state machine*/ \ 82 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \ 83 /*wait till 0x04[9] = 0 polling until return 0 to disable*/ 84 85 #define RTL8188E_TRANS_CARDEMU_TO_SUS \ 86 /* format 87 * { offset, cut_msk, cmd, msk, 88 * value }, 89 * comments here 90 */ \ 91 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ 92 /* 0x04[12:11] = 2b'01enable WL suspend */ \ 93 {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \ 94 /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ 95 {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ 96 /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ 97 {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 98 /*Set USB suspend enable local register 0xfe10[4]=1 */ 99 100 #define RTL8188E_TRANS_SUS_TO_CARDEMU \ 101 /* format 102 * { offset, cut_msk, cmd, msk, 103 * value }, 104 * comments here 105 */ \ 106 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ 107 /*0x04[12:11] = 2b'01enable WL suspend*/ 108 109 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ 110 /* format 111 * { offset, cut_msk, cmd, msk, 112 * value }, 113 * comments here 114 */ \ 115 {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ 116 /*0x24[23] = 2b'01 schmit trigger */ \ 117 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ 118 /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 119 {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \ 120 /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ 121 {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ 122 /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ 123 {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 124 /*Set USB suspend enable local register 0xfe10[4]=1 */ 125 126 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ 127 /* format 128 * { offset, cut_msk, cmd, msk, 129 * value }, 130 * comments here 131 */ \ 132 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ 133 /*0x04[12:11] = 2b'01enable WL suspend*/ 134 135 #define RTL8188E_TRANS_CARDEMU_TO_PDN \ 136 /* format 137 * { offset, cut_msk, cmd, msk, 138 * value }, 139 * comments here 140 */ \ 141 {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \ 142 /* 0x04[16] = 0*/ \ 143 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ 144 /* 0x04[15] = 1*/ 145 146 #define RTL8188E_TRANS_PDN_TO_CARDEMU \ 147 /* format 148 * { offset, cut_msk, cmd, msk, 149 * value }, 150 * comments here 151 */ \ 152 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \ 153 /* 0x04[15] = 0*/ 154 155 /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ 156 #define RTL8188E_TRANS_ACT_TO_LPS \ 157 /* format 158 * { offset, cut_msk, cmd, msk, 159 * value }, 160 * comments here 161 */ \ 162 {0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ 163 {0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ 164 /*Should be zero if no packet is transmitting*/ \ 165 {0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ 166 /*Should be zero if no packet is transmitting*/ \ 167 {0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ 168 /*Should be zero if no packet is transmitting*/ \ 169 {0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ 170 /*Should be zero if no packet is transmitting*/ \ 171 {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \ 172 /*CCK and OFDM are disabled,and clock are gated*/ \ 173 {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \ 174 /*Delay 1us*/ \ 175 {0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \ 176 /*Reset MAC TRX*/ \ 177 {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \ 178 /*check if removed later*/\ 179 {0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \ 180 /*Respond TxOK to scheduler*/ 181 182 183 #define RTL8188E_TRANS_LPS_TO_ACT \ 184 /* format 185 * { offset, cut_msk, cmd, msk, 186 * value }, 187 * comments here 188 */ \ 189 {0xFE58, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x84}, \ 190 /*USB RPWM*/ \ 191 {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \ 192 /*Delay*/ \ 193 {0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ 194 /* 0x08[4] = 0 switch TSF to 40M */ \ 195 {0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \ 196 /* Polling 0x109[7]=0 TSF in 40M */ \ 197 {0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \ 198 /* 0x29[7:6] = 2b'00 enable BB clock */ \ 199 {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 200 /* 0x101[1] = 1 */ \ 201 {0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 202 /* 0x100[7:0] = 0xFF enable WMAC TRX */ \ 203 {0x0002, PWR_CUT_ALL_MSK, \ 204 PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ 205 /* 0x02[1:0] = 2b'11 enable BB macro */ \ 206 {0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ 207 208 #define RTL8188E_TRANS_END \ 209 /* format 210 * { offset, cut_msk, cmd, msk, 211 * value }, 212 * comments here 213 */ \ 214 {0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0}, 215 216 217 extern struct wl_pwr_cfg rtl8188E_power_on_flow 218 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS]; 219 extern struct wl_pwr_cfg rtl8188E_radio_off_flow 220 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS]; 221 extern struct wl_pwr_cfg rtl8188E_card_disable_flow 222 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 223 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 224 RTL8188E_TRANS_END_STEPS]; 225 extern struct wl_pwr_cfg rtl8188E_card_enable_flow 226 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 227 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 228 RTL8188E_TRANS_END_STEPS]; 229 extern struct wl_pwr_cfg rtl8188E_suspend_flow[ 230 RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 231 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + 232 RTL8188E_TRANS_END_STEPS]; 233 extern struct wl_pwr_cfg rtl8188E_resume_flow 234 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 235 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + 236 RTL8188E_TRANS_END_STEPS]; 237 extern struct wl_pwr_cfg rtl8188E_hwpdn_flow 238 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 239 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS]; 240 extern struct wl_pwr_cfg rtl8188E_enter_lps_flow 241 [RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS]; 242 extern struct wl_pwr_cfg rtl8188E_leave_lps_flow 243 [RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS]; 244 245 #endif /* __HAL8188EPWRSEQ_H__ */ 246
