1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * rt5677.h -- RT5677 ALSA SoC audio driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9 #ifndef __RT5677_H__ 10 #define __RT5677_H__ 11 12 #include <linux/gpio/driver.h> 13 #include <linux/gpio/consumer.h> 14 15 /* Info */ 16 #define RT5677_RESET 0x00 17 #define RT5677_VENDOR_ID 0xfd 18 #define RT5677_VENDOR_ID1 0xfe 19 #define RT5677_VENDOR_ID2 0xff 20 /* I/O - Output */ 21 #define RT5677_LOUT1 0x01 22 /* I/O - Input */ 23 #define RT5677_IN1 0x03 24 #define RT5677_MICBIAS 0x04 25 /* I/O - SLIMBus */ 26 #define RT5677_SLIMBUS_PARAM 0x07 27 #define RT5677_SLIMBUS_RX 0x08 28 #define RT5677_SLIMBUS_CTRL 0x09 29 /* I/O */ 30 #define RT5677_SIDETONE_CTRL 0x13 31 /* I/O - ADC/DAC */ 32 #define RT5677_ANA_DAC1_2_3_SRC 0x15 33 #define RT5677_IF_DSP_DAC3_4_MIXER 0x16 34 #define RT5677_DAC4_DIG_VOL 0x17 35 #define RT5677_DAC3_DIG_VOL 0x18 36 #define RT5677_DAC1_DIG_VOL 0x19 37 #define RT5677_DAC2_DIG_VOL 0x1a 38 #define RT5677_IF_DSP_DAC2_MIXER 0x1b 39 #define RT5677_STO1_ADC_DIG_VOL 0x1c 40 #define RT5677_MONO_ADC_DIG_VOL 0x1d 41 #define RT5677_STO1_2_ADC_BST 0x1e 42 #define RT5677_STO2_ADC_DIG_VOL 0x1f 43 /* Mixer - D-D */ 44 #define RT5677_ADC_BST_CTRL2 0x20 45 #define RT5677_STO3_4_ADC_BST 0x21 46 #define RT5677_STO3_ADC_DIG_VOL 0x22 47 #define RT5677_STO4_ADC_DIG_VOL 0x23 48 #define RT5677_STO4_ADC_MIXER 0x24 49 #define RT5677_STO3_ADC_MIXER 0x25 50 #define RT5677_STO2_ADC_MIXER 0x26 51 #define RT5677_STO1_ADC_MIXER 0x27 52 #define RT5677_MONO_ADC_MIXER 0x28 53 #define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29 54 #define RT5677_STO1_DAC_MIXER 0x2a 55 #define RT5677_MONO_DAC_MIXER 0x2b 56 #define RT5677_DD1_MIXER 0x2c 57 #define RT5677_DD2_MIXER 0x2d 58 #define RT5677_IF3_DATA 0x2f 59 #define RT5677_IF4_DATA 0x30 60 /* Mixer - PDM */ 61 #define RT5677_PDM_OUT_CTRL 0x31 62 #define RT5677_PDM_DATA_CTRL1 0x32 63 #define RT5677_PDM_DATA_CTRL2 0x33 64 #define RT5677_PDM1_DATA_CTRL2 0x34 65 #define RT5677_PDM1_DATA_CTRL3 0x35 66 #define RT5677_PDM1_DATA_CTRL4 0x36 67 #define RT5677_PDM2_DATA_CTRL2 0x37 68 #define RT5677_PDM2_DATA_CTRL3 0x38 69 #define RT5677_PDM2_DATA_CTRL4 0x39 70 /* TDM */ 71 #define RT5677_TDM1_CTRL1 0x3b 72 #define RT5677_TDM1_CTRL2 0x3c 73 #define RT5677_TDM1_CTRL3 0x3d 74 #define RT5677_TDM1_CTRL4 0x3e 75 #define RT5677_TDM1_CTRL5 0x3f 76 #define RT5677_TDM2_CTRL1 0x40 77 #define RT5677_TDM2_CTRL2 0x41 78 #define RT5677_TDM2_CTRL3 0x42 79 #define RT5677_TDM2_CTRL4 0x43 80 #define RT5677_TDM2_CTRL5 0x44 81 /* I2C_MASTER_CTRL */ 82 #define RT5677_I2C_MASTER_CTRL1 0x47 83 #define RT5677_I2C_MASTER_CTRL2 0x48 84 #define RT5677_I2C_MASTER_CTRL3 0x49 85 #define RT5677_I2C_MASTER_CTRL4 0x4a 86 #define RT5677_I2C_MASTER_CTRL5 0x4b 87 #define RT5677_I2C_MASTER_CTRL6 0x4c 88 #define RT5677_I2C_MASTER_CTRL7 0x4d 89 #define RT5677_I2C_MASTER_CTRL8 0x4e 90 /* DMIC */ 91 #define RT5677_DMIC_CTRL1 0x50 92 #define RT5677_DMIC_CTRL2 0x51 93 /* Haptic Generator */ 94 #define RT5677_HAP_GENE_CTRL1 0x56 95 #define RT5677_HAP_GENE_CTRL2 0x57 96 #define RT5677_HAP_GENE_CTRL3 0x58 97 #define RT5677_HAP_GENE_CTRL4 0x59 98 #define RT5677_HAP_GENE_CTRL5 0x5a 99 #define RT5677_HAP_GENE_CTRL6 0x5b 100 #define RT5677_HAP_GENE_CTRL7 0x5c 101 #define RT5677_HAP_GENE_CTRL8 0x5d 102 #define RT5677_HAP_GENE_CTRL9 0x5e 103 #define RT5677_HAP_GENE_CTRL10 0x5f 104 /* Power */ 105 #define RT5677_PWR_DIG1 0x61 106 #define RT5677_PWR_DIG2 0x62 107 #define RT5677_PWR_ANLG1 0x63 108 #define RT5677_PWR_ANLG2 0x64 109 #define RT5677_PWR_DSP1 0x65 110 #define RT5677_PWR_DSP_ST 0x66 111 #define RT5677_PWR_DSP2 0x67 112 #define RT5677_ADC_DAC_HPF_CTRL1 0x68 113 /* Private Register Control */ 114 #define RT5677_PRIV_INDEX 0x6a 115 #define RT5677_PRIV_DATA 0x6c 116 /* Format - ADC/DAC */ 117 #define RT5677_I2S4_SDP 0x6f 118 #define RT5677_I2S1_SDP 0x70 119 #define RT5677_I2S2_SDP 0x71 120 #define RT5677_I2S3_SDP 0x72 121 #define RT5677_CLK_TREE_CTRL1 0x73 122 #define RT5677_CLK_TREE_CTRL2 0x74 123 #define RT5677_CLK_TREE_CTRL3 0x75 124 /* Function - Analog */ 125 #define RT5677_PLL1_CTRL1 0x7a 126 #define RT5677_PLL1_CTRL2 0x7b 127 #define RT5677_PLL2_CTRL1 0x7c 128 #define RT5677_PLL2_CTRL2 0x7d 129 #define RT5677_GLB_CLK1 0x80 130 #define RT5677_GLB_CLK2 0x81 131 #define RT5677_ASRC_1 0x83 132 #define RT5677_ASRC_2 0x84 133 #define RT5677_ASRC_3 0x85 134 #define RT5677_ASRC_4 0x86 135 #define RT5677_ASRC_5 0x87 136 #define RT5677_ASRC_6 0x88 137 #define RT5677_ASRC_7 0x89 138 #define RT5677_ASRC_8 0x8a 139 #define RT5677_ASRC_9 0x8b 140 #define RT5677_ASRC_10 0x8c 141 #define RT5677_ASRC_11 0x8d 142 #define RT5677_ASRC_12 0x8e 143 #define RT5677_ASRC_13 0x8f 144 #define RT5677_ASRC_14 0x90 145 #define RT5677_ASRC_15 0x91 146 #define RT5677_ASRC_16 0x92 147 #define RT5677_ASRC_17 0x93 148 #define RT5677_ASRC_18 0x94 149 #define RT5677_ASRC_19 0x95 150 #define RT5677_ASRC_20 0x97 151 #define RT5677_ASRC_21 0x98 152 #define RT5677_ASRC_22 0x99 153 #define RT5677_ASRC_23 0x9a 154 #define RT5677_VAD_CTRL1 0x9c 155 #define RT5677_VAD_CTRL2 0x9d 156 #define RT5677_VAD_CTRL3 0x9e 157 #define RT5677_VAD_CTRL4 0x9f 158 #define RT5677_VAD_CTRL5 0xa0 159 /* Function - Digital */ 160 #define RT5677_DSP_INB_CTRL1 0xa3 161 #define RT5677_DSP_INB_CTRL2 0xa4 162 #define RT5677_DSP_IN_OUTB_CTRL 0xa5 163 #define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6 164 #define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7 165 #define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8 166 #define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9 167 #define RT5677_ADC_EQ_CTRL1 0xae 168 #define RT5677_ADC_EQ_CTRL2 0xaf 169 #define RT5677_EQ_CTRL1 0xb0 170 #define RT5677_EQ_CTRL2 0xb1 171 #define RT5677_EQ_CTRL3 0xb2 172 #define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3 173 #define RT5677_JD_CTRL1 0xb5 174 #define RT5677_JD_CTRL2 0xb6 175 #define RT5677_JD_CTRL3 0xb8 176 #define RT5677_IRQ_CTRL1 0xbd 177 #define RT5677_IRQ_CTRL2 0xbe 178 #define RT5677_GPIO_ST 0xbf 179 #define RT5677_GPIO_CTRL1 0xc0 180 #define RT5677_GPIO_CTRL2 0xc1 181 #define RT5677_GPIO_CTRL3 0xc2 182 #define RT5677_STO1_ADC_HI_FILTER1 0xc5 183 #define RT5677_STO1_ADC_HI_FILTER2 0xc6 184 #define RT5677_MONO_ADC_HI_FILTER1 0xc7 185 #define RT5677_MONO_ADC_HI_FILTER2 0xc8 186 #define RT5677_STO2_ADC_HI_FILTER1 0xc9 187 #define RT5677_STO2_ADC_HI_FILTER2 0xca 188 #define RT5677_STO3_ADC_HI_FILTER1 0xcb 189 #define RT5677_STO3_ADC_HI_FILTER2 0xcc 190 #define RT5677_STO4_ADC_HI_FILTER1 0xcd 191 #define RT5677_STO4_ADC_HI_FILTER2 0xce 192 #define RT5677_MB_DRC_CTRL1 0xd0 193 #define RT5677_DRC1_CTRL1 0xd2 194 #define RT5677_DRC1_CTRL2 0xd3 195 #define RT5677_DRC1_CTRL3 0xd4 196 #define RT5677_DRC1_CTRL4 0xd5 197 #define RT5677_DRC1_CTRL5 0xd6 198 #define RT5677_DRC1_CTRL6 0xd7 199 #define RT5677_DRC2_CTRL1 0xd8 200 #define RT5677_DRC2_CTRL2 0xd9 201 #define RT5677_DRC2_CTRL3 0xda 202 #define RT5677_DRC2_CTRL4 0xdb 203 #define RT5677_DRC2_CTRL5 0xdc 204 #define RT5677_DRC2_CTRL6 0xdd 205 #define RT5677_DRC1_HL_CTRL1 0xde 206 #define RT5677_DRC1_HL_CTRL2 0xdf 207 #define RT5677_DRC2_HL_CTRL1 0xe0 208 #define RT5677_DRC2_HL_CTRL2 0xe1 209 #define RT5677_DSP_INB1_SRC_CTRL1 0xe3 210 #define RT5677_DSP_INB1_SRC_CTRL2 0xe4 211 #define RT5677_DSP_INB1_SRC_CTRL3 0xe5 212 #define RT5677_DSP_INB1_SRC_CTRL4 0xe6 213 #define RT5677_DSP_INB2_SRC_CTRL1 0xe7 214 #define RT5677_DSP_INB2_SRC_CTRL2 0xe8 215 #define RT5677_DSP_INB2_SRC_CTRL3 0xe9 216 #define RT5677_DSP_INB2_SRC_CTRL4 0xea 217 #define RT5677_DSP_INB3_SRC_CTRL1 0xeb 218 #define RT5677_DSP_INB3_SRC_CTRL2 0xec 219 #define RT5677_DSP_INB3_SRC_CTRL3 0xed 220 #define RT5677_DSP_INB3_SRC_CTRL4 0xee 221 #define RT5677_DSP_OUTB1_SRC_CTRL1 0xef 222 #define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0 223 #define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1 224 #define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2 225 #define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3 226 #define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4 227 #define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5 228 #define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6 229 230 /* Virtual DSP Mixer Control */ 231 #define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7 232 #define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8 233 #define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9 234 235 /* General Control */ 236 #define RT5677_DIG_MISC 0xfa 237 #define RT5677_GEN_CTRL1 0xfb 238 #define RT5677_GEN_CTRL2 0xfc 239 240 /* DSP Mode I2C Control*/ 241 #define RT5677_DSP_I2C_OP_CODE 0x00 242 #define RT5677_DSP_I2C_ADDR_LSB 0x01 243 #define RT5677_DSP_I2C_ADDR_MSB 0x02 244 #define RT5677_DSP_I2C_DATA_LSB 0x03 245 #define RT5677_DSP_I2C_DATA_MSB 0x04 246 247 /* Index of Codec Private Register definition */ 248 #define RT5677_PR_DRC1_CTRL_1 0x01 249 #define RT5677_PR_DRC1_CTRL_2 0x02 250 #define RT5677_PR_DRC1_CTRL_3 0x03 251 #define RT5677_PR_DRC1_CTRL_4 0x04 252 #define RT5677_PR_DRC1_CTRL_5 0x05 253 #define RT5677_PR_DRC1_CTRL_6 0x06 254 #define RT5677_PR_DRC1_CTRL_7 0x07 255 #define RT5677_PR_DRC2_CTRL_1 0x08 256 #define RT5677_PR_DRC2_CTRL_2 0x09 257 #define RT5677_PR_DRC2_CTRL_3 0x0a 258 #define RT5677_PR_DRC2_CTRL_4 0x0b 259 #define RT5677_PR_DRC2_CTRL_5 0x0c 260 #define RT5677_PR_DRC2_CTRL_6 0x0d 261 #define RT5677_PR_DRC2_CTRL_7 0x0e 262 #define RT5677_BIAS_CUR1 0x10 263 #define RT5677_BIAS_CUR2 0x12 264 #define RT5677_BIAS_CUR3 0x13 265 #define RT5677_BIAS_CUR4 0x14 266 #define RT5677_BIAS_CUR5 0x15 267 #define RT5677_VREF_LOUT_CTRL 0x17 268 #define RT5677_DIG_VOL_CTRL1 0x1a 269 #define RT5677_DIG_VOL_CTRL2 0x1b 270 #define RT5677_ANA_ADC_GAIN_CTRL 0x1e 271 #define RT5677_VAD_SRAM_TEST1 0x20 272 #define RT5677_VAD_SRAM_TEST2 0x21 273 #define RT5677_VAD_SRAM_TEST3 0x22 274 #define RT5677_VAD_SRAM_TEST4 0x23 275 #define RT5677_PAD_DRV_CTRL 0x26 276 #define RT5677_DIG_IN_PIN_ST_CTRL1 0x29 277 #define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a 278 #define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b 279 #define RT5677_PLL1_INT 0x38 280 #define RT5677_PLL2_INT 0x39 281 #define RT5677_TEST_CTRL1 0x3a 282 #define RT5677_TEST_CTRL2 0x3b 283 #define RT5677_TEST_CTRL3 0x3c 284 #define RT5677_CHOP_DAC_ADC 0x3d 285 #define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e 286 #define RT5677_CROSS_OVER_FILTER1 0x90 287 #define RT5677_CROSS_OVER_FILTER2 0x91 288 #define RT5677_CROSS_OVER_FILTER3 0x92 289 #define RT5677_CROSS_OVER_FILTER4 0x93 290 #define RT5677_CROSS_OVER_FILTER5 0x94 291 #define RT5677_CROSS_OVER_FILTER6 0x95 292 #define RT5677_CROSS_OVER_FILTER7 0x96 293 #define RT5677_CROSS_OVER_FILTER8 0x97 294 #define RT5677_CROSS_OVER_FILTER9 0x98 295 #define RT5677_CROSS_OVER_FILTER10 0x99 296 297 /* global definition */ 298 #define RT5677_L_MUTE (0x1 << 15) 299 #define RT5677_L_MUTE_SFT 15 300 #define RT5677_VOL_L_MUTE (0x1 << 14) 301 #define RT5677_VOL_L_SFT 14 302 #define RT5677_R_MUTE (0x1 << 7) 303 #define RT5677_R_MUTE_SFT 7 304 #define RT5677_VOL_R_MUTE (0x1 << 6) 305 #define RT5677_VOL_R_SFT 6 306 #define RT5677_L_VOL_MASK (0x7f << 9) 307 #define RT5677_L_VOL_SFT 9 308 #define RT5677_R_VOL_MASK (0x7f << 1) 309 #define RT5677_R_VOL_SFT 1 310 311 /* LOUT1 Control (0x01) */ 312 #define RT5677_LOUT1_L_MUTE (0x1 << 15) 313 #define RT5677_LOUT1_L_MUTE_SFT (15) 314 #define RT5677_LOUT1_L_DF (0x1 << 14) 315 #define RT5677_LOUT1_L_DF_SFT (14) 316 #define RT5677_LOUT2_L_MUTE (0x1 << 13) 317 #define RT5677_LOUT2_L_MUTE_SFT (13) 318 #define RT5677_LOUT2_L_DF (0x1 << 12) 319 #define RT5677_LOUT2_L_DF_SFT (12) 320 #define RT5677_LOUT3_L_MUTE (0x1 << 11) 321 #define RT5677_LOUT3_L_MUTE_SFT (11) 322 #define RT5677_LOUT3_L_DF (0x1 << 10) 323 #define RT5677_LOUT3_L_DF_SFT (10) 324 #define RT5677_LOUT1_ENH_DRV (0x1 << 9) 325 #define RT5677_LOUT1_ENH_DRV_SFT (9) 326 #define RT5677_LOUT2_ENH_DRV (0x1 << 8) 327 #define RT5677_LOUT2_ENH_DRV_SFT (8) 328 #define RT5677_LOUT3_ENH_DRV (0x1 << 7) 329 #define RT5677_LOUT3_ENH_DRV_SFT (7) 330 331 /* IN1 Control (0x03) */ 332 #define RT5677_BST_MASK1 (0xf << 12) 333 #define RT5677_BST_SFT1 12 334 #define RT5677_BST_MASK2 (0xf << 8) 335 #define RT5677_BST_SFT2 8 336 #define RT5677_IN_DF1 (0x1 << 7) 337 #define RT5677_IN_DF1_SFT 7 338 #define RT5677_IN_DF2 (0x1 << 6) 339 #define RT5677_IN_DF2_SFT 6 340 341 /* Micbias Control (0x04) */ 342 #define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15) 343 #define RT5677_MICBIAS1_OUTVOLT_SFT (15) 344 #define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15) 345 #define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15) 346 #define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14) 347 #define RT5677_MICBIAS1_CTRL_VDD_SFT (14) 348 #define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14) 349 #define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14) 350 #define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11) 351 #define RT5677_MICBIAS1_OVCD_SHIFT (11) 352 #define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11) 353 #define RT5677_MICBIAS1_OVCD_EN (0x1 << 11) 354 #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9) 355 #define RT5677_MICBIAS1_OVTH_SFT 9 356 #define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9) 357 #define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9) 358 #define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9) 359 360 /* SLIMbus Parameter (0x07) */ 361 362 /* SLIMbus Rx (0x08) */ 363 #define RT5677_SLB_ADC4_MASK (0x3 << 6) 364 #define RT5677_SLB_ADC4_SFT 6 365 #define RT5677_SLB_ADC3_MASK (0x3 << 4) 366 #define RT5677_SLB_ADC3_SFT 4 367 #define RT5677_SLB_ADC2_MASK (0x3 << 2) 368 #define RT5677_SLB_ADC2_SFT 2 369 #define RT5677_SLB_ADC1_MASK (0x3 << 0) 370 #define RT5677_SLB_ADC1_SFT 0 371 372 /* SLIMBus control (0x09) */ 373 374 /* Sidetone Control (0x13) */ 375 #define RT5677_ST_HPF_SEL_MASK (0x7 << 13) 376 #define RT5677_ST_HPF_SEL_SFT 13 377 #define RT5677_ST_HPF_PATH (0x1 << 12) 378 #define RT5677_ST_HPF_PATH_SFT 12 379 #define RT5677_ST_SEL_MASK (0x7 << 9) 380 #define RT5677_ST_SEL_SFT 9 381 #define RT5677_ST_EN (0x1 << 6) 382 #define RT5677_ST_EN_SFT 6 383 #define RT5677_ST_GAIN (0x1 << 5) 384 #define RT5677_ST_GAIN_SFT 5 385 #define RT5677_ST_VOL_MASK (0x1f << 0) 386 #define RT5677_ST_VOL_SFT 0 387 388 /* Analog DAC1/2/3 Source Control (0x15) */ 389 #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4) 390 #define RT5677_ANA_DAC3_SRC_SEL_SFT 4 391 #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0) 392 #define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0 393 394 /* IF/DSP to DAC3/4 Mixer Control (0x16) */ 395 #define RT5677_M_DAC4_L_VOL (0x1 << 15) 396 #define RT5677_M_DAC4_L_VOL_SFT 15 397 #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12) 398 #define RT5677_SEL_DAC4_L_SRC_SFT 12 399 #define RT5677_M_DAC4_R_VOL (0x1 << 11) 400 #define RT5677_M_DAC4_R_VOL_SFT 11 401 #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8) 402 #define RT5677_SEL_DAC4_R_SRC_SFT 8 403 #define RT5677_M_DAC3_L_VOL (0x1 << 7) 404 #define RT5677_M_DAC3_L_VOL_SFT 7 405 #define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4) 406 #define RT5677_SEL_DAC3_L_SRC_SFT 4 407 #define RT5677_M_DAC3_R_VOL (0x1 << 3) 408 #define RT5677_M_DAC3_R_VOL_SFT 3 409 #define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0) 410 #define RT5677_SEL_DAC3_R_SRC_SFT 0 411 412 /* DAC4 Digital Volume (0x17) */ 413 #define RT5677_DAC4_L_VOL_MASK (0xff << 8) 414 #define RT5677_DAC4_L_VOL_SFT 8 415 #define RT5677_DAC4_R_VOL_MASK (0xff) 416 #define RT5677_DAC4_R_VOL_SFT 0 417 418 /* DAC3 Digital Volume (0x18) */ 419 #define RT5677_DAC3_L_VOL_MASK (0xff << 8) 420 #define RT5677_DAC3_L_VOL_SFT 8 421 #define RT5677_DAC3_R_VOL_MASK (0xff) 422 #define RT5677_DAC3_R_VOL_SFT 0 423 424 /* DAC3 Digital Volume (0x19) */ 425 #define RT5677_DAC1_L_VOL_MASK (0xff << 8) 426 #define RT5677_DAC1_L_VOL_SFT 8 427 #define RT5677_DAC1_R_VOL_MASK (0xff) 428 #define RT5677_DAC1_R_VOL_SFT 0 429 430 /* DAC2 Digital Volume (0x1a) */ 431 #define RT5677_DAC2_L_VOL_MASK (0xff << 8) 432 #define RT5677_DAC2_L_VOL_SFT 8 433 #define RT5677_DAC2_R_VOL_MASK (0xff) 434 #define RT5677_DAC2_R_VOL_SFT 0 435 436 /* IF/DSP to DAC2 Mixer Control (0x1b) */ 437 #define RT5677_M_DAC2_L_VOL (0x1 << 7) 438 #define RT5677_M_DAC2_L_VOL_SFT 7 439 #define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4) 440 #define RT5677_SEL_DAC2_L_SRC_SFT 4 441 #define RT5677_M_DAC2_R_VOL (0x1 << 3) 442 #define RT5677_M_DAC2_R_VOL_SFT 3 443 #define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0) 444 #define RT5677_SEL_DAC2_R_SRC_SFT 0 445 446 /* Stereo1 ADC Digital Volume Control (0x1c) */ 447 #define RT5677_STO1_ADC_L_VOL_MASK (0x3f << 9) 448 #define RT5677_STO1_ADC_L_VOL_SFT 9 449 #define RT5677_STO1_ADC_R_VOL_MASK (0x3f << 1) 450 #define RT5677_STO1_ADC_R_VOL_SFT 1 451 452 /* Mono ADC Digital Volume Control (0x1d) */ 453 #define RT5677_MONO_ADC_L_VOL_MASK (0x3f << 9) 454 #define RT5677_MONO_ADC_L_VOL_SFT 9 455 #define RT5677_MONO_ADC_R_VOL_MASK (0x3f << 1) 456 #define RT5677_MONO_ADC_R_VOL_SFT 1 457 458 /* Stereo 1/2 ADC Boost Gain Control (0x1e) */ 459 #define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14) 460 #define RT5677_STO1_ADC_L_BST_SFT 14 461 #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12) 462 #define RT5677_STO1_ADC_R_BST_SFT 12 463 #define RT5677_STO1_ADC_COMP_MASK (0x3 << 10) 464 #define RT5677_STO1_ADC_COMP_SFT 10 465 #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8) 466 #define RT5677_STO2_ADC_L_BST_SFT 8 467 #define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6) 468 #define RT5677_STO2_ADC_R_BST_SFT 6 469 #define RT5677_STO2_ADC_COMP_MASK (0x3 << 4) 470 #define RT5677_STO2_ADC_COMP_SFT 4 471 472 /* Stereo2 ADC Digital Volume Control (0x1f) */ 473 #define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8) 474 #define RT5677_STO2_ADC_L_VOL_SFT 8 475 #define RT5677_STO2_ADC_R_VOL_MASK (0x7f) 476 #define RT5677_STO2_ADC_R_VOL_SFT 0 477 478 /* ADC Boost Gain Control 2 (0x20) */ 479 #define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14) 480 #define RT5677_MONO_ADC_L_BST_SFT 14 481 #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12) 482 #define RT5677_MONO_ADC_R_BST_SFT 12 483 #define RT5677_MONO_ADC_COMP_MASK (0x3 << 10) 484 #define RT5677_MONO_ADC_COMP_SFT 10 485 486 /* Stereo 3/4 ADC Boost Gain Control (0x21) */ 487 #define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14) 488 #define RT5677_STO3_ADC_L_BST_SFT 14 489 #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12) 490 #define RT5677_STO3_ADC_R_BST_SFT 12 491 #define RT5677_STO3_ADC_COMP_MASK (0x3 << 10) 492 #define RT5677_STO3_ADC_COMP_SFT 10 493 #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8) 494 #define RT5677_STO4_ADC_L_BST_SFT 8 495 #define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6) 496 #define RT5677_STO4_ADC_R_BST_SFT 6 497 #define RT5677_STO4_ADC_COMP_MASK (0x3 << 4) 498 #define RT5677_STO4_ADC_COMP_SFT 4 499 500 /* Stereo3 ADC Digital Volume Control (0x22) */ 501 #define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8) 502 #define RT5677_STO3_ADC_L_VOL_SFT 8 503 #define RT5677_STO3_ADC_R_VOL_MASK (0x7f) 504 #define RT5677_STO3_ADC_R_VOL_SFT 0 505 506 /* Stereo4 ADC Digital Volume Control (0x23) */ 507 #define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8) 508 #define RT5677_STO4_ADC_L_VOL_SFT 8 509 #define RT5677_STO4_ADC_R_VOL_MASK (0x7f) 510 #define RT5677_STO4_ADC_R_VOL_SFT 0 511 512 /* Stereo4 ADC Mixer control (0x24) */ 513 #define RT5677_M_STO4_ADC_L2 (0x1 << 15) 514 #define RT5677_M_STO4_ADC_L2_SFT 15 515 #define RT5677_M_STO4_ADC_L1 (0x1 << 14) 516 #define RT5677_M_STO4_ADC_L1_SFT 14 517 #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12) 518 #define RT5677_SEL_STO4_ADC1_SFT 12 519 #define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10) 520 #define RT5677_SEL_STO4_ADC2_SFT 10 521 #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8) 522 #define RT5677_SEL_STO4_DMIC_SFT 8 523 #define RT5677_M_STO4_ADC_R1 (0x1 << 7) 524 #define RT5677_M_STO4_ADC_R1_SFT 7 525 #define RT5677_M_STO4_ADC_R2 (0x1 << 6) 526 #define RT5677_M_STO4_ADC_R2_SFT 6 527 528 /* Stereo3 ADC Mixer control (0x25) */ 529 #define RT5677_M_STO3_ADC_L2 (0x1 << 15) 530 #define RT5677_M_STO3_ADC_L2_SFT 15 531 #define RT5677_M_STO3_ADC_L1 (0x1 << 14) 532 #define RT5677_M_STO3_ADC_L1_SFT 14 533 #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12) 534 #define RT5677_SEL_STO3_ADC1_SFT 12 535 #define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10) 536 #define RT5677_SEL_STO3_ADC2_SFT 10 537 #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8) 538 #define RT5677_SEL_STO3_DMIC_SFT 8 539 #define RT5677_M_STO3_ADC_R1 (0x1 << 7) 540 #define RT5677_M_STO3_ADC_R1_SFT 7 541 #define RT5677_M_STO3_ADC_R2 (0x1 << 6) 542 #define RT5677_M_STO3_ADC_R2_SFT 6 543 544 /* Stereo2 ADC Mixer Control (0x26) */ 545 #define RT5677_M_STO2_ADC_L2 (0x1 << 15) 546 #define RT5677_M_STO2_ADC_L2_SFT 15 547 #define RT5677_M_STO2_ADC_L1 (0x1 << 14) 548 #define RT5677_M_STO2_ADC_L1_SFT 14 549 #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12) 550 #define RT5677_SEL_STO2_ADC1_SFT 12 551 #define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10) 552 #define RT5677_SEL_STO2_ADC2_SFT 10 553 #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8) 554 #define RT5677_SEL_STO2_DMIC_SFT 8 555 #define RT5677_M_STO2_ADC_R1 (0x1 << 7) 556 #define RT5677_M_STO2_ADC_R1_SFT 7 557 #define RT5677_M_STO2_ADC_R2 (0x1 << 6) 558 #define RT5677_M_STO2_ADC_R2_SFT 6 559 #define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0) 560 #define RT5677_SEL_STO2_LR_MIX_SFT 0 561 #define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0) 562 #define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0) 563 564 /* Stereo1 ADC Mixer control (0x27) */ 565 #define RT5677_M_STO1_ADC_L2 (0x1 << 15) 566 #define RT5677_M_STO1_ADC_L2_SFT 15 567 #define RT5677_M_STO1_ADC_L1 (0x1 << 14) 568 #define RT5677_M_STO1_ADC_L1_SFT 14 569 #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12) 570 #define RT5677_SEL_STO1_ADC1_SFT 12 571 #define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10) 572 #define RT5677_SEL_STO1_ADC2_SFT 10 573 #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8) 574 #define RT5677_SEL_STO1_DMIC_SFT 8 575 #define RT5677_M_STO1_ADC_R1 (0x1 << 7) 576 #define RT5677_M_STO1_ADC_R1_SFT 7 577 #define RT5677_M_STO1_ADC_R2 (0x1 << 6) 578 #define RT5677_M_STO1_ADC_R2_SFT 6 579 580 /* Mono ADC Mixer control (0x28) */ 581 #define RT5677_M_MONO_ADC_L2 (0x1 << 15) 582 #define RT5677_M_MONO_ADC_L2_SFT 15 583 #define RT5677_M_MONO_ADC_L1 (0x1 << 14) 584 #define RT5677_M_MONO_ADC_L1_SFT 14 585 #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12) 586 #define RT5677_SEL_MONO_ADC_L1_SFT 12 587 #define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10) 588 #define RT5677_SEL_MONO_ADC_L2_SFT 10 589 #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8) 590 #define RT5677_SEL_MONO_DMIC_L_SFT 8 591 #define RT5677_M_MONO_ADC_R1 (0x1 << 7) 592 #define RT5677_M_MONO_ADC_R1_SFT 7 593 #define RT5677_M_MONO_ADC_R2 (0x1 << 6) 594 #define RT5677_M_MONO_ADC_R2_SFT 6 595 #define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4) 596 #define RT5677_SEL_MONO_ADC_R1_SFT 4 597 #define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2) 598 #define RT5677_SEL_MONO_ADC_R2_SFT 2 599 #define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0) 600 #define RT5677_SEL_MONO_DMIC_R_SFT 0 601 602 /* ADC/IF/DSP to DAC1 Mixer control (0x29) */ 603 #define RT5677_M_ADDA_MIXER1_L (0x1 << 15) 604 #define RT5677_M_ADDA_MIXER1_L_SFT 15 605 #define RT5677_M_DAC1_L (0x1 << 14) 606 #define RT5677_M_DAC1_L_SFT 14 607 #define RT5677_DAC1_L_SEL_MASK (0x7 << 8) 608 #define RT5677_DAC1_L_SEL_SFT 8 609 #define RT5677_M_ADDA_MIXER1_R (0x1 << 7) 610 #define RT5677_M_ADDA_MIXER1_R_SFT 7 611 #define RT5677_M_DAC1_R (0x1 << 6) 612 #define RT5677_M_DAC1_R_SFT 6 613 #define RT5677_ADDA1_SEL_MASK (0x3 << 0) 614 #define RT5677_ADDA1_SEL_SFT 0 615 616 /* Stereo1 DAC Mixer L/R Control (0x2a) */ 617 #define RT5677_M_ST_DAC1_L (0x1 << 15) 618 #define RT5677_M_ST_DAC1_L_SFT 15 619 #define RT5677_M_DAC1_L_STO_L (0x1 << 13) 620 #define RT5677_M_DAC1_L_STO_L_SFT 13 621 #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12) 622 #define RT5677_DAC1_L_STO_L_VOL_SFT 12 623 #define RT5677_M_DAC2_L_STO_L (0x1 << 11) 624 #define RT5677_M_DAC2_L_STO_L_SFT 11 625 #define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10) 626 #define RT5677_DAC2_L_STO_L_VOL_SFT 10 627 #define RT5677_M_DAC1_R_STO_L (0x1 << 9) 628 #define RT5677_M_DAC1_R_STO_L_SFT 9 629 #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8) 630 #define RT5677_DAC1_R_STO_L_VOL_SFT 8 631 #define RT5677_M_ST_DAC1_R (0x1 << 7) 632 #define RT5677_M_ST_DAC1_R_SFT 7 633 #define RT5677_M_DAC1_R_STO_R (0x1 << 5) 634 #define RT5677_M_DAC1_R_STO_R_SFT 5 635 #define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4) 636 #define RT5677_DAC1_R_STO_R_VOL_SFT 4 637 #define RT5677_M_DAC2_R_STO_R (0x1 << 3) 638 #define RT5677_M_DAC2_R_STO_R_SFT 3 639 #define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2) 640 #define RT5677_DAC2_R_STO_R_VOL_SFT 2 641 #define RT5677_M_DAC1_L_STO_R (0x1 << 1) 642 #define RT5677_M_DAC1_L_STO_R_SFT 1 643 #define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0) 644 #define RT5677_DAC1_L_STO_R_VOL_SFT 0 645 646 /* Mono DAC Mixer L/R Control (0x2b) */ 647 #define RT5677_M_ST_DAC2_L (0x1 << 15) 648 #define RT5677_M_ST_DAC2_L_SFT 15 649 #define RT5677_M_DAC2_L_MONO_L (0x1 << 13) 650 #define RT5677_M_DAC2_L_MONO_L_SFT 13 651 #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12) 652 #define RT5677_DAC2_L_MONO_L_VOL_SFT 12 653 #define RT5677_M_DAC2_R_MONO_L (0x1 << 11) 654 #define RT5677_M_DAC2_R_MONO_L_SFT 11 655 #define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10) 656 #define RT5677_DAC2_R_MONO_L_VOL_SFT 10 657 #define RT5677_M_DAC1_L_MONO_L (0x1 << 9) 658 #define RT5677_M_DAC1_L_MONO_L_SFT 9 659 #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8) 660 #define RT5677_DAC1_L_MONO_L_VOL_SFT 8 661 #define RT5677_M_ST_DAC2_R (0x1 << 7) 662 #define RT5677_M_ST_DAC2_R_SFT 7 663 #define RT5677_M_DAC2_R_MONO_R (0x1 << 5) 664 #define RT5677_M_DAC2_R_MONO_R_SFT 5 665 #define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4) 666 #define RT5677_DAC2_R_MONO_R_VOL_SFT 4 667 #define RT5677_M_DAC1_R_MONO_R (0x1 << 3) 668 #define RT5677_M_DAC1_R_MONO_R_SFT 3 669 #define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2) 670 #define RT5677_DAC1_R_MONO_R_VOL_SFT 2 671 #define RT5677_M_DAC2_L_MONO_R (0x1 << 1) 672 #define RT5677_M_DAC2_L_MONO_R_SFT 1 673 #define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0) 674 #define RT5677_DAC2_L_MONO_R_VOL_SFT 0 675 676 /* DD Mixer 1 Control (0x2c) */ 677 #define RT5677_M_STO_L_DD1_L (0x1 << 15) 678 #define RT5677_M_STO_L_DD1_L_SFT 15 679 #define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14) 680 #define RT5677_STO_L_DD1_L_VOL_SFT 14 681 #define RT5677_M_MONO_L_DD1_L (0x1 << 13) 682 #define RT5677_M_MONO_L_DD1_L_SFT 13 683 #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12) 684 #define RT5677_MONO_L_DD1_L_VOL_SFT 12 685 #define RT5677_M_DAC3_L_DD1_L (0x1 << 11) 686 #define RT5677_M_DAC3_L_DD1_L_SFT 11 687 #define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10) 688 #define RT5677_DAC3_L_DD1_L_VOL_SFT 10 689 #define RT5677_M_DAC3_R_DD1_L (0x1 << 9) 690 #define RT5677_M_DAC3_R_DD1_L_SFT 9 691 #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8) 692 #define RT5677_DAC3_R_DD1_L_VOL_SFT 8 693 #define RT5677_M_STO_R_DD1_R (0x1 << 7) 694 #define RT5677_M_STO_R_DD1_R_SFT 7 695 #define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6) 696 #define RT5677_STO_R_DD1_R_VOL_SFT 6 697 #define RT5677_M_MONO_R_DD1_R (0x1 << 5) 698 #define RT5677_M_MONO_R_DD1_R_SFT 5 699 #define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4) 700 #define RT5677_MONO_R_DD1_R_VOL_SFT 4 701 #define RT5677_M_DAC3_R_DD1_R (0x1 << 3) 702 #define RT5677_M_DAC3_R_DD1_R_SFT 3 703 #define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2) 704 #define RT5677_DAC3_R_DD1_R_VOL_SFT 2 705 #define RT5677_M_DAC3_L_DD1_R (0x1 << 1) 706 #define RT5677_M_DAC3_L_DD1_R_SFT 1 707 #define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0) 708 #define RT5677_DAC3_L_DD1_R_VOL_SFT 0 709 710 /* DD Mixer 2 Control (0x2d) */ 711 #define RT5677_M_STO_L_DD2_L (0x1 << 15) 712 #define RT5677_M_STO_L_DD2_L_SFT 15 713 #define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14) 714 #define RT5677_STO_L_DD2_L_VOL_SFT 14 715 #define RT5677_M_MONO_L_DD2_L (0x1 << 13) 716 #define RT5677_M_MONO_L_DD2_L_SFT 13 717 #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12) 718 #define RT5677_MONO_L_DD2_L_VOL_SFT 12 719 #define RT5677_M_DAC4_L_DD2_L (0x1 << 11) 720 #define RT5677_M_DAC4_L_DD2_L_SFT 11 721 #define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10) 722 #define RT5677_DAC4_L_DD2_L_VOL_SFT 10 723 #define RT5677_M_DAC4_R_DD2_L (0x1 << 9) 724 #define RT5677_M_DAC4_R_DD2_L_SFT 9 725 #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8) 726 #define RT5677_DAC4_R_DD2_L_VOL_SFT 8 727 #define RT5677_M_STO_R_DD2_R (0x1 << 7) 728 #define RT5677_M_STO_R_DD2_R_SFT 7 729 #define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6) 730 #define RT5677_STO_R_DD2_R_VOL_SFT 6 731 #define RT5677_M_MONO_R_DD2_R (0x1 << 5) 732 #define RT5677_M_MONO_R_DD2_R_SFT 5 733 #define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4) 734 #define RT5677_MONO_R_DD2_R_VOL_SFT 4 735 #define RT5677_M_DAC4_R_DD2_R (0x1 << 3) 736 #define RT5677_M_DAC4_R_DD2_R_SFT 3 737 #define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2) 738 #define RT5677_DAC4_R_DD2_R_VOL_SFT 2 739 #define RT5677_M_DAC4_L_DD2_R (0x1 << 1) 740 #define RT5677_M_DAC4_L_DD2_R_SFT 1 741 #define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0) 742 #define RT5677_DAC4_L_DD2_R_VOL_SFT 0 743 744 /* IF3 data control (0x2f) */ 745 #define RT5677_IF3_DAC_SEL_MASK (0x3 << 6) 746 #define RT5677_IF3_DAC_SEL_SFT 6 747 #define RT5677_IF3_ADC_SEL_MASK (0x3 << 4) 748 #define RT5677_IF3_ADC_SEL_SFT 4 749 #define RT5677_IF3_ADC_IN_MASK (0xf << 0) 750 #define RT5677_IF3_ADC_IN_SFT 0 751 752 /* IF4 data control (0x30) */ 753 #define RT5677_IF4_ADC_IN_MASK (0xf << 4) 754 #define RT5677_IF4_ADC_IN_SFT 4 755 #define RT5677_IF4_DAC_SEL_MASK (0x3 << 2) 756 #define RT5677_IF4_DAC_SEL_SFT 2 757 #define RT5677_IF4_ADC_SEL_MASK (0x3 << 0) 758 #define RT5677_IF4_ADC_SEL_SFT 0 759 760 /* PDM Output Control (0x31) */ 761 #define RT5677_M_PDM1_L (0x1 << 15) 762 #define RT5677_M_PDM1_L_SFT 15 763 #define RT5677_SEL_PDM1_L_MASK (0x3 << 12) 764 #define RT5677_SEL_PDM1_L_SFT 12 765 #define RT5677_M_PDM1_R (0x1 << 11) 766 #define RT5677_M_PDM1_R_SFT 11 767 #define RT5677_SEL_PDM1_R_MASK (0x3 << 8) 768 #define RT5677_SEL_PDM1_R_SFT 8 769 #define RT5677_M_PDM2_L (0x1 << 7) 770 #define RT5677_M_PDM2_L_SFT 7 771 #define RT5677_SEL_PDM2_L_MASK (0x3 << 4) 772 #define RT5677_SEL_PDM2_L_SFT 4 773 #define RT5677_M_PDM2_R (0x1 << 3) 774 #define RT5677_M_PDM2_R_SFT 3 775 #define RT5677_SEL_PDM2_R_MASK (0x3 << 0) 776 #define RT5677_SEL_PDM2_R_SFT 0 777 778 /* PDM I2C / Data Control 1 (0x32) */ 779 #define RT5677_PDM2_PW_DOWN (0x1 << 7) 780 #define RT5677_PDM1_PW_DOWN (0x1 << 6) 781 #define RT5677_PDM2_BUSY (0x1 << 5) 782 #define RT5677_PDM1_BUSY (0x1 << 4) 783 #define RT5677_PDM_PATTERN (0x1 << 3) 784 #define RT5677_PDM_GAIN (0x1 << 2) 785 #define RT5677_PDM_DIV_MASK (0x3 << 0) 786 787 /* PDM I2C / Data Control 2 (0x33) */ 788 #define RT5677_PDM1_I2C_ID (0xf << 12) 789 #define RT5677_PDM1_EXE (0x1 << 11) 790 #define RT5677_PDM1_I2C_CMD (0x1 << 10) 791 #define RT5677_PDM1_I2C_EXE (0x1 << 9) 792 #define RT5677_PDM1_I2C_BUSY (0x1 << 8) 793 #define RT5677_PDM2_I2C_ID (0xf << 4) 794 #define RT5677_PDM2_EXE (0x1 << 3) 795 #define RT5677_PDM2_I2C_CMD (0x1 << 2) 796 #define RT5677_PDM2_I2C_EXE (0x1 << 1) 797 #define RT5677_PDM2_I2C_BUSY (0x1 << 0) 798 799 /* TDM1 control 1 (0x3b) */ 800 #define RT5677_IF1_ADC_MODE_MASK (0x1 << 12) 801 #define RT5677_IF1_ADC_MODE_SFT 12 802 #define RT5677_IF1_ADC_MODE_I2S (0x0 << 12) 803 #define RT5677_IF1_ADC_MODE_TDM (0x1 << 12) 804 #define RT5677_IF1_ADC1_SWAP_MASK (0x3 << 6) 805 #define RT5677_IF1_ADC1_SWAP_SFT 6 806 #define RT5677_IF1_ADC2_SWAP_MASK (0x3 << 4) 807 #define RT5677_IF1_ADC2_SWAP_SFT 4 808 #define RT5677_IF1_ADC3_SWAP_MASK (0x3 << 2) 809 #define RT5677_IF1_ADC3_SWAP_SFT 2 810 #define RT5677_IF1_ADC4_SWAP_MASK (0x3 << 0) 811 #define RT5677_IF1_ADC4_SWAP_SFT 0 812 813 /* TDM1 control 2 (0x3c) */ 814 #define RT5677_IF1_ADC4_MASK (0x3 << 10) 815 #define RT5677_IF1_ADC4_SFT 10 816 #define RT5677_IF1_ADC3_MASK (0x3 << 8) 817 #define RT5677_IF1_ADC3_SFT 8 818 #define RT5677_IF1_ADC2_MASK (0x3 << 6) 819 #define RT5677_IF1_ADC2_SFT 6 820 #define RT5677_IF1_ADC1_MASK (0x3 << 4) 821 #define RT5677_IF1_ADC1_SFT 4 822 #define RT5677_IF1_ADC_CTRL_MASK (0x7 << 0) 823 #define RT5677_IF1_ADC_CTRL_SFT 0 824 825 /* TDM1 control 4 (0x3e) */ 826 #define RT5677_IF1_DAC0_MASK (0x7 << 12) 827 #define RT5677_IF1_DAC0_SFT 12 828 #define RT5677_IF1_DAC1_MASK (0x7 << 8) 829 #define RT5677_IF1_DAC1_SFT 8 830 #define RT5677_IF1_DAC2_MASK (0x7 << 4) 831 #define RT5677_IF1_DAC2_SFT 4 832 #define RT5677_IF1_DAC3_MASK (0x7 << 0) 833 #define RT5677_IF1_DAC3_SFT 0 834 835 /* TDM1 control 5 (0x3f) */ 836 #define RT5677_IF1_DAC4_MASK (0x7 << 12) 837 #define RT5677_IF1_DAC4_SFT 12 838 #define RT5677_IF1_DAC5_MASK (0x7 << 8) 839 #define RT5677_IF1_DAC5_SFT 8 840 #define RT5677_IF1_DAC6_MASK (0x7 << 4) 841 #define RT5677_IF1_DAC6_SFT 4 842 #define RT5677_IF1_DAC7_MASK (0x7 << 0) 843 #define RT5677_IF1_DAC7_SFT 0 844 845 /* TDM2 control 1 (0x40) */ 846 #define RT5677_IF2_ADC_MODE_MASK (0x1 << 12) 847 #define RT5677_IF2_ADC_MODE_SFT 12 848 #define RT5677_IF2_ADC_MODE_I2S (0x0 << 12) 849 #define RT5677_IF2_ADC_MODE_TDM (0x1 << 12) 850 #define RT5677_IF2_ADC1_SWAP_MASK (0x3 << 6) 851 #define RT5677_IF2_ADC1_SWAP_SFT 6 852 #define RT5677_IF2_ADC2_SWAP_MASK (0x3 << 4) 853 #define RT5677_IF2_ADC2_SWAP_SFT 4 854 #define RT5677_IF2_ADC3_SWAP_MASK (0x3 << 2) 855 #define RT5677_IF2_ADC3_SWAP_SFT 2 856 #define RT5677_IF2_ADC4_SWAP_MASK (0x3 << 0) 857 #define RT5677_IF2_ADC4_SWAP_SFT 0 858 859 /* TDM2 control 2 (0x41) */ 860 #define RT5677_IF2_ADC4_MASK (0x3 << 10) 861 #define RT5677_IF2_ADC4_SFT 10 862 #define RT5677_IF2_ADC3_MASK (0x3 << 8) 863 #define RT5677_IF2_ADC3_SFT 8 864 #define RT5677_IF2_ADC2_MASK (0x3 << 6) 865 #define RT5677_IF2_ADC2_SFT 6 866 #define RT5677_IF2_ADC1_MASK (0x3 << 4) 867 #define RT5677_IF2_ADC1_SFT 4 868 #define RT5677_IF2_ADC_CTRL_MASK (0x7 << 0) 869 #define RT5677_IF2_ADC_CTRL_SFT 0 870 871 /* TDM2 control 4 (0x43) */ 872 #define RT5677_IF2_DAC0_MASK (0x7 << 12) 873 #define RT5677_IF2_DAC0_SFT 12 874 #define RT5677_IF2_DAC1_MASK (0x7 << 8) 875 #define RT5677_IF2_DAC1_SFT 8 876 #define RT5677_IF2_DAC2_MASK (0x7 << 4) 877 #define RT5677_IF2_DAC2_SFT 4 878 #define RT5677_IF2_DAC3_MASK (0x7 << 0) 879 #define RT5677_IF2_DAC3_SFT 0 880 881 /* TDM2 control 5 (0x44) */ 882 #define RT5677_IF2_DAC4_MASK (0x7 << 12) 883 #define RT5677_IF2_DAC4_SFT 12 884 #define RT5677_IF2_DAC5_MASK (0x7 << 8) 885 #define RT5677_IF2_DAC5_SFT 8 886 #define RT5677_IF2_DAC6_MASK (0x7 << 4) 887 #define RT5677_IF2_DAC6_SFT 4 888 #define RT5677_IF2_DAC7_MASK (0x7 << 0) 889 #define RT5677_IF2_DAC7_SFT 0 890 891 /* Digital Microphone Control 1 (0x50) */ 892 #define RT5677_DMIC_1_EN_MASK (0x1 << 15) 893 #define RT5677_DMIC_1_EN_SFT 15 894 #define RT5677_DMIC_1_DIS (0x0 << 15) 895 #define RT5677_DMIC_1_EN (0x1 << 15) 896 #define RT5677_DMIC_2_EN_MASK (0x1 << 14) 897 #define RT5677_DMIC_2_EN_SFT 14 898 #define RT5677_DMIC_2_DIS (0x0 << 14) 899 #define RT5677_DMIC_2_EN (0x1 << 14) 900 #define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13) 901 #define RT5677_DMIC_L_STO1_LH_SFT 13 902 #define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13) 903 #define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13) 904 #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12) 905 #define RT5677_DMIC_R_STO1_LH_SFT 12 906 #define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12) 907 #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12) 908 #define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11) 909 #define RT5677_DMIC_L_STO3_LH_SFT 11 910 #define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11) 911 #define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11) 912 #define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10) 913 #define RT5677_DMIC_R_STO3_LH_SFT 10 914 #define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10) 915 #define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10) 916 #define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9) 917 #define RT5677_DMIC_L_STO2_LH_SFT 9 918 #define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9) 919 #define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9) 920 #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8) 921 #define RT5677_DMIC_R_STO2_LH_SFT 8 922 #define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8) 923 #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8) 924 #define RT5677_DMIC_CLK_MASK (0x7 << 5) 925 #define RT5677_DMIC_CLK_SFT 5 926 #define RT5677_DMIC_3_EN_MASK (0x1 << 4) 927 #define RT5677_DMIC_3_EN_SFT 4 928 #define RT5677_DMIC_3_DIS (0x0 << 4) 929 #define RT5677_DMIC_3_EN (0x1 << 4) 930 #define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2) 931 #define RT5677_DMIC_R_MONO_LH_SFT 2 932 #define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2) 933 #define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2) 934 #define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1) 935 #define RT5677_DMIC_L_STO4_LH_SFT 1 936 #define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1) 937 #define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1) 938 #define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0) 939 #define RT5677_DMIC_R_STO4_LH_SFT 0 940 #define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0) 941 #define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0) 942 943 /* Digital Microphone Control 2 (0x51) */ 944 #define RT5677_DMIC_4_EN_MASK (0x1 << 15) 945 #define RT5677_DMIC_4_EN_SFT 15 946 #define RT5677_DMIC_4_DIS (0x0 << 15) 947 #define RT5677_DMIC_4_EN (0x1 << 15) 948 #define RT5677_DMIC_4L_LH_MASK (0x1 << 7) 949 #define RT5677_DMIC_4L_LH_SFT 7 950 #define RT5677_DMIC_4L_LH_FALLING (0x0 << 7) 951 #define RT5677_DMIC_4L_LH_RISING (0x1 << 7) 952 #define RT5677_DMIC_4R_LH_MASK (0x1 << 6) 953 #define RT5677_DMIC_4R_LH_SFT 6 954 #define RT5677_DMIC_4R_LH_FALLING (0x0 << 6) 955 #define RT5677_DMIC_4R_LH_RISING (0x1 << 6) 956 #define RT5677_DMIC_3L_LH_MASK (0x1 << 5) 957 #define RT5677_DMIC_3L_LH_SFT 5 958 #define RT5677_DMIC_3L_LH_FALLING (0x0 << 5) 959 #define RT5677_DMIC_3L_LH_RISING (0x1 << 5) 960 #define RT5677_DMIC_3R_LH_MASK (0x1 << 4) 961 #define RT5677_DMIC_3R_LH_SFT 4 962 #define RT5677_DMIC_3R_LH_FALLING (0x0 << 4) 963 #define RT5677_DMIC_3R_LH_RISING (0x1 << 4) 964 #define RT5677_DMIC_2L_LH_MASK (0x1 << 3) 965 #define RT5677_DMIC_2L_LH_SFT 3 966 #define RT5677_DMIC_2L_LH_FALLING (0x0 << 3) 967 #define RT5677_DMIC_2L_LH_RISING (0x1 << 3) 968 #define RT5677_DMIC_2R_LH_MASK (0x1 << 2) 969 #define RT5677_DMIC_2R_LH_SFT 2 970 #define RT5677_DMIC_2R_LH_FALLING (0x0 << 2) 971 #define RT5677_DMIC_2R_LH_RISING (0x1 << 2) 972 #define RT5677_DMIC_1L_LH_MASK (0x1 << 1) 973 #define RT5677_DMIC_1L_LH_SFT 1 974 #define RT5677_DMIC_1L_LH_FALLING (0x0 << 1) 975 #define RT5677_DMIC_1L_LH_RISING (0x1 << 1) 976 #define RT5677_DMIC_1R_LH_MASK (0x1 << 0) 977 #define RT5677_DMIC_1R_LH_SFT 0 978 #define RT5677_DMIC_1R_LH_FALLING (0x0 << 0) 979 #define RT5677_DMIC_1R_LH_RISING (0x1 << 0) 980 981 /* Power Management for Digital 1 (0x61) */ 982 #define RT5677_PWR_I2S1 (0x1 << 15) 983 #define RT5677_PWR_I2S1_BIT 15 984 #define RT5677_PWR_I2S2 (0x1 << 14) 985 #define RT5677_PWR_I2S2_BIT 14 986 #define RT5677_PWR_I2S3 (0x1 << 13) 987 #define RT5677_PWR_I2S3_BIT 13 988 #define RT5677_PWR_DAC1 (0x1 << 12) 989 #define RT5677_PWR_DAC1_BIT 12 990 #define RT5677_PWR_DAC2 (0x1 << 11) 991 #define RT5677_PWR_DAC2_BIT 11 992 #define RT5677_PWR_I2S4 (0x1 << 10) 993 #define RT5677_PWR_I2S4_BIT 10 994 #define RT5677_PWR_SLB (0x1 << 9) 995 #define RT5677_PWR_SLB_BIT 9 996 #define RT5677_PWR_DAC3 (0x1 << 7) 997 #define RT5677_PWR_DAC3_BIT 7 998 #define RT5677_PWR_ADCFED2 (0x1 << 4) 999 #define RT5677_PWR_ADCFED2_BIT 4 1000 #define RT5677_PWR_ADCFED1 (0x1 << 3) 1001 #define RT5677_PWR_ADCFED1_BIT 3 1002 #define RT5677_PWR_ADC_L (0x1 << 2) 1003 #define RT5677_PWR_ADC_L_BIT 2 1004 #define RT5677_PWR_ADC_R (0x1 << 1) 1005 #define RT5677_PWR_ADC_R_BIT 1 1006 #define RT5677_PWR_I2C_MASTER (0x1 << 0) 1007 #define RT5677_PWR_I2C_MASTER_BIT 0 1008 1009 /* Power Management for Digital 2 (0x62) */ 1010 #define RT5677_PWR_ADC_S1F (0x1 << 15) 1011 #define RT5677_PWR_ADC_S1F_BIT 15 1012 #define RT5677_PWR_ADC_MF_L (0x1 << 14) 1013 #define RT5677_PWR_ADC_MF_L_BIT 14 1014 #define RT5677_PWR_ADC_MF_R (0x1 << 13) 1015 #define RT5677_PWR_ADC_MF_R_BIT 13 1016 #define RT5677_PWR_DAC_S1F (0x1 << 12) 1017 #define RT5677_PWR_DAC_S1F_BIT 12 1018 #define RT5677_PWR_DAC_M2F_L (0x1 << 11) 1019 #define RT5677_PWR_DAC_M2F_L_BIT 11 1020 #define RT5677_PWR_DAC_M2F_R (0x1 << 10) 1021 #define RT5677_PWR_DAC_M2F_R_BIT 10 1022 #define RT5677_PWR_DAC_M3F_L (0x1 << 9) 1023 #define RT5677_PWR_DAC_M3F_L_BIT 9 1024 #define RT5677_PWR_DAC_M3F_R (0x1 << 8) 1025 #define RT5677_PWR_DAC_M3F_R_BIT 8 1026 #define RT5677_PWR_DAC_M4F_L (0x1 << 7) 1027 #define RT5677_PWR_DAC_M4F_L_BIT 7 1028 #define RT5677_PWR_DAC_M4F_R (0x1 << 6) 1029 #define RT5677_PWR_DAC_M4F_R_BIT 6 1030 #define RT5677_PWR_ADC_S2F (0x1 << 5) 1031 #define RT5677_PWR_ADC_S2F_BIT 5 1032 #define RT5677_PWR_ADC_S3F (0x1 << 4) 1033 #define RT5677_PWR_ADC_S3F_BIT 4 1034 #define RT5677_PWR_ADC_S4F (0x1 << 3) 1035 #define RT5677_PWR_ADC_S4F_BIT 3 1036 #define RT5677_PWR_PDM1 (0x1 << 2) 1037 #define RT5677_PWR_PDM1_BIT 2 1038 #define RT5677_PWR_PDM2 (0x1 << 1) 1039 #define RT5677_PWR_PDM2_BIT 1 1040 1041 /* Power Management for Analog 1 (0x63) */ 1042 #define RT5677_PWR_VREF1 (0x1 << 15) 1043 #define RT5677_PWR_VREF1_BIT 15 1044 #define RT5677_PWR_FV1 (0x1 << 14) 1045 #define RT5677_PWR_FV1_BIT 14 1046 #define RT5677_PWR_MB (0x1 << 13) 1047 #define RT5677_PWR_MB_BIT 13 1048 #define RT5677_PWR_LO1 (0x1 << 12) 1049 #define RT5677_PWR_LO1_BIT 12 1050 #define RT5677_PWR_BG (0x1 << 11) 1051 #define RT5677_PWR_BG_BIT 11 1052 #define RT5677_PWR_LO2 (0x1 << 10) 1053 #define RT5677_PWR_LO2_BIT 10 1054 #define RT5677_PWR_LO3 (0x1 << 9) 1055 #define RT5677_PWR_LO3_BIT 9 1056 #define RT5677_PWR_VREF2 (0x1 << 8) 1057 #define RT5677_PWR_VREF2_BIT 8 1058 #define RT5677_PWR_FV2 (0x1 << 7) 1059 #define RT5677_PWR_FV2_BIT 7 1060 #define RT5677_LDO2_SEL_MASK (0x7 << 4) 1061 #define RT5677_LDO2_SEL_SFT 4 1062 #define RT5677_LDO1_SEL_MASK (0x7 << 0) 1063 #define RT5677_LDO1_SEL_SFT 0 1064 1065 /* Power Management for Analog 2 (0x64) */ 1066 #define RT5677_PWR_BST1 (0x1 << 15) 1067 #define RT5677_PWR_BST1_BIT 15 1068 #define RT5677_PWR_BST2 (0x1 << 14) 1069 #define RT5677_PWR_BST2_BIT 14 1070 #define RT5677_PWR_CLK_MB1 (0x1 << 13) 1071 #define RT5677_PWR_CLK_MB1_BIT 13 1072 #define RT5677_PWR_SLIM (0x1 << 12) 1073 #define RT5677_PWR_SLIM_BIT 12 1074 #define RT5677_PWR_MB1 (0x1 << 11) 1075 #define RT5677_PWR_MB1_BIT 11 1076 #define RT5677_PWR_PP_MB1 (0x1 << 10) 1077 #define RT5677_PWR_PP_MB1_BIT 10 1078 #define RT5677_PWR_PLL1 (0x1 << 9) 1079 #define RT5677_PWR_PLL1_BIT 9 1080 #define RT5677_PWR_PLL2 (0x1 << 8) 1081 #define RT5677_PWR_PLL2_BIT 8 1082 #define RT5677_PWR_CORE (0x1 << 7) 1083 #define RT5677_PWR_CORE_BIT 7 1084 #define RT5677_PWR_CLK_MB (0x1 << 6) 1085 #define RT5677_PWR_CLK_MB_BIT 6 1086 #define RT5677_PWR_BST1_P (0x1 << 5) 1087 #define RT5677_PWR_BST1_P_BIT 5 1088 #define RT5677_PWR_BST2_P (0x1 << 4) 1089 #define RT5677_PWR_BST2_P_BIT 4 1090 #define RT5677_PWR_IPTV (0x1 << 3) 1091 #define RT5677_PWR_IPTV_BIT 3 1092 #define RT5677_PWR_25M_CLK (0x1 << 1) 1093 #define RT5677_PWR_25M_CLK_BIT 1 1094 #define RT5677_PWR_LDO1 (0x1 << 0) 1095 #define RT5677_PWR_LDO1_BIT 0 1096 1097 /* Power Management for DSP (0x65) */ 1098 #define RT5677_PWR_SR7 (0x1 << 10) 1099 #define RT5677_PWR_SR7_BIT 10 1100 #define RT5677_PWR_SR6 (0x1 << 9) 1101 #define RT5677_PWR_SR6_BIT 9 1102 #define RT5677_PWR_SR5 (0x1 << 8) 1103 #define RT5677_PWR_SR5_BIT 8 1104 #define RT5677_PWR_SR4 (0x1 << 7) 1105 #define RT5677_PWR_SR4_BIT 7 1106 #define RT5677_PWR_SR3 (0x1 << 6) 1107 #define RT5677_PWR_SR3_BIT 6 1108 #define RT5677_PWR_SR2 (0x1 << 5) 1109 #define RT5677_PWR_SR2_BIT 5 1110 #define RT5677_PWR_SR1 (0x1 << 4) 1111 #define RT5677_PWR_SR1_BIT 4 1112 #define RT5677_PWR_SR0 (0x1 << 3) 1113 #define RT5677_PWR_SR0_BIT 3 1114 #define RT5677_PWR_MLT (0x1 << 2) 1115 #define RT5677_PWR_MLT_BIT 2 1116 #define RT5677_PWR_DSP (0x1 << 1) 1117 #define RT5677_PWR_DSP_BIT 1 1118 #define RT5677_PWR_DSP_CPU (0x1 << 0) 1119 #define RT5677_PWR_DSP_CPU_BIT 0 1120 1121 /* Power Status for DSP (0x66) */ 1122 #define RT5677_PWR_SR7_RDY (0x1 << 9) 1123 #define RT5677_PWR_SR7_RDY_BIT 9 1124 #define RT5677_PWR_SR6_RDY (0x1 << 8) 1125 #define RT5677_PWR_SR6_RDY_BIT 8 1126 #define RT5677_PWR_SR5_RDY (0x1 << 7) 1127 #define RT5677_PWR_SR5_RDY_BIT 7 1128 #define RT5677_PWR_SR4_RDY (0x1 << 6) 1129 #define RT5677_PWR_SR4_RDY_BIT 6 1130 #define RT5677_PWR_SR3_RDY (0x1 << 5) 1131 #define RT5677_PWR_SR3_RDY_BIT 5 1132 #define RT5677_PWR_SR2_RDY (0x1 << 4) 1133 #define RT5677_PWR_SR2_RDY_BIT 4 1134 #define RT5677_PWR_SR1_RDY (0x1 << 3) 1135 #define RT5677_PWR_SR1_RDY_BIT 3 1136 #define RT5677_PWR_SR0_RDY (0x1 << 2) 1137 #define RT5677_PWR_SR0_RDY_BIT 2 1138 #define RT5677_PWR_MLT_RDY (0x1 << 1) 1139 #define RT5677_PWR_MLT_RDY_BIT 1 1140 #define RT5677_PWR_DSP_RDY (0x1 << 0) 1141 #define RT5677_PWR_DSP_RDY_BIT 0 1142 1143 /* Power Management for DSP (0x67) */ 1144 #define RT5677_PWR_SLIM_ISO (0x1 << 11) 1145 #define RT5677_PWR_SLIM_ISO_BIT 11 1146 #define RT5677_PWR_CORE_ISO (0x1 << 10) 1147 #define RT5677_PWR_CORE_ISO_BIT 10 1148 #define RT5677_PWR_DSP_ISO (0x1 << 9) 1149 #define RT5677_PWR_DSP_ISO_BIT 9 1150 #define RT5677_PWR_SR7_ISO (0x1 << 8) 1151 #define RT5677_PWR_SR7_ISO_BIT 8 1152 #define RT5677_PWR_SR6_ISO (0x1 << 7) 1153 #define RT5677_PWR_SR6_ISO_BIT 7 1154 #define RT5677_PWR_SR5_ISO (0x1 << 6) 1155 #define RT5677_PWR_SR5_ISO_BIT 6 1156 #define RT5677_PWR_SR4_ISO (0x1 << 5) 1157 #define RT5677_PWR_SR4_ISO_BIT 5 1158 #define RT5677_PWR_SR3_ISO (0x1 << 4) 1159 #define RT5677_PWR_SR3_ISO_BIT 4 1160 #define RT5677_PWR_SR2_ISO (0x1 << 3) 1161 #define RT5677_PWR_SR2_ISO_BIT 3 1162 #define RT5677_PWR_SR1_ISO (0x1 << 2) 1163 #define RT5677_PWR_SR1_ISO_BIT 2 1164 #define RT5677_PWR_SR0_ISO (0x1 << 1) 1165 #define RT5677_PWR_SR0_ISO_BIT 1 1166 #define RT5677_PWR_MLT_ISO (0x1 << 0) 1167 #define RT5677_PWR_MLT_ISO_BIT 0 1168 1169 /* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */ 1170 #define RT5677_I2S_MS_MASK (0x1 << 15) 1171 #define RT5677_I2S_MS_SFT 15 1172 #define RT5677_I2S_MS_M (0x0 << 15) 1173 #define RT5677_I2S_MS_S (0x1 << 15) 1174 #define RT5677_I2S_O_CP_MASK (0x3 << 10) 1175 #define RT5677_I2S_O_CP_SFT 10 1176 #define RT5677_I2S_O_CP_OFF (0x0 << 10) 1177 #define RT5677_I2S_O_CP_U_LAW (0x1 << 10) 1178 #define RT5677_I2S_O_CP_A_LAW (0x2 << 10) 1179 #define RT5677_I2S_I_CP_MASK (0x3 << 8) 1180 #define RT5677_I2S_I_CP_SFT 8 1181 #define RT5677_I2S_I_CP_OFF (0x0 << 8) 1182 #define RT5677_I2S_I_CP_U_LAW (0x1 << 8) 1183 #define RT5677_I2S_I_CP_A_LAW (0x2 << 8) 1184 #define RT5677_I2S_BP_MASK (0x1 << 7) 1185 #define RT5677_I2S_BP_SFT 7 1186 #define RT5677_I2S_BP_NOR (0x0 << 7) 1187 #define RT5677_I2S_BP_INV (0x1 << 7) 1188 #define RT5677_I2S_DL_MASK (0x3 << 2) 1189 #define RT5677_I2S_DL_SFT 2 1190 #define RT5677_I2S_DL_16 (0x0 << 2) 1191 #define RT5677_I2S_DL_20 (0x1 << 2) 1192 #define RT5677_I2S_DL_24 (0x2 << 2) 1193 #define RT5677_I2S_DL_8 (0x3 << 2) 1194 #define RT5677_I2S_DF_MASK (0x3 << 0) 1195 #define RT5677_I2S_DF_SFT 0 1196 #define RT5677_I2S_DF_I2S (0x0 << 0) 1197 #define RT5677_I2S_DF_LEFT (0x1 << 0) 1198 #define RT5677_I2S_DF_PCM_A (0x2 << 0) 1199 #define RT5677_I2S_DF_PCM_B (0x3 << 0) 1200 1201 /* Clock Tree Control 1 (0x73) */ 1202 #define RT5677_I2S_PD1_MASK (0x7 << 12) 1203 #define RT5677_I2S_PD1_SFT 12 1204 #define RT5677_I2S_PD1_1 (0x0 << 12) 1205 #define RT5677_I2S_PD1_2 (0x1 << 12) 1206 #define RT5677_I2S_PD1_3 (0x2 << 12) 1207 #define RT5677_I2S_PD1_4 (0x3 << 12) 1208 #define RT5677_I2S_PD1_6 (0x4 << 12) 1209 #define RT5677_I2S_PD1_8 (0x5 << 12) 1210 #define RT5677_I2S_PD1_12 (0x6 << 12) 1211 #define RT5677_I2S_PD1_16 (0x7 << 12) 1212 #define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11) 1213 #define RT5677_I2S_BCLK_MS2_SFT 11 1214 #define RT5677_I2S_BCLK_MS2_32 (0x0 << 11) 1215 #define RT5677_I2S_BCLK_MS2_64 (0x1 << 11) 1216 #define RT5677_I2S_PD2_MASK (0x7 << 8) 1217 #define RT5677_I2S_PD2_SFT 8 1218 #define RT5677_I2S_PD2_1 (0x0 << 8) 1219 #define RT5677_I2S_PD2_2 (0x1 << 8) 1220 #define RT5677_I2S_PD2_3 (0x2 << 8) 1221 #define RT5677_I2S_PD2_4 (0x3 << 8) 1222 #define RT5677_I2S_PD2_6 (0x4 << 8) 1223 #define RT5677_I2S_PD2_8 (0x5 << 8) 1224 #define RT5677_I2S_PD2_12 (0x6 << 8) 1225 #define RT5677_I2S_PD2_16 (0x7 << 8) 1226 #define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7) 1227 #define RT5677_I2S_BCLK_MS3_SFT 7 1228 #define RT5677_I2S_BCLK_MS3_32 (0x0 << 7) 1229 #define RT5677_I2S_BCLK_MS3_64 (0x1 << 7) 1230 #define RT5677_I2S_PD3_MASK (0x7 << 4) 1231 #define RT5677_I2S_PD3_SFT 4 1232 #define RT5677_I2S_PD3_1 (0x0 << 4) 1233 #define RT5677_I2S_PD3_2 (0x1 << 4) 1234 #define RT5677_I2S_PD3_3 (0x2 << 4) 1235 #define RT5677_I2S_PD3_4 (0x3 << 4) 1236 #define RT5677_I2S_PD3_6 (0x4 << 4) 1237 #define RT5677_I2S_PD3_8 (0x5 << 4) 1238 #define RT5677_I2S_PD3_12 (0x6 << 4) 1239 #define RT5677_I2S_PD3_16 (0x7 << 4) 1240 #define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3) 1241 #define RT5677_I2S_BCLK_MS4_SFT 3 1242 #define RT5677_I2S_BCLK_MS4_32 (0x0 << 3) 1243 #define RT5677_I2S_BCLK_MS4_64 (0x1 << 3) 1244 #define RT5677_I2S_PD4_MASK (0x7 << 0) 1245 #define RT5677_I2S_PD4_SFT 0 1246 #define RT5677_I2S_PD4_1 (0x0 << 0) 1247 #define RT5677_I2S_PD4_2 (0x1 << 0) 1248 #define RT5677_I2S_PD4_3 (0x2 << 0) 1249 #define RT5677_I2S_PD4_4 (0x3 << 0) 1250 #define RT5677_I2S_PD4_6 (0x4 << 0) 1251 #define RT5677_I2S_PD4_8 (0x5 << 0) 1252 #define RT5677_I2S_PD4_12 (0x6 << 0) 1253 #define RT5677_I2S_PD4_16 (0x7 << 0) 1254 1255 /* Clock Tree Control 2 (0x74) */ 1256 #define RT5677_I2S_PD5_MASK (0x7 << 12) 1257 #define RT5677_I2S_PD5_SFT 12 1258 #define RT5677_I2S_PD5_1 (0x0 << 12) 1259 #define RT5677_I2S_PD5_2 (0x1 << 12) 1260 #define RT5677_I2S_PD5_3 (0x2 << 12) 1261 #define RT5677_I2S_PD5_4 (0x3 << 12) 1262 #define RT5677_I2S_PD5_6 (0x4 << 12) 1263 #define RT5677_I2S_PD5_8 (0x5 << 12) 1264 #define RT5677_I2S_PD5_12 (0x6 << 12) 1265 #define RT5677_I2S_PD5_16 (0x7 << 12) 1266 #define RT5677_I2S_PD6_MASK (0x7 << 8) 1267 #define RT5677_I2S_PD6_SFT 8 1268 #define RT5677_I2S_PD6_1 (0x0 << 8) 1269 #define RT5677_I2S_PD6_2 (0x1 << 8) 1270 #define RT5677_I2S_PD6_3 (0x2 << 8) 1271 #define RT5677_I2S_PD6_4 (0x3 << 8) 1272 #define RT5677_I2S_PD6_6 (0x4 << 8) 1273 #define RT5677_I2S_PD6_8 (0x5 << 8) 1274 #define RT5677_I2S_PD6_12 (0x6 << 8) 1275 #define RT5677_I2S_PD6_16 (0x7 << 8) 1276 #define RT5677_I2S_PD7_MASK (0x7 << 4) 1277 #define RT5677_I2S_PD7_SFT 4 1278 #define RT5677_I2S_PD7_1 (0x0 << 4) 1279 #define RT5677_I2S_PD7_2 (0x1 << 4) 1280 #define RT5677_I2S_PD7_3 (0x2 << 4) 1281 #define RT5677_I2S_PD7_4 (0x3 << 4) 1282 #define RT5677_I2S_PD7_6 (0x4 << 4) 1283 #define RT5677_I2S_PD7_8 (0x5 << 4) 1284 #define RT5677_I2S_PD7_12 (0x6 << 4) 1285 #define RT5677_I2S_PD7_16 (0x7 << 4) 1286 #define RT5677_I2S_PD8_MASK (0x7 << 0) 1287 #define RT5677_I2S_PD8_SFT 0 1288 #define RT5677_I2S_PD8_1 (0x0 << 0) 1289 #define RT5677_I2S_PD8_2 (0x1 << 0) 1290 #define RT5677_I2S_PD8_3 (0x2 << 0) 1291 #define RT5677_I2S_PD8_4 (0x3 << 0) 1292 #define RT5677_I2S_PD8_6 (0x4 << 0) 1293 #define RT5677_I2S_PD8_8 (0x5 << 0) 1294 #define RT5677_I2S_PD8_12 (0x6 << 0) 1295 #define RT5677_I2S_PD8_16 (0x7 << 0) 1296 1297 /* Clock Tree Control 3 (0x75) */ 1298 #define RT5677_DSP_ASRC_O_MASK (0x3 << 6) 1299 #define RT5677_DSP_ASRC_O_SFT 6 1300 #define RT5677_DSP_ASRC_O_1_0 (0x0 << 6) 1301 #define RT5677_DSP_ASRC_O_1_5 (0x1 << 6) 1302 #define RT5677_DSP_ASRC_O_2_0 (0x2 << 6) 1303 #define RT5677_DSP_ASRC_O_3_0 (0x3 << 6) 1304 #define RT5677_DSP_ASRC_I_MASK (0x3 << 4) 1305 #define RT5677_DSP_ASRC_I_SFT 4 1306 #define RT5677_DSP_ASRC_I_1_0 (0x0 << 4) 1307 #define RT5677_DSP_ASRC_I_1_5 (0x1 << 4) 1308 #define RT5677_DSP_ASRC_I_2_0 (0x2 << 4) 1309 #define RT5677_DSP_ASRC_I_3_0 (0x3 << 4) 1310 #define RT5677_DSP_BUS_PD_MASK (0x7 << 0) 1311 #define RT5677_DSP_BUS_PD_SFT 0 1312 #define RT5677_DSP_BUS_PD_1 (0x0 << 0) 1313 #define RT5677_DSP_BUS_PD_2 (0x1 << 0) 1314 #define RT5677_DSP_BUS_PD_3 (0x2 << 0) 1315 #define RT5677_DSP_BUS_PD_4 (0x3 << 0) 1316 #define RT5677_DSP_BUS_PD_6 (0x4 << 0) 1317 #define RT5677_DSP_BUS_PD_8 (0x5 << 0) 1318 #define RT5677_DSP_BUS_PD_12 (0x6 << 0) 1319 #define RT5677_DSP_BUS_PD_16 (0x7 << 0) 1320 1321 #define RT5677_PLL_INP_MAX 40000000 1322 #define RT5677_PLL_INP_MIN 2048000 1323 /* PLL M/N/K Code Control 1 (0x7a 0x7c) */ 1324 #define RT5677_PLL_N_MAX 0x1ff 1325 #define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7) 1326 #define RT5677_PLL_N_SFT 7 1327 #define RT5677_PLL_K_BP (0x1 << 5) 1328 #define RT5677_PLL_K_BP_SFT 5 1329 #define RT5677_PLL_K_MAX 0x1f 1330 #define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX) 1331 #define RT5677_PLL_K_SFT 0 1332 1333 /* PLL M/N/K Code Control 2 (0x7b 0x7d) */ 1334 #define RT5677_PLL_M_MAX 0xf 1335 #define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12) 1336 #define RT5677_PLL_M_SFT 12 1337 #define RT5677_PLL_M_BP (0x1 << 11) 1338 #define RT5677_PLL_M_BP_SFT 11 1339 1340 /* Global Clock Control 1 (0x80) */ 1341 #define RT5677_SCLK_SRC_MASK (0x3 << 14) 1342 #define RT5677_SCLK_SRC_SFT 14 1343 #define RT5677_SCLK_SRC_MCLK (0x0 << 14) 1344 #define RT5677_SCLK_SRC_PLL1 (0x1 << 14) 1345 #define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */ 1346 #define RT5677_SCLK_SRC_SLIM (0x3 << 14) 1347 #define RT5677_PLL1_SRC_MASK (0x7 << 11) 1348 #define RT5677_PLL1_SRC_SFT 11 1349 #define RT5677_PLL1_SRC_MCLK (0x0 << 11) 1350 #define RT5677_PLL1_SRC_BCLK1 (0x1 << 11) 1351 #define RT5677_PLL1_SRC_BCLK2 (0x2 << 11) 1352 #define RT5677_PLL1_SRC_BCLK3 (0x3 << 11) 1353 #define RT5677_PLL1_SRC_BCLK4 (0x4 << 11) 1354 #define RT5677_PLL1_SRC_RCCLK (0x5 << 11) 1355 #define RT5677_PLL1_SRC_SLIM (0x6 << 11) 1356 #define RT5677_MCLK_SRC_MASK (0x1 << 10) 1357 #define RT5677_MCLK_SRC_SFT 10 1358 #define RT5677_MCLK1_SRC (0x0 << 10) 1359 #define RT5677_MCLK2_SRC (0x1 << 10) 1360 #define RT5677_PLL1_PD_MASK (0x1 << 8) 1361 #define RT5677_PLL1_PD_SFT 8 1362 #define RT5677_PLL1_PD_1 (0x0 << 8) 1363 #define RT5677_PLL1_PD_2 (0x1 << 8) 1364 #define RT5677_DAC_OSR_MASK (0x3 << 6) 1365 #define RT5677_DAC_OSR_SFT 6 1366 #define RT5677_DAC_OSR_128 (0x0 << 6) 1367 #define RT5677_DAC_OSR_64 (0x1 << 6) 1368 #define RT5677_DAC_OSR_32 (0x2 << 6) 1369 #define RT5677_ADC_OSR_MASK (0x3 << 4) 1370 #define RT5677_ADC_OSR_SFT 4 1371 #define RT5677_ADC_OSR_128 (0x0 << 4) 1372 #define RT5677_ADC_OSR_64 (0x1 << 4) 1373 #define RT5677_ADC_OSR_32 (0x2 << 4) 1374 1375 /* Global Clock Control 2 (0x81) */ 1376 #define RT5677_PLL2_PR_SRC_MASK (0x1 << 15) 1377 #define RT5677_PLL2_PR_SRC_SFT 15 1378 #define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15) 1379 #define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15) 1380 #define RT5677_PLL2_SRC_MASK (0x7 << 12) 1381 #define RT5677_PLL2_SRC_SFT 12 1382 #define RT5677_PLL2_SRC_MCLK (0x0 << 12) 1383 #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12) 1384 #define RT5677_PLL2_SRC_BCLK2 (0x2 << 12) 1385 #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12) 1386 #define RT5677_PLL2_SRC_BCLK4 (0x4 << 12) 1387 #define RT5677_PLL2_SRC_RCCLK (0x5 << 12) 1388 #define RT5677_PLL2_SRC_SLIM (0x6 << 12) 1389 #define RT5677_DSP_ASRC_O_SRC (0x3 << 10) 1390 #define RT5677_DSP_ASRC_O_SRC_SFT 10 1391 #define RT5677_DSP_ASRC_O_MCLK (0x0 << 10) 1392 #define RT5677_DSP_ASRC_O_PLL1 (0x1 << 10) 1393 #define RT5677_DSP_ASRC_O_SLIM (0x2 << 10) 1394 #define RT5677_DSP_ASRC_O_RCCLK (0x3 << 10) 1395 #define RT5677_DSP_ASRC_I_SRC (0x3 << 8) 1396 #define RT5677_DSP_ASRC_I_SRC_SFT 8 1397 #define RT5677_DSP_ASRC_I_MCLK (0x0 << 8) 1398 #define RT5677_DSP_ASRC_I_PLL1 (0x1 << 8) 1399 #define RT5677_DSP_ASRC_I_SLIM (0x2 << 8) 1400 #define RT5677_DSP_ASRC_I_RCCLK (0x3 << 8) 1401 #define RT5677_DSP_CLK_SRC_MASK (0x1 << 7) 1402 #define RT5677_DSP_CLK_SRC_SFT 7 1403 #define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7) 1404 #define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7) 1405 1406 /* ASRC Control 3 (0x85) */ 1407 #define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12) 1408 #define RT5677_DA_STO_CLK_SEL_SFT 12 1409 #define RT5677_DA_MONO2L_CLK_SEL_MASK (0xf << 4) 1410 #define RT5677_DA_MONO2L_CLK_SEL_SFT 4 1411 #define RT5677_DA_MONO2R_CLK_SEL_MASK (0xf << 0) 1412 #define RT5677_DA_MONO2R_CLK_SEL_SFT 0 1413 1414 /* ASRC Control 4 (0x86) */ 1415 #define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12) 1416 #define RT5677_DA_MONO3L_CLK_SEL_SFT 12 1417 #define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8) 1418 #define RT5677_DA_MONO3R_CLK_SEL_SFT 8 1419 #define RT5677_DA_MONO4L_CLK_SEL_MASK (0xf << 4) 1420 #define RT5677_DA_MONO4L_CLK_SEL_SFT 4 1421 #define RT5677_DA_MONO4R_CLK_SEL_MASK (0xf << 0) 1422 #define RT5677_DA_MONO4R_CLK_SEL_SFT 0 1423 1424 /* ASRC Control 5 (0x87) */ 1425 #define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12) 1426 #define RT5677_AD_STO1_CLK_SEL_SFT 12 1427 #define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8) 1428 #define RT5677_AD_STO2_CLK_SEL_SFT 8 1429 #define RT5677_AD_STO3_CLK_SEL_MASK (0xf << 4) 1430 #define RT5677_AD_STO3_CLK_SEL_SFT 4 1431 #define RT5677_AD_STO4_CLK_SEL_MASK (0xf << 0) 1432 #define RT5677_AD_STO4_CLK_SEL_SFT 0 1433 1434 /* ASRC Control 6 (0x88) */ 1435 #define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12) 1436 #define RT5677_AD_MONOL_CLK_SEL_SFT 12 1437 #define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8) 1438 #define RT5677_AD_MONOR_CLK_SEL_SFT 8 1439 1440 /* ASRC Control 7 (0x89) */ 1441 #define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12) 1442 #define RT5677_DSP_OB_0_3_CLK_SEL_SFT 12 1443 #define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8) 1444 #define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8 1445 1446 /* ASRC Control 8 (0x8a) */ 1447 #define RT5677_I2S1_CLK_SEL_MASK (0xf << 12) 1448 #define RT5677_I2S1_CLK_SEL_SFT 12 1449 #define RT5677_I2S2_CLK_SEL_MASK (0xf << 8) 1450 #define RT5677_I2S2_CLK_SEL_SFT 8 1451 #define RT5677_I2S3_CLK_SEL_MASK (0xf << 4) 1452 #define RT5677_I2S3_CLK_SEL_SFT 4 1453 #define RT5677_I2S4_CLK_SEL_MASK (0xf) 1454 #define RT5677_I2S4_CLK_SEL_SFT 0 1455 1456 /* VAD Function Control 1 (0x9c) */ 1457 #define RT5677_VAD_MIN_DUR_MASK (0x3 << 13) 1458 #define RT5677_VAD_MIN_DUR_SFT 13 1459 #define RT5677_VAD_ADPCM_BYPASS (1 << 10) 1460 #define RT5677_VAD_ADPCM_BYPASS_BIT 10 1461 #define RT5677_VAD_FG2ENC (1 << 9) 1462 #define RT5677_VAD_FG2ENC_BIT 9 1463 #define RT5677_VAD_BUF_OW (1 << 8) 1464 #define RT5677_VAD_BUF_OW_BIT 8 1465 #define RT5677_VAD_CLR_FLAG (1 << 7) 1466 #define RT5677_VAD_CLR_FLAG_BIT 7 1467 #define RT5677_VAD_BUF_POP (1 << 6) 1468 #define RT5677_VAD_BUF_POP_BIT 6 1469 #define RT5677_VAD_BUF_PUSH (1 << 5) 1470 #define RT5677_VAD_BUF_PUSH_BIT 5 1471 #define RT5677_VAD_DET_ENABLE (1 << 4) 1472 #define RT5677_VAD_DET_ENABLE_BIT 4 1473 #define RT5677_VAD_FUNC_ENABLE (1 << 3) 1474 #define RT5677_VAD_FUNC_ENABLE_BIT 3 1475 #define RT5677_VAD_FUNC_RESET (1 << 2) 1476 #define RT5677_VAD_FUNC_RESET_BIT 2 1477 1478 /* VAD Function Control 4 (0x9f) */ 1479 #define RT5677_VAD_OUT_SRC_RATE_MASK (0x1 << 11) 1480 #define RT5677_VAD_OUT_SRC_RATE_SFT 11 1481 #define RT5677_VAD_OUT_SRC_MASK (0x1 << 10) 1482 #define RT5677_VAD_OUT_SRC_SFT 10 1483 #define RT5677_VAD_SRC_MASK (0x3 << 8) 1484 #define RT5677_VAD_SRC_SFT 8 1485 #define RT5677_VAD_LV_DIFF_MASK (0xff << 0) 1486 #define RT5677_VAD_LV_DIFF_SFT 0 1487 1488 /* DSP InBound Control (0xa3) */ 1489 #define RT5677_IB01_SRC_MASK (0x7 << 12) 1490 #define RT5677_IB01_SRC_SFT 12 1491 #define RT5677_IB23_SRC_MASK (0x7 << 8) 1492 #define RT5677_IB23_SRC_SFT 8 1493 #define RT5677_IB45_SRC_MASK (0x7 << 4) 1494 #define RT5677_IB45_SRC_SFT 4 1495 #define RT5677_IB6_SRC_MASK (0x7 << 0) 1496 #define RT5677_IB6_SRC_SFT 0 1497 1498 /* DSP InBound Control (0xa4) */ 1499 #define RT5677_IB7_SRC_MASK (0x7 << 12) 1500 #define RT5677_IB7_SRC_SFT 12 1501 #define RT5677_IB8_SRC_MASK (0x7 << 8) 1502 #define RT5677_IB8_SRC_SFT 8 1503 #define RT5677_IB9_SRC_MASK (0x7 << 4) 1504 #define RT5677_IB9_SRC_SFT 4 1505 1506 /* DSP In/OutBound Control (0xa5) */ 1507 #define RT5677_SEL_SRC_OB23 (0x1 << 4) 1508 #define RT5677_SEL_SRC_OB23_SFT 4 1509 #define RT5677_SEL_SRC_OB01 (0x1 << 3) 1510 #define RT5677_SEL_SRC_OB01_SFT 3 1511 #define RT5677_SEL_SRC_IB45 (0x1 << 2) 1512 #define RT5677_SEL_SRC_IB45_SFT 2 1513 #define RT5677_SEL_SRC_IB23 (0x1 << 1) 1514 #define RT5677_SEL_SRC_IB23_SFT 1 1515 #define RT5677_SEL_SRC_IB01 (0x1 << 0) 1516 #define RT5677_SEL_SRC_IB01_SFT 0 1517 1518 /* Jack Detect Control 1 (0xb5) */ 1519 #define RT5677_SEL_GPIO_JD1_MASK (0x3 << 14) 1520 #define RT5677_SEL_GPIO_JD1_SFT 14 1521 #define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12) 1522 #define RT5677_SEL_GPIO_JD2_SFT 12 1523 #define RT5677_SEL_GPIO_JD3_MASK (0x3 << 10) 1524 #define RT5677_SEL_GPIO_JD3_SFT 10 1525 1526 /* IRQ Control 1 (0xbd) */ 1527 #define RT5677_STA_GPIO_JD1 (0x1 << 15) 1528 #define RT5677_STA_GPIO_JD1_SFT 15 1529 #define RT5677_EN_IRQ_GPIO_JD1 (0x1 << 14) 1530 #define RT5677_EN_IRQ_GPIO_JD1_SFT 14 1531 #define RT5677_EN_GPIO_JD1_STICKY (0x1 << 13) 1532 #define RT5677_EN_GPIO_JD1_STICKY_SFT 13 1533 #define RT5677_INV_GPIO_JD1 (0x1 << 12) 1534 #define RT5677_INV_GPIO_JD1_SFT 12 1535 #define RT5677_STA_GPIO_JD2 (0x1 << 11) 1536 #define RT5677_STA_GPIO_JD2_SFT 11 1537 #define RT5677_EN_IRQ_GPIO_JD2 (0x1 << 10) 1538 #define RT5677_EN_IRQ_GPIO_JD2_SFT 10 1539 #define RT5677_EN_GPIO_JD2_STICKY (0x1 << 9) 1540 #define RT5677_EN_GPIO_JD2_STICKY_SFT 9 1541 #define RT5677_INV_GPIO_JD2 (0x1 << 8) 1542 #define RT5677_INV_GPIO_JD2_SFT 8 1543 #define RT5677_STA_MICBIAS1_OVCD (0x1 << 7) 1544 #define RT5677_STA_MICBIAS1_OVCD_SFT 7 1545 #define RT5677_EN_IRQ_MICBIAS1_OVCD (0x1 << 6) 1546 #define RT5677_EN_IRQ_MICBIAS1_OVCD_SFT 6 1547 #define RT5677_EN_MICBIAS1_OVCD_STICKY (0x1 << 5) 1548 #define RT5677_EN_MICBIAS1_OVCD_STICKY_SFT 5 1549 #define RT5677_INV_MICBIAS1_OVCD (0x1 << 4) 1550 #define RT5677_INV_MICBIAS1_OVCD_SFT 4 1551 #define RT5677_STA_GPIO_JD3 (0x1 << 3) 1552 #define RT5677_STA_GPIO_JD3_SFT 3 1553 #define RT5677_EN_IRQ_GPIO_JD3 (0x1 << 2) 1554 #define RT5677_EN_IRQ_GPIO_JD3_SFT 2 1555 #define RT5677_EN_GPIO_JD3_STICKY (0x1 << 1) 1556 #define RT5677_EN_GPIO_JD3_STICKY_SFT 1 1557 #define RT5677_INV_GPIO_JD3 (0x1 << 0) 1558 #define RT5677_INV_GPIO_JD3_SFT 0 1559 1560 /* GPIO status (0xbf) */ 1561 #define RT5677_GPIO6_STATUS_MASK (0x1 << 5) 1562 #define RT5677_GPIO6_STATUS_SFT 5 1563 #define RT5677_GPIO5_STATUS_MASK (0x1 << 4) 1564 #define RT5677_GPIO5_STATUS_SFT 4 1565 #define RT5677_GPIO4_STATUS_MASK (0x1 << 3) 1566 #define RT5677_GPIO4_STATUS_SFT 3 1567 #define RT5677_GPIO3_STATUS_MASK (0x1 << 2) 1568 #define RT5677_GPIO3_STATUS_SFT 2 1569 #define RT5677_GPIO2_STATUS_MASK (0x1 << 1) 1570 #define RT5677_GPIO2_STATUS_SFT 1 1571 #define RT5677_GPIO1_STATUS_MASK (0x1 << 0) 1572 #define RT5677_GPIO1_STATUS_SFT 0 1573 1574 /* GPIO Control 1 (0xc0) */ 1575 #define RT5677_GPIO1_PIN_MASK (0x1 << 15) 1576 #define RT5677_GPIO1_PIN_SFT 15 1577 #define RT5677_GPIO1_PIN_GPIO1 (0x0 << 15) 1578 #define RT5677_GPIO1_PIN_IRQ (0x1 << 15) 1579 #define RT5677_IPTV_MODE_MASK (0x1 << 14) 1580 #define RT5677_IPTV_MODE_SFT 14 1581 #define RT5677_IPTV_MODE_GPIO (0x0 << 14) 1582 #define RT5677_IPTV_MODE_IPTV (0x1 << 14) 1583 #define RT5677_FUNC_MODE_MASK (0x1 << 13) 1584 #define RT5677_FUNC_MODE_SFT 13 1585 #define RT5677_FUNC_MODE_DMIC_GPIO (0x0 << 13) 1586 #define RT5677_FUNC_MODE_JTAG (0x1 << 13) 1587 1588 /* GPIO Control 2 (0xc1) */ 1589 #define RT5677_GPIO5_DIR_MASK (0x1 << 14) 1590 #define RT5677_GPIO5_DIR_SFT 14 1591 #define RT5677_GPIO5_DIR_IN (0x0 << 14) 1592 #define RT5677_GPIO5_DIR_OUT (0x1 << 14) 1593 #define RT5677_GPIO5_OUT_MASK (0x1 << 13) 1594 #define RT5677_GPIO5_OUT_SFT 13 1595 #define RT5677_GPIO5_OUT_LO (0x0 << 13) 1596 #define RT5677_GPIO5_OUT_HI (0x1 << 13) 1597 #define RT5677_GPIO5_P_MASK (0x1 << 12) 1598 #define RT5677_GPIO5_P_SFT 12 1599 #define RT5677_GPIO5_P_NOR (0x0 << 12) 1600 #define RT5677_GPIO5_P_INV (0x1 << 12) 1601 #define RT5677_GPIO4_DIR_MASK (0x1 << 11) 1602 #define RT5677_GPIO4_DIR_SFT 11 1603 #define RT5677_GPIO4_DIR_IN (0x0 << 11) 1604 #define RT5677_GPIO4_DIR_OUT (0x1 << 11) 1605 #define RT5677_GPIO4_OUT_MASK (0x1 << 10) 1606 #define RT5677_GPIO4_OUT_SFT 10 1607 #define RT5677_GPIO4_OUT_LO (0x0 << 10) 1608 #define RT5677_GPIO4_OUT_HI (0x1 << 10) 1609 #define RT5677_GPIO4_P_MASK (0x1 << 9) 1610 #define RT5677_GPIO4_P_SFT 9 1611 #define RT5677_GPIO4_P_NOR (0x0 << 9) 1612 #define RT5677_GPIO4_P_INV (0x1 << 9) 1613 #define RT5677_GPIO3_DIR_MASK (0x1 << 8) 1614 #define RT5677_GPIO3_DIR_SFT 8 1615 #define RT5677_GPIO3_DIR_IN (0x0 << 8) 1616 #define RT5677_GPIO3_DIR_OUT (0x1 << 8) 1617 #define RT5677_GPIO3_OUT_MASK (0x1 << 7) 1618 #define RT5677_GPIO3_OUT_SFT 7 1619 #define RT5677_GPIO3_OUT_LO (0x0 << 7) 1620 #define RT5677_GPIO3_OUT_HI (0x1 << 7) 1621 #define RT5677_GPIO3_P_MASK (0x1 << 6) 1622 #define RT5677_GPIO3_P_SFT 6 1623 #define RT5677_GPIO3_P_NOR (0x0 << 6) 1624 #define RT5677_GPIO3_P_INV (0x1 << 6) 1625 #define RT5677_GPIO2_DIR_MASK (0x1 << 5) 1626 #define RT5677_GPIO2_DIR_SFT 5 1627 #define RT5677_GPIO2_DIR_IN (0x0 << 5) 1628 #define RT5677_GPIO2_DIR_OUT (0x1 << 5) 1629 #define RT5677_GPIO2_OUT_MASK (0x1 << 4) 1630 #define RT5677_GPIO2_OUT_SFT 4 1631 #define RT5677_GPIO2_OUT_LO (0x0 << 4) 1632 #define RT5677_GPIO2_OUT_HI (0x1 << 4) 1633 #define RT5677_GPIO2_P_MASK (0x1 << 3) 1634 #define RT5677_GPIO2_P_SFT 3 1635 #define RT5677_GPIO2_P_NOR (0x0 << 3) 1636 #define RT5677_GPIO2_P_INV (0x1 << 3) 1637 #define RT5677_GPIO1_DIR_MASK (0x1 << 2) 1638 #define RT5677_GPIO1_DIR_SFT 2 1639 #define RT5677_GPIO1_DIR_IN (0x0 << 2) 1640 #define RT5677_GPIO1_DIR_OUT (0x1 << 2) 1641 #define RT5677_GPIO1_OUT_MASK (0x1 << 1) 1642 #define RT5677_GPIO1_OUT_SFT 1 1643 #define RT5677_GPIO1_OUT_LO (0x0 << 1) 1644 #define RT5677_GPIO1_OUT_HI (0x1 << 1) 1645 #define RT5677_GPIO1_P_MASK (0x1 << 0) 1646 #define RT5677_GPIO1_P_SFT 0 1647 #define RT5677_GPIO1_P_NOR (0x0 << 0) 1648 #define RT5677_GPIO1_P_INV (0x1 << 0) 1649 1650 /* GPIO Control 3 (0xc2) */ 1651 #define RT5677_GPIO6_DIR_MASK (0x1 << 2) 1652 #define RT5677_GPIO6_DIR_SFT 2 1653 #define RT5677_GPIO6_DIR_IN (0x0 << 2) 1654 #define RT5677_GPIO6_DIR_OUT (0x1 << 2) 1655 #define RT5677_GPIO6_OUT_MASK (0x1 << 1) 1656 #define RT5677_GPIO6_OUT_SFT 1 1657 #define RT5677_GPIO6_OUT_LO (0x0 << 1) 1658 #define RT5677_GPIO6_OUT_HI (0x1 << 1) 1659 #define RT5677_GPIO6_P_MASK (0x1 << 0) 1660 #define RT5677_GPIO6_P_SFT 0 1661 #define RT5677_GPIO6_P_NOR (0x0 << 0) 1662 #define RT5677_GPIO6_P_INV (0x1 << 0) 1663 1664 /* General Control (0xfa) */ 1665 #define RT5677_IRQ_DEBOUNCE_SEL_MASK (0x3 << 3) 1666 #define RT5677_IRQ_DEBOUNCE_SEL_MCLK (0x0 << 3) 1667 #define RT5677_IRQ_DEBOUNCE_SEL_RC (0x1 << 3) 1668 #define RT5677_IRQ_DEBOUNCE_SEL_SLIM (0x2 << 3) 1669 1670 /* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */ 1671 #define RT5677_DSP_IB_01_H (0x1 << 15) 1672 #define RT5677_DSP_IB_01_H_SFT 15 1673 #define RT5677_DSP_IB_23_H (0x1 << 14) 1674 #define RT5677_DSP_IB_23_H_SFT 14 1675 #define RT5677_DSP_IB_45_H (0x1 << 13) 1676 #define RT5677_DSP_IB_45_H_SFT 13 1677 #define RT5677_DSP_IB_6_H (0x1 << 12) 1678 #define RT5677_DSP_IB_6_H_SFT 12 1679 #define RT5677_DSP_IB_7_H (0x1 << 11) 1680 #define RT5677_DSP_IB_7_H_SFT 11 1681 #define RT5677_DSP_IB_8_H (0x1 << 10) 1682 #define RT5677_DSP_IB_8_H_SFT 10 1683 #define RT5677_DSP_IB_9_H (0x1 << 9) 1684 #define RT5677_DSP_IB_9_H_SFT 9 1685 #define RT5677_DSP_IB_01_L (0x1 << 7) 1686 #define RT5677_DSP_IB_01_L_SFT 7 1687 #define RT5677_DSP_IB_23_L (0x1 << 6) 1688 #define RT5677_DSP_IB_23_L_SFT 6 1689 #define RT5677_DSP_IB_45_L (0x1 << 5) 1690 #define RT5677_DSP_IB_45_L_SFT 5 1691 #define RT5677_DSP_IB_6_L (0x1 << 4) 1692 #define RT5677_DSP_IB_6_L_SFT 4 1693 #define RT5677_DSP_IB_7_L (0x1 << 3) 1694 #define RT5677_DSP_IB_7_L_SFT 3 1695 #define RT5677_DSP_IB_8_L (0x1 << 2) 1696 #define RT5677_DSP_IB_8_L_SFT 2 1697 #define RT5677_DSP_IB_9_L (0x1 << 1) 1698 #define RT5677_DSP_IB_9_L_SFT 1 1699 1700 /* General Control2 (0xfc)*/ 1701 #define RT5677_GPIO5_FUNC_MASK (0x1 << 9) 1702 #define RT5677_GPIO5_FUNC_GPIO (0x0 << 9) 1703 #define RT5677_GPIO5_FUNC_DMIC (0x1 << 9) 1704 1705 #define RT5677_FIRMWARE1 "rt5677_dsp_fw1.bin" 1706 #define RT5677_FIRMWARE2 "rt5677_dsp_fw2.bin" 1707 1708 #define RT5677_DRV_NAME "rt5677" 1709 1710 /* System Clock Source */ 1711 enum { 1712 RT5677_SCLK_S_MCLK, 1713 RT5677_SCLK_S_PLL1, 1714 RT5677_SCLK_S_RCCLK, 1715 }; 1716 1717 /* PLL1 Source */ 1718 enum { 1719 RT5677_PLL1_S_MCLK, 1720 RT5677_PLL1_S_BCLK1, 1721 RT5677_PLL1_S_BCLK2, 1722 RT5677_PLL1_S_BCLK3, 1723 RT5677_PLL1_S_BCLK4, 1724 }; 1725 1726 enum { 1727 RT5677_AIF1, 1728 RT5677_AIF2, 1729 RT5677_AIF3, 1730 RT5677_AIF4, 1731 RT5677_AIF5, 1732 RT5677_AIFS, 1733 }; 1734 1735 enum { 1736 RT5677_GPIO1, 1737 RT5677_GPIO2, 1738 RT5677_GPIO3, 1739 RT5677_GPIO4, 1740 RT5677_GPIO5, 1741 RT5677_GPIO6, 1742 RT5677_GPIO_NUM, 1743 }; 1744 1745 enum { 1746 RT5677_IRQ_JD1, 1747 RT5677_IRQ_JD2, 1748 RT5677_IRQ_JD3, 1749 RT5677_IRQ_NUM, 1750 }; 1751 1752 enum rt5677_type { 1753 RT5677, 1754 RT5676, 1755 }; 1756 1757 /* ASRC clock source selection */ 1758 enum { 1759 RT5677_CLK_SEL_SYS, 1760 RT5677_CLK_SEL_I2S1_ASRC, 1761 RT5677_CLK_SEL_I2S2_ASRC, 1762 RT5677_CLK_SEL_I2S3_ASRC, 1763 RT5677_CLK_SEL_I2S4_ASRC, 1764 RT5677_CLK_SEL_I2S5_ASRC, 1765 RT5677_CLK_SEL_I2S6_ASRC, 1766 RT5677_CLK_SEL_SYS2, 1767 RT5677_CLK_SEL_SYS3, 1768 RT5677_CLK_SEL_SYS4, 1769 RT5677_CLK_SEL_SYS5, 1770 RT5677_CLK_SEL_SYS6, 1771 RT5677_CLK_SEL_SYS7, 1772 }; 1773 1774 /* filter mask */ 1775 enum { 1776 RT5677_DA_STEREO_FILTER = 0x1, 1777 RT5677_DA_MONO2_L_FILTER = (0x1 << 1), 1778 RT5677_DA_MONO2_R_FILTER = (0x1 << 2), 1779 RT5677_DA_MONO3_L_FILTER = (0x1 << 3), 1780 RT5677_DA_MONO3_R_FILTER = (0x1 << 4), 1781 RT5677_DA_MONO4_L_FILTER = (0x1 << 5), 1782 RT5677_DA_MONO4_R_FILTER = (0x1 << 6), 1783 RT5677_AD_STEREO1_FILTER = (0x1 << 7), 1784 RT5677_AD_STEREO2_FILTER = (0x1 << 8), 1785 RT5677_AD_STEREO3_FILTER = (0x1 << 9), 1786 RT5677_AD_STEREO4_FILTER = (0x1 << 10), 1787 RT5677_AD_MONO_L_FILTER = (0x1 << 11), 1788 RT5677_AD_MONO_R_FILTER = (0x1 << 12), 1789 RT5677_DSP_OB_0_3_FILTER = (0x1 << 13), 1790 RT5677_DSP_OB_4_7_FILTER = (0x1 << 14), 1791 RT5677_I2S1_SOURCE = (0x1 << 15), 1792 RT5677_I2S2_SOURCE = (0x1 << 16), 1793 RT5677_I2S3_SOURCE = (0x1 << 17), 1794 RT5677_I2S4_SOURCE = (0x1 << 18), 1795 }; 1796 1797 enum rt5677_dmic2_clk { 1798 RT5677_DMIC_CLK1 = 0, 1799 RT5677_DMIC_CLK2 = 1, 1800 }; 1801 1802 struct rt5677_platform_data { 1803 /* IN1/IN2/LOUT1/LOUT2/LOUT3 can optionally be differential */ 1804 bool in1_diff; 1805 bool in2_diff; 1806 bool lout1_diff; 1807 bool lout2_diff; 1808 bool lout3_diff; 1809 /* DMIC2 clock source selection */ 1810 enum rt5677_dmic2_clk dmic2_clk_pin; 1811 1812 /* configures GPIO, 0 - floating, 1 - pulldown, 2 - pullup */ 1813 u8 gpio_config[6]; 1814 1815 /* jd1 can select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively */ 1816 unsigned int jd1_gpio; 1817 /* jd2 and jd3 can select 0 ~ 3 as 1818 OFF, GPIO4, GPIO5 and GPIO6 respectively */ 1819 unsigned int jd2_gpio; 1820 unsigned int jd3_gpio; 1821 1822 /* Set MICBIAS1 VDD 1v8 or 3v3 */ 1823 bool micbias1_vdd_3v3; 1824 }; 1825 1826 struct rt5677_priv { 1827 struct snd_soc_component *component; 1828 struct device *dev; 1829 struct rt5677_platform_data pdata; 1830 struct regmap *regmap, *regmap_physical; 1831 const struct firmware *fw1, *fw2; 1832 struct mutex dsp_cmd_lock, dsp_pri_lock; 1833 1834 int sysclk; 1835 int sysclk_src; 1836 int lrck[RT5677_AIFS]; 1837 int bclk[RT5677_AIFS]; 1838 int master[RT5677_AIFS]; 1839 int pll_src; 1840 int pll_in; 1841 int pll_out; 1842 struct gpio_desc *pow_ldo2; /* POW_LDO2 pin */ 1843 struct gpio_desc *reset_pin; /* RESET pin */ 1844 enum rt5677_type type; 1845 #ifdef CONFIG_GPIOLIB 1846 struct gpio_chip gpio_chip; 1847 #endif 1848 bool dsp_vad_en; 1849 bool is_dsp_mode; 1850 bool is_vref_slow; 1851 1852 /* Interrupt handling */ 1853 struct irq_domain *domain; 1854 struct mutex irq_lock; 1855 unsigned int irq_en; 1856 }; 1857 1858 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component, 1859 unsigned int filter_mask, unsigned int clk_src); 1860 1861 #endif /* __RT5677_H__ */ 1862
