1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * rt5663.h -- RT5663 ALSA SoC audio driver 4 * 5 * Copyright 2016 Realtek Microelectronics 6 * Author: Jack Yu <jack.yu@realtek.com> 7 */ 8 9 #ifndef __RT5663_H__ 10 #define __RT5663_H__ 11 12 #include <sound/rt5663.h> 13 14 /* Info */ 15 #define RT5663_RESET 0x0000 16 #define RT5663_VENDOR_ID 0x00fd 17 #define RT5663_VENDOR_ID_1 0x00fe 18 #define RT5663_VENDOR_ID_2 0x00ff 19 20 #define RT5663_LOUT_CTRL 0x0001 21 #define RT5663_HP_AMP_2 0x0003 22 #define RT5663_MONO_OUT 0x0004 23 #define RT5663_MONO_GAIN 0x0007 24 25 #define RT5663_AEC_BST 0x000b 26 #define RT5663_IN1_IN2 0x000c 27 #define RT5663_IN3_IN4 0x000d 28 #define RT5663_INL1_INR1 0x000f 29 #define RT5663_CBJ_TYPE_2 0x0011 30 #define RT5663_CBJ_TYPE_3 0x0012 31 #define RT5663_CBJ_TYPE_4 0x0013 32 #define RT5663_CBJ_TYPE_5 0x0014 33 #define RT5663_CBJ_TYPE_8 0x0017 34 35 /* I/O - ADC/DAC/DMIC */ 36 #define RT5663_DAC3_DIG_VOL 0x001a 37 #define RT5663_DAC3_CTRL 0x001b 38 #define RT5663_MONO_ADC_DIG_VOL 0x001d 39 #define RT5663_STO2_ADC_DIG_VOL 0x001e 40 #define RT5663_MONO_ADC_BST_GAIN 0x0020 41 #define RT5663_STO2_ADC_BST_GAIN 0x0021 42 #define RT5663_SIDETONE_CTRL 0x0024 43 /* Mixer - D-D */ 44 #define RT5663_MONO1_ADC_MIXER 0x0027 45 #define RT5663_STO2_ADC_MIXER 0x0028 46 #define RT5663_MONO_DAC_MIXER 0x002b 47 #define RT5663_DAC2_SRC_CTRL 0x002e 48 #define RT5663_IF_3_4_DATA_CTL 0x002f 49 #define RT5663_IF_5_DATA_CTL 0x0030 50 #define RT5663_PDM_OUT_CTL 0x0031 51 #define RT5663_PDM_I2C_DATA_CTL1 0x0032 52 #define RT5663_PDM_I2C_DATA_CTL2 0x0033 53 #define RT5663_PDM_I2C_DATA_CTL3 0x0034 54 #define RT5663_PDM_I2C_DATA_CTL4 0x0035 55 56 /*Mixer - Analog*/ 57 #define RT5663_RECMIX1_NEW 0x003a 58 #define RT5663_RECMIX1L_0 0x003b 59 #define RT5663_RECMIX1L 0x003c 60 #define RT5663_RECMIX1R_0 0x003d 61 #define RT5663_RECMIX1R 0x003e 62 #define RT5663_RECMIX2_NEW 0x003f 63 #define RT5663_RECMIX2_L_2 0x0041 64 #define RT5663_RECMIX2_R 0x0042 65 #define RT5663_RECMIX2_R_2 0x0043 66 #define RT5663_CALIB_REC_LR 0x0044 67 #define RT5663_ALC_BK_GAIN 0x0049 68 #define RT5663_MONOMIX_GAIN 0x004a 69 #define RT5663_MONOMIX_IN_GAIN 0x004b 70 #define RT5663_OUT_MIXL_GAIN 0x004d 71 #define RT5663_OUT_LMIX_IN_GAIN 0x004e 72 #define RT5663_OUT_RMIX_IN_GAIN 0x004f 73 #define RT5663_OUT_RMIX_IN_GAIN1 0x0050 74 #define RT5663_LOUT_MIXER_CTRL 0x0052 75 /* Power */ 76 #define RT5663_PWR_VOL 0x0067 77 78 #define RT5663_ADCDAC_RST 0x006d 79 /* Format - ADC/DAC */ 80 #define RT5663_I2S34_SDP 0x0071 81 #define RT5663_I2S5_SDP 0x0072 82 83 /* Function - Analog */ 84 #define RT5663_ASRC_3 0x0085 85 #define RT5663_ASRC_6 0x0088 86 #define RT5663_ASRC_7 0x0089 87 #define RT5663_PLL_TRK_13 0x0099 88 #define RT5663_I2S_M_CLK_CTL 0x00a0 89 #define RT5663_FDIV_I2S34_M_CLK 0x00a1 90 #define RT5663_FDIV_I2S34_M_CLK2 0x00a2 91 #define RT5663_FDIV_I2S5_M_CLK 0x00a3 92 #define RT5663_FDIV_I2S5_M_CLK2 0x00a4 93 94 /* Function - Digital */ 95 #define RT5663_V2_IRQ_4 0x00b9 96 #define RT5663_GPIO_3 0x00c2 97 #define RT5663_GPIO_4 0x00c3 98 #define RT5663_GPIO_STA2 0x00c4 99 #define RT5663_HP_AMP_DET1 0x00d0 100 #define RT5663_HP_AMP_DET2 0x00d1 101 #define RT5663_HP_AMP_DET3 0x00d2 102 #define RT5663_MID_BD_HP_AMP 0x00d3 103 #define RT5663_LOW_BD_HP_AMP 0x00d4 104 #define RT5663_SOF_VOL_ZC2 0x00da 105 #define RT5663_ADC_STO2_ADJ1 0x00ee 106 #define RT5663_ADC_STO2_ADJ2 0x00ef 107 /* General Control */ 108 #define RT5663_A_JD_CTRL 0x00f0 109 #define RT5663_JD1_TRES_CTRL 0x00f1 110 #define RT5663_JD2_TRES_CTRL 0x00f2 111 #define RT5663_V2_JD_CTRL2 0x00f7 112 #define RT5663_DUM_REG_2 0x00fb 113 #define RT5663_DUM_REG_3 0x00fc 114 115 116 #define RT5663_DACADC_DIG_VOL2 0x0101 117 #define RT5663_DIG_IN_PIN2 0x0133 118 #define RT5663_PAD_DRV_CTL1 0x0136 119 #define RT5663_SOF_RAM_DEPOP 0x0138 120 #define RT5663_VOL_TEST 0x013f 121 #define RT5663_MONO_DYNA_1 0x0170 122 #define RT5663_MONO_DYNA_2 0x0171 123 #define RT5663_MONO_DYNA_3 0x0172 124 #define RT5663_MONO_DYNA_4 0x0173 125 #define RT5663_MONO_DYNA_5 0x0174 126 #define RT5663_MONO_DYNA_6 0x0175 127 #define RT5663_STO1_SIL_DET 0x0190 128 #define RT5663_MONOL_SIL_DET 0x0191 129 #define RT5663_MONOR_SIL_DET 0x0192 130 #define RT5663_STO2_DAC_SIL 0x0193 131 #define RT5663_PWR_SAV_CTL1 0x0194 132 #define RT5663_PWR_SAV_CTL2 0x0195 133 #define RT5663_PWR_SAV_CTL3 0x0196 134 #define RT5663_PWR_SAV_CTL4 0x0197 135 #define RT5663_PWR_SAV_CTL5 0x0198 136 #define RT5663_PWR_SAV_CTL6 0x0199 137 #define RT5663_MONO_AMP_CAL1 0x01a0 138 #define RT5663_MONO_AMP_CAL2 0x01a1 139 #define RT5663_MONO_AMP_CAL3 0x01a2 140 #define RT5663_MONO_AMP_CAL4 0x01a3 141 #define RT5663_MONO_AMP_CAL5 0x01a4 142 #define RT5663_MONO_AMP_CAL6 0x01a5 143 #define RT5663_MONO_AMP_CAL7 0x01a6 144 #define RT5663_MONO_AMP_CAL_ST1 0x01a7 145 #define RT5663_MONO_AMP_CAL_ST2 0x01a8 146 #define RT5663_MONO_AMP_CAL_ST3 0x01a9 147 #define RT5663_MONO_AMP_CAL_ST4 0x01aa 148 #define RT5663_MONO_AMP_CAL_ST5 0x01ab 149 #define RT5663_V2_HP_IMP_SEN_13 0x01b9 150 #define RT5663_V2_HP_IMP_SEN_14 0x01ba 151 #define RT5663_V2_HP_IMP_SEN_6 0x01bb 152 #define RT5663_V2_HP_IMP_SEN_7 0x01bc 153 #define RT5663_V2_HP_IMP_SEN_8 0x01bd 154 #define RT5663_V2_HP_IMP_SEN_9 0x01be 155 #define RT5663_V2_HP_IMP_SEN_10 0x01bf 156 #define RT5663_HP_LOGIC_3 0x01dc 157 #define RT5663_HP_CALIB_ST10 0x01f3 158 #define RT5663_HP_CALIB_ST11 0x01f4 159 #define RT5663_PRO_REG_TBL_4 0x0203 160 #define RT5663_PRO_REG_TBL_5 0x0204 161 #define RT5663_PRO_REG_TBL_6 0x0205 162 #define RT5663_PRO_REG_TBL_7 0x0206 163 #define RT5663_PRO_REG_TBL_8 0x0207 164 #define RT5663_PRO_REG_TBL_9 0x0208 165 #define RT5663_SAR_ADC_INL_1 0x0210 166 #define RT5663_SAR_ADC_INL_2 0x0211 167 #define RT5663_SAR_ADC_INL_3 0x0212 168 #define RT5663_SAR_ADC_INL_4 0x0213 169 #define RT5663_SAR_ADC_INL_5 0x0214 170 #define RT5663_SAR_ADC_INL_6 0x0215 171 #define RT5663_SAR_ADC_INL_7 0x0216 172 #define RT5663_SAR_ADC_INL_8 0x0217 173 #define RT5663_SAR_ADC_INL_9 0x0218 174 #define RT5663_SAR_ADC_INL_10 0x0219 175 #define RT5663_SAR_ADC_INL_11 0x021a 176 #define RT5663_SAR_ADC_INL_12 0x021b 177 #define RT5663_DRC_CTRL_1 0x02ff 178 #define RT5663_DRC1_CTRL_2 0x0301 179 #define RT5663_DRC1_CTRL_3 0x0302 180 #define RT5663_DRC1_CTRL_4 0x0303 181 #define RT5663_DRC1_CTRL_5 0x0304 182 #define RT5663_DRC1_CTRL_6 0x0305 183 #define RT5663_DRC1_HD_CTRL_1 0x0306 184 #define RT5663_DRC1_HD_CTRL_2 0x0307 185 #define RT5663_DRC1_PRI_REG_1 0x0310 186 #define RT5663_DRC1_PRI_REG_2 0x0311 187 #define RT5663_DRC1_PRI_REG_3 0x0312 188 #define RT5663_DRC1_PRI_REG_4 0x0313 189 #define RT5663_DRC1_PRI_REG_5 0x0314 190 #define RT5663_DRC1_PRI_REG_6 0x0315 191 #define RT5663_DRC1_PRI_REG_7 0x0316 192 #define RT5663_DRC1_PRI_REG_8 0x0317 193 #define RT5663_ALC_PGA_CTL_1 0x0330 194 #define RT5663_ALC_PGA_CTL_2 0x0331 195 #define RT5663_ALC_PGA_CTL_3 0x0332 196 #define RT5663_ALC_PGA_CTL_4 0x0333 197 #define RT5663_ALC_PGA_CTL_5 0x0334 198 #define RT5663_ALC_PGA_CTL_6 0x0335 199 #define RT5663_ALC_PGA_CTL_7 0x0336 200 #define RT5663_ALC_PGA_CTL_8 0x0337 201 #define RT5663_ALC_PGA_REG_1 0x0338 202 #define RT5663_ALC_PGA_REG_2 0x0339 203 #define RT5663_ALC_PGA_REG_3 0x033a 204 #define RT5663_ADC_EQ_RECOV_1 0x03c0 205 #define RT5663_ADC_EQ_RECOV_2 0x03c1 206 #define RT5663_ADC_EQ_RECOV_3 0x03c2 207 #define RT5663_ADC_EQ_RECOV_4 0x03c3 208 #define RT5663_ADC_EQ_RECOV_5 0x03c4 209 #define RT5663_ADC_EQ_RECOV_6 0x03c5 210 #define RT5663_ADC_EQ_RECOV_7 0x03c6 211 #define RT5663_ADC_EQ_RECOV_8 0x03c7 212 #define RT5663_ADC_EQ_RECOV_9 0x03c8 213 #define RT5663_ADC_EQ_RECOV_10 0x03c9 214 #define RT5663_ADC_EQ_RECOV_11 0x03ca 215 #define RT5663_ADC_EQ_RECOV_12 0x03cb 216 #define RT5663_ADC_EQ_RECOV_13 0x03cc 217 #define RT5663_VID_HIDDEN 0x03fe 218 #define RT5663_VID_CUSTOMER 0x03ff 219 #define RT5663_SCAN_MODE 0x07f0 220 #define RT5663_I2C_BYPA 0x07fa 221 222 /* Headphone Amp Control 2 (0x0003) */ 223 #define RT5663_EN_DAC_HPO_MASK (0x1 << 14) 224 #define RT5663_EN_DAC_HPO_SHIFT 14 225 #define RT5663_EN_DAC_HPO_DIS (0x0 << 14) 226 #define RT5663_EN_DAC_HPO_EN (0x1 << 14) 227 228 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ 229 #define RT5663_GAIN_HP (0x1f << 8) 230 #define RT5663_GAIN_HP_SHIFT 8 231 232 /* AEC BST Control (0x000b) */ 233 #define RT5663_GAIN_CBJ_MASK (0xf << 8) 234 #define RT5663_GAIN_CBJ_SHIFT 8 235 236 /* IN1 Control / MIC GND REF (0x000c) */ 237 #define RT5663_IN1_DF_MASK (0x1 << 15) 238 #define RT5663_IN1_DF_SHIFT 15 239 240 /* Combo Jack and Type Detection Control 1 (0x0010) */ 241 #define RT5663_CBJ_DET_MASK (0x1 << 15) 242 #define RT5663_CBJ_DET_SHIFT 15 243 #define RT5663_CBJ_DET_DIS (0x0 << 15) 244 #define RT5663_CBJ_DET_EN (0x1 << 15) 245 #define RT5663_DET_TYPE_MASK (0x1 << 12) 246 #define RT5663_DET_TYPE_SHIFT 12 247 #define RT5663_DET_TYPE_WLCSP (0x0 << 12) 248 #define RT5663_DET_TYPE_QFN (0x1 << 12) 249 #define RT5663_VREF_BIAS_MASK (0x1 << 6) 250 #define RT5663_VREF_BIAS_SHIFT 6 251 #define RT5663_VREF_BIAS_FSM (0x0 << 6) 252 #define RT5663_VREF_BIAS_REG (0x1 << 6) 253 254 /* REC Left Mixer Control 2 (0x003c) */ 255 #define RT5663_RECMIX1L_BST1_CBJ (0x1 << 7) 256 #define RT5663_RECMIX1L_BST1_CBJ_SHIFT 7 257 #define RT5663_RECMIX1L_BST2 (0x1 << 4) 258 #define RT5663_RECMIX1L_BST2_SHIFT 4 259 260 /* REC Right Mixer Control 2 (0x003e) */ 261 #define RT5663_RECMIX1R_BST2 (0x1 << 4) 262 #define RT5663_RECMIX1R_BST2_SHIFT 4 263 264 /* DAC1 Digital Volume (0x0019) */ 265 #define RT5663_DAC_L1_VOL_MASK (0xff << 8) 266 #define RT5663_DAC_L1_VOL_SHIFT 8 267 #define RT5663_DAC_R1_VOL_MASK (0xff) 268 #define RT5663_DAC_R1_VOL_SHIFT 0 269 270 /* ADC Digital Volume Control (0x001c) */ 271 #define RT5663_ADC_L_MUTE_MASK (0x1 << 15) 272 #define RT5663_ADC_L_MUTE_SHIFT 15 273 #define RT5663_ADC_L_VOL_MASK (0x7f << 8) 274 #define RT5663_ADC_L_VOL_SHIFT 8 275 #define RT5663_ADC_R_MUTE_MASK (0x1 << 7) 276 #define RT5663_ADC_R_MUTE_SHIFT 7 277 #define RT5663_ADC_R_VOL_MASK (0x7f) 278 #define RT5663_ADC_R_VOL_SHIFT 0 279 280 /* Stereo ADC Mixer Control (0x0026) */ 281 #define RT5663_M_STO1_ADC_L1 (0x1 << 15) 282 #define RT5663_M_STO1_ADC_L1_SHIFT 15 283 #define RT5663_M_STO1_ADC_L2 (0x1 << 14) 284 #define RT5663_M_STO1_ADC_L2_SHIFT 14 285 #define RT5663_STO1_ADC_L1_SRC (0x1 << 13) 286 #define RT5663_STO1_ADC_L1_SRC_SHIFT 13 287 #define RT5663_STO1_ADC_L2_SRC (0x1 << 12) 288 #define RT5663_STO1_ADC_L2_SRC_SHIFT 12 289 #define RT5663_STO1_ADC_L_SRC (0x3 << 10) 290 #define RT5663_STO1_ADC_L_SRC_SHIFT 10 291 #define RT5663_M_STO1_ADC_R1 (0x1 << 7) 292 #define RT5663_M_STO1_ADC_R1_SHIFT 7 293 #define RT5663_M_STO1_ADC_R2 (0x1 << 6) 294 #define RT5663_M_STO1_ADC_R2_SHIFT 6 295 #define RT5663_STO1_ADC_R1_SRC (0x1 << 5) 296 #define RT5663_STO1_ADC_R1_SRC_SHIFT 5 297 #define RT5663_STO1_ADC_R2_SRC (0x1 << 4) 298 #define RT5663_STO1_ADC_R2_SRC_SHIFT 4 299 #define RT5663_STO1_ADC_R_SRC (0x3 << 2) 300 #define RT5663_STO1_ADC_R_SRC_SHIFT 2 301 302 /* ADC Mixer to DAC Mixer Control (0x0029) */ 303 #define RT5663_M_ADCMIX_L (0x1 << 15) 304 #define RT5663_M_ADCMIX_L_SHIFT 15 305 #define RT5663_M_DAC1_L (0x1 << 14) 306 #define RT5663_M_DAC1_L_SHIFT 14 307 #define RT5663_M_ADCMIX_R (0x1 << 7) 308 #define RT5663_M_ADCMIX_R_SHIFT 7 309 #define RT5663_M_DAC1_R (0x1 << 6) 310 #define RT5663_M_DAC1_R_SHIFT 6 311 312 /* Stereo DAC Mixer Control (0x002a) */ 313 #define RT5663_M_DAC_L1_STO_L (0x1 << 15) 314 #define RT5663_M_DAC_L1_STO_L_SHIFT 15 315 #define RT5663_M_DAC_R1_STO_L (0x1 << 13) 316 #define RT5663_M_DAC_R1_STO_L_SHIFT 13 317 #define RT5663_M_DAC_L1_STO_R (0x1 << 7) 318 #define RT5663_M_DAC_L1_STO_R_SHIFT 7 319 #define RT5663_M_DAC_R1_STO_R (0x1 << 5) 320 #define RT5663_M_DAC_R1_STO_R_SHIFT 5 321 322 /* Power Management for Digital 1 (0x0061) */ 323 #define RT5663_PWR_I2S1 (0x1 << 15) 324 #define RT5663_PWR_I2S1_SHIFT 15 325 #define RT5663_PWR_DAC_L1 (0x1 << 11) 326 #define RT5663_PWR_DAC_L1_SHIFT 11 327 #define RT5663_PWR_DAC_R1 (0x1 << 10) 328 #define RT5663_PWR_DAC_R1_SHIFT 10 329 #define RT5663_PWR_LDO_DACREF_MASK (0x1 << 8) 330 #define RT5663_PWR_LDO_DACREF_SHIFT 8 331 #define RT5663_PWR_LDO_DACREF_ON (0x1 << 8) 332 #define RT5663_PWR_LDO_DACREF_DOWN (0x0 << 8) 333 #define RT5663_PWR_LDO_SHIFT 8 334 #define RT5663_PWR_ADC_L1 (0x1 << 4) 335 #define RT5663_PWR_ADC_L1_SHIFT 4 336 #define RT5663_PWR_ADC_R1 (0x1 << 3) 337 #define RT5663_PWR_ADC_R1_SHIFT 3 338 339 /* Power Management for Digital 2 (0x0062) */ 340 #define RT5663_PWR_ADC_S1F (0x1 << 15) 341 #define RT5663_PWR_ADC_S1F_SHIFT 15 342 #define RT5663_PWR_DAC_S1F (0x1 << 10) 343 #define RT5663_PWR_DAC_S1F_SHIFT 10 344 345 /* Power Management for Analog 1 (0x0063) */ 346 #define RT5663_PWR_VREF1 (0x1 << 15) 347 #define RT5663_PWR_VREF1_MASK (0x1 << 15) 348 #define RT5663_PWR_VREF1_SHIFT 15 349 #define RT5663_PWR_FV1 (0x1 << 14) 350 #define RT5663_PWR_FV1_MASK (0x1 << 14) 351 #define RT5663_PWR_FV1_SHIFT 14 352 #define RT5663_PWR_VREF2 (0x1 << 13) 353 #define RT5663_PWR_VREF2_MASK (0x1 << 13) 354 #define RT5663_PWR_VREF2_SHIFT 13 355 #define RT5663_PWR_FV2 (0x1 << 12) 356 #define RT5663_PWR_FV2_MASK (0x1 << 12) 357 #define RT5663_PWR_FV2_SHIFT 12 358 #define RT5663_PWR_MB (0x1 << 9) 359 #define RT5663_PWR_MB_MASK (0x1 << 9) 360 #define RT5663_PWR_MB_SHIFT 9 361 #define RT5663_AMP_HP_MASK (0x3 << 2) 362 #define RT5663_AMP_HP_SHIFT 2 363 #define RT5663_AMP_HP_1X (0x0 << 2) 364 #define RT5663_AMP_HP_3X (0x1 << 2) 365 #define RT5663_AMP_HP_5X (0x3 << 2) 366 #define RT5663_LDO1_DVO_MASK (0x3) 367 #define RT5663_LDO1_DVO_SHIFT 0 368 #define RT5663_LDO1_DVO_0_9V (0x0) 369 #define RT5663_LDO1_DVO_1_0V (0x1) 370 #define RT5663_LDO1_DVO_1_2V (0x2) 371 #define RT5663_LDO1_DVO_1_4V (0x3) 372 373 /* Power Management for Analog 2 (0x0064) */ 374 #define RT5663_PWR_BST1 (0x1 << 15) 375 #define RT5663_PWR_BST1_MASK (0x1 << 15) 376 #define RT5663_PWR_BST1_SHIFT 15 377 #define RT5663_PWR_BST1_OFF (0x0 << 15) 378 #define RT5663_PWR_BST1_ON (0x1 << 15) 379 #define RT5663_PWR_BST2 (0x1 << 14) 380 #define RT5663_PWR_BST2_MASK (0x1 << 14) 381 #define RT5663_PWR_BST2_SHIFT 14 382 #define RT5663_PWR_MB1 (0x1 << 11) 383 #define RT5663_PWR_MB1_SHIFT 11 384 #define RT5663_PWR_MB2 (0x1 << 10) 385 #define RT5663_PWR_MB2_SHIFT 10 386 #define RT5663_PWR_BST2_OP (0x1 << 6) 387 #define RT5663_PWR_BST2_OP_MASK (0x1 << 6) 388 #define RT5663_PWR_BST2_OP_SHIFT 6 389 #define RT5663_PWR_JD1 (0x1 << 3) 390 #define RT5663_PWR_JD1_MASK (0x1 << 3) 391 #define RT5663_PWR_JD1_SHIFT 3 392 #define RT5663_PWR_JD2 (0x1 << 2) 393 #define RT5663_PWR_JD2_MASK (0x1 << 2) 394 #define RT5663_PWR_JD2_SHIFT 2 395 #define RT5663_PWR_RECMIX1 (0x1 << 1) 396 #define RT5663_PWR_RECMIX1_SHIFT 1 397 #define RT5663_PWR_RECMIX2 (0x1) 398 #define RT5663_PWR_RECMIX2_SHIFT 0 399 400 /* Power Management for Analog 3 (0x0065) */ 401 #define RT5663_PWR_CBJ_MASK (0x1 << 9) 402 #define RT5663_PWR_CBJ_SHIFT 9 403 #define RT5663_PWR_CBJ_OFF (0x0 << 9) 404 #define RT5663_PWR_CBJ_ON (0x1 << 9) 405 #define RT5663_PWR_PLL (0x1 << 6) 406 #define RT5663_PWR_PLL_SHIFT 6 407 #define RT5663_PWR_LDO2 (0x1 << 2) 408 #define RT5663_PWR_LDO2_SHIFT 2 409 410 /* Power Management for Volume (0x0067) */ 411 #define RT5663_V2_PWR_MIC_DET (0x1 << 5) 412 #define RT5663_V2_PWR_MIC_DET_SHIFT 5 413 414 /* MCLK and System Clock Detection Control (0x006b) */ 415 #define RT5663_EN_ANA_CLK_DET_MASK (0x1 << 15) 416 #define RT5663_EN_ANA_CLK_DET_SHIFT 15 417 #define RT5663_EN_ANA_CLK_DET_DIS (0x0 << 15) 418 #define RT5663_EN_ANA_CLK_DET_AUTO (0x1 << 15) 419 #define RT5663_PWR_CLK_DET_MASK (0x1) 420 #define RT5663_PWR_CLK_DET_SHIFT 0 421 #define RT5663_PWR_CLK_DET_DIS (0x0) 422 #define RT5663_PWR_CLK_DET_EN (0x1) 423 424 /* I2S1 Audio Serial Data Port Control (0x0070) */ 425 #define RT5663_I2S_MS_MASK (0x1 << 15) 426 #define RT5663_I2S_MS_SHIFT 15 427 #define RT5663_I2S_MS_M (0x0 << 15) 428 #define RT5663_I2S_MS_S (0x1 << 15) 429 #define RT5663_I2S_BP_MASK (0x1 << 8) 430 #define RT5663_I2S_BP_SHIFT 8 431 #define RT5663_I2S_BP_NOR (0x0 << 8) 432 #define RT5663_I2S_BP_INV (0x1 << 8) 433 #define RT5663_I2S_DL_MASK (0x3 << 4) 434 #define RT5663_I2S_DL_SHIFT 4 435 #define RT5663_I2S_DL_16 (0x0 << 4) 436 #define RT5663_I2S_DL_20 (0x1 << 4) 437 #define RT5663_I2S_DL_24 (0x2 << 4) 438 #define RT5663_I2S_DL_8 (0x3 << 4) 439 #define RT5663_I2S_DF_MASK (0x7) 440 #define RT5663_I2S_DF_SHIFT 0 441 #define RT5663_I2S_DF_I2S (0x0) 442 #define RT5663_I2S_DF_LEFT (0x1) 443 #define RT5663_I2S_DF_PCM_A (0x2) 444 #define RT5663_I2S_DF_PCM_B (0x3) 445 #define RT5663_I2S_DF_PCM_A_N (0x6) 446 #define RT5663_I2S_DF_PCM_B_N (0x7) 447 448 /* ADC/DAC Clock Control 1 (0x0073) */ 449 #define RT5663_I2S_PD1_MASK (0x7 << 12) 450 #define RT5663_I2S_PD1_SHIFT 12 451 #define RT5663_M_I2S_DIV_MASK (0x7 << 8) 452 #define RT5663_M_I2S_DIV_SHIFT 8 453 #define RT5663_CLK_SRC_MASK (0x3 << 4) 454 #define RT5663_CLK_SRC_MCLK (0x0 << 4) 455 #define RT5663_CLK_SRC_PLL_OUT (0x1 << 4) 456 #define RT5663_CLK_SRC_DIV (0x2 << 4) 457 #define RT5663_CLK_SRC_RC (0x3 << 4) 458 #define RT5663_DAC_OSR_MASK (0x3 << 2) 459 #define RT5663_DAC_OSR_SHIFT 2 460 #define RT5663_DAC_OSR_128 (0x0 << 2) 461 #define RT5663_DAC_OSR_64 (0x1 << 2) 462 #define RT5663_DAC_OSR_32 (0x2 << 2) 463 #define RT5663_ADC_OSR_MASK (0x3) 464 #define RT5663_ADC_OSR_SHIFT 0 465 #define RT5663_ADC_OSR_128 (0x0) 466 #define RT5663_ADC_OSR_64 (0x1) 467 #define RT5663_ADC_OSR_32 (0x2) 468 469 /* TDM1 control 1 (0x0078) */ 470 #define RT5663_TDM_MODE_MASK (0x1 << 15) 471 #define RT5663_TDM_MODE_SHIFT 15 472 #define RT5663_TDM_MODE_I2S (0x0 << 15) 473 #define RT5663_TDM_MODE_TDM (0x1 << 15) 474 #define RT5663_TDM_IN_CH_MASK (0x3 << 10) 475 #define RT5663_TDM_IN_CH_SHIFT 10 476 #define RT5663_TDM_IN_CH_2 (0x0 << 10) 477 #define RT5663_TDM_IN_CH_4 (0x1 << 10) 478 #define RT5663_TDM_IN_CH_6 (0x2 << 10) 479 #define RT5663_TDM_IN_CH_8 (0x3 << 10) 480 #define RT5663_TDM_OUT_CH_MASK (0x3 << 8) 481 #define RT5663_TDM_OUT_CH_SHIFT 8 482 #define RT5663_TDM_OUT_CH_2 (0x0 << 8) 483 #define RT5663_TDM_OUT_CH_4 (0x1 << 8) 484 #define RT5663_TDM_OUT_CH_6 (0x2 << 8) 485 #define RT5663_TDM_OUT_CH_8 (0x3 << 8) 486 #define RT5663_TDM_IN_LEN_MASK (0x3 << 6) 487 #define RT5663_TDM_IN_LEN_SHIFT 6 488 #define RT5663_TDM_IN_LEN_16 (0x0 << 6) 489 #define RT5663_TDM_IN_LEN_20 (0x1 << 6) 490 #define RT5663_TDM_IN_LEN_24 (0x2 << 6) 491 #define RT5663_TDM_IN_LEN_32 (0x3 << 6) 492 #define RT5663_TDM_OUT_LEN_MASK (0x3 << 4) 493 #define RT5663_TDM_OUT_LEN_SHIFT 4 494 #define RT5663_TDM_OUT_LEN_16 (0x0 << 4) 495 #define RT5663_TDM_OUT_LEN_20 (0x1 << 4) 496 #define RT5663_TDM_OUT_LEN_24 (0x2 << 4) 497 #define RT5663_TDM_OUT_LEN_32 (0x3 << 4) 498 499 /* Global Clock Control (0x0080) */ 500 #define RT5663_SCLK_SRC_MASK (0x3 << 14) 501 #define RT5663_SCLK_SRC_SHIFT 14 502 #define RT5663_SCLK_SRC_MCLK (0x0 << 14) 503 #define RT5663_SCLK_SRC_PLL1 (0x1 << 14) 504 #define RT5663_SCLK_SRC_RCCLK (0x2 << 14) 505 #define RT5663_PLL1_SRC_MASK (0x7 << 11) 506 #define RT5663_PLL1_SRC_SHIFT 11 507 #define RT5663_PLL1_SRC_MCLK (0x0 << 11) 508 #define RT5663_PLL1_SRC_BCLK1 (0x1 << 11) 509 #define RT5663_V2_PLL1_SRC_MASK (0x7 << 8) 510 #define RT5663_V2_PLL1_SRC_SHIFT 8 511 #define RT5663_V2_PLL1_SRC_MCLK (0x0 << 8) 512 #define RT5663_V2_PLL1_SRC_BCLK1 (0x1 << 8) 513 #define RT5663_PLL1_PD_MASK (0x1 << 4) 514 #define RT5663_PLL1_PD_SHIFT 4 515 516 #define RT5663_PLL_INP_MAX 40000000 517 #define RT5663_PLL_INP_MIN 256000 518 /* PLL M/N/K Code Control 1 (0x0081) */ 519 #define RT5663_PLL_N_MAX 0x001ff 520 #define RT5663_PLL_N_MASK (RT5663_PLL_N_MAX << 7) 521 #define RT5663_PLL_N_SHIFT 7 522 #define RT5663_PLL_K_MAX 0x001f 523 #define RT5663_PLL_K_MASK (RT5663_PLL_K_MAX) 524 #define RT5663_PLL_K_SHIFT 0 525 526 /* PLL M/N/K Code Control 2 (0x0082) */ 527 #define RT5663_PLL_M_MAX 0x00f 528 #define RT5663_PLL_M_MASK (RT5663_PLL_M_MAX << 12) 529 #define RT5663_PLL_M_SHIFT 12 530 #define RT5663_PLL_M_BP (0x1 << 11) 531 #define RT5663_PLL_M_BP_SHIFT 11 532 533 /* PLL tracking mode 1 (0x0083) */ 534 #define RT5663_V2_I2S1_ASRC_MASK (0x1 << 13) 535 #define RT5663_V2_I2S1_ASRC_SHIFT 13 536 #define RT5663_V2_DAC_STO1_ASRC_MASK (0x1 << 12) 537 #define RT5663_V2_DAC_STO1_ASRC_SHIFT 12 538 #define RT5663_V2_ADC_STO1_ASRC_MASK (0x1 << 4) 539 #define RT5663_V2_ADC_STO1_ASRC_SHIFT 4 540 541 /* PLL tracking mode 2 (0x0084)*/ 542 #define RT5663_DA_STO1_TRACK_MASK (0x7 << 12) 543 #define RT5663_DA_STO1_TRACK_SHIFT 12 544 #define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12) 545 #define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12) 546 547 /* PLL tracking mode 3 (0x0085)*/ 548 #define RT5663_V2_AD_STO1_TRACK_MASK (0x7 << 12) 549 #define RT5663_V2_AD_STO1_TRACK_SHIFT 12 550 #define RT5663_V2_AD_STO1_TRACK_SYSCLK (0x0 << 12) 551 #define RT5663_V2_AD_STO1_TRACK_I2S1 (0x1 << 12) 552 553 /* HPOUT Charge pump control 1 (0x0091) */ 554 #define RT5663_OSW_HP_L_MASK (0x1 << 11) 555 #define RT5663_OSW_HP_L_SHIFT 11 556 #define RT5663_OSW_HP_L_EN (0x1 << 11) 557 #define RT5663_OSW_HP_L_DIS (0x0 << 11) 558 #define RT5663_OSW_HP_R_MASK (0x1 << 10) 559 #define RT5663_OSW_HP_R_SHIFT 10 560 #define RT5663_OSW_HP_R_EN (0x1 << 10) 561 #define RT5663_OSW_HP_R_DIS (0x0 << 10) 562 #define RT5663_SEL_PM_HP_MASK (0x3 << 8) 563 #define RT5663_SEL_PM_HP_SHIFT 8 564 #define RT5663_SEL_PM_HP_0_6 (0x0 << 8) 565 #define RT5663_SEL_PM_HP_0_9 (0x1 << 8) 566 #define RT5663_SEL_PM_HP_1_8 (0x2 << 8) 567 #define RT5663_SEL_PM_HP_HIGH (0x3 << 8) 568 #define RT5663_OVCD_HP_MASK (0x1 << 2) 569 #define RT5663_OVCD_HP_SHIFT 2 570 #define RT5663_OVCD_HP_EN (0x1 << 2) 571 #define RT5663_OVCD_HP_DIS (0x0 << 2) 572 573 /* RC Clock Control (0x0094) */ 574 #define RT5663_DIG_25M_CLK_MASK (0x1 << 9) 575 #define RT5663_DIG_25M_CLK_SHIFT 9 576 #define RT5663_DIG_25M_CLK_DIS (0x0 << 9) 577 #define RT5663_DIG_25M_CLK_EN (0x1 << 9) 578 #define RT5663_DIG_1M_CLK_MASK (0x1 << 8) 579 #define RT5663_DIG_1M_CLK_SHIFT 8 580 #define RT5663_DIG_1M_CLK_DIS (0x0 << 8) 581 #define RT5663_DIG_1M_CLK_EN (0x1 << 8) 582 583 /* Auto Turn On 1M RC CLK (0x009f) */ 584 #define RT5663_IRQ_POW_SAV_MASK (0x1 << 15) 585 #define RT5663_IRQ_POW_SAV_SHIFT 15 586 #define RT5663_IRQ_POW_SAV_DIS (0x0 << 15) 587 #define RT5663_IRQ_POW_SAV_EN (0x1 << 15) 588 #define RT5663_IRQ_POW_SAV_JD1_MASK (0x1 << 14) 589 #define RT5663_IRQ_POW_SAV_JD1_SHIFT 14 590 #define RT5663_IRQ_POW_SAV_JD1_DIS (0x0 << 14) 591 #define RT5663_IRQ_POW_SAV_JD1_EN (0x1 << 14) 592 #define RT5663_IRQ_MANUAL_MASK (0x1 << 8) 593 #define RT5663_IRQ_MANUAL_SHIFT 8 594 #define RT5663_IRQ_MANUAL_DIS (0x0 << 8) 595 #define RT5663_IRQ_MANUAL_EN (0x1 << 8) 596 597 /* IRQ Control 1 (0x00b6) */ 598 #define RT5663_EN_CB_JD_MASK (0x1 << 3) 599 #define RT5663_EN_CB_JD_SHIFT 3 600 #define RT5663_EN_CB_JD_EN (0x1 << 3) 601 #define RT5663_EN_CB_JD_DIS (0x0 << 3) 602 603 /* IRQ Control 3 (0x00b8) */ 604 #define RT5663_V2_EN_IRQ_INLINE_MASK (0x1 << 6) 605 #define RT5663_V2_EN_IRQ_INLINE_SHIFT 6 606 #define RT5663_V2_EN_IRQ_INLINE_BYP (0x0 << 6) 607 #define RT5663_V2_EN_IRQ_INLINE_NOR (0x1 << 6) 608 609 /* GPIO Control 1 (0x00c0) */ 610 #define RT5663_GP1_PIN_MASK (0x1 << 15) 611 #define RT5663_GP1_PIN_SHIFT 15 612 #define RT5663_GP1_PIN_GPIO1 (0x0 << 15) 613 #define RT5663_GP1_PIN_IRQ (0x1 << 15) 614 615 /* GPIO Control 2 (0x00c1) */ 616 #define RT5663_GP4_PIN_CONF_MASK (0x1 << 5) 617 #define RT5663_GP4_PIN_CONF_SHIFT 5 618 #define RT5663_GP4_PIN_CONF_INPUT (0x0 << 5) 619 #define RT5663_GP4_PIN_CONF_OUTPUT (0x1 << 5) 620 621 /* GPIO Control 2 (0x00c2) */ 622 #define RT5663_GP8_PIN_CONF_MASK (0x1 << 13) 623 #define RT5663_GP8_PIN_CONF_SHIFT 13 624 #define RT5663_GP8_PIN_CONF_INPUT (0x0 << 13) 625 #define RT5663_GP8_PIN_CONF_OUTPUT (0x1 << 13) 626 627 /* 4 Buttons Inline Command Function 1 (0x00df) */ 628 #define RT5663_4BTN_CLK_DEB_MASK (0x3 << 2) 629 #define RT5663_4BTN_CLK_DEB_SHIFT 2 630 #define RT5663_4BTN_CLK_DEB_8MS (0x0 << 2) 631 #define RT5663_4BTN_CLK_DEB_16MS (0x1 << 2) 632 #define RT5663_4BTN_CLK_DEB_32MS (0x2 << 2) 633 #define RT5663_4BTN_CLK_DEB_65MS (0x3 << 2) 634 635 /* Inline Command Function 6 (0x00e0) */ 636 #define RT5663_EN_4BTN_INL_MASK (0x1 << 15) 637 #define RT5663_EN_4BTN_INL_SHIFT 15 638 #define RT5663_EN_4BTN_INL_DIS (0x0 << 15) 639 #define RT5663_EN_4BTN_INL_EN (0x1 << 15) 640 #define RT5663_RESET_4BTN_INL_MASK (0x1 << 14) 641 #define RT5663_RESET_4BTN_INL_SHIFT 14 642 #define RT5663_RESET_4BTN_INL_RESET (0x0 << 14) 643 #define RT5663_RESET_4BTN_INL_NOR (0x1 << 14) 644 645 /* Digital Misc Control (0x00fa) */ 646 #define RT5663_DIG_GATE_CTRL_MASK 0x1 647 #define RT5663_DIG_GATE_CTRL_SHIFT (0) 648 #define RT5663_DIG_GATE_CTRL_DIS 0x0 649 #define RT5663_DIG_GATE_CTRL_EN 0x1 650 651 /* Chopper and Clock control for DAC L (0x013a)*/ 652 #define RT5663_CKXEN_DAC1_MASK (0x1 << 13) 653 #define RT5663_CKXEN_DAC1_SHIFT 13 654 #define RT5663_CKGEN_DAC1_MASK (0x1 << 12) 655 #define RT5663_CKGEN_DAC1_SHIFT 12 656 657 /* Chopper and Clock control for ADC (0x013b)*/ 658 #define RT5663_CKXEN_ADCC_MASK (0x1 << 13) 659 #define RT5663_CKXEN_ADCC_SHIFT 13 660 #define RT5663_CKGEN_ADCC_MASK (0x1 << 12) 661 #define RT5663_CKGEN_ADCC_SHIFT 12 662 663 /* HP Behavior Logic Control 2 (0x01db) */ 664 #define RT5663_HP_SIG_SRC1_MASK (0x3) 665 #define RT5663_HP_SIG_SRC1_SHIFT 0 666 #define RT5663_HP_SIG_SRC1_HP_DC (0x0) 667 #define RT5663_HP_SIG_SRC1_HP_CALIB (0x1) 668 #define RT5663_HP_SIG_SRC1_REG (0x2) 669 #define RT5663_HP_SIG_SRC1_SILENCE (0x3) 670 671 /* RT5663 specific register */ 672 #define RT5663_HP_OUT_EN 0x0002 673 #define RT5663_HP_LCH_DRE 0x0005 674 #define RT5663_HP_RCH_DRE 0x0006 675 #define RT5663_CALIB_BST 0x000a 676 #define RT5663_RECMIX 0x0010 677 #define RT5663_SIL_DET_CTL 0x0015 678 #define RT5663_PWR_SAV_SILDET 0x0016 679 #define RT5663_SIDETONE_CTL 0x0018 680 #define RT5663_STO1_DAC_DIG_VOL 0x0019 681 #define RT5663_STO1_ADC_DIG_VOL 0x001c 682 #define RT5663_STO1_BOOST 0x001f 683 #define RT5663_HP_IMP_GAIN_1 0x0022 684 #define RT5663_HP_IMP_GAIN_2 0x0023 685 #define RT5663_STO1_ADC_MIXER 0x0026 686 #define RT5663_AD_DA_MIXER 0x0029 687 #define RT5663_STO_DAC_MIXER 0x002a 688 #define RT5663_DIG_SIDE_MIXER 0x002c 689 #define RT5663_BYPASS_STO_DAC 0x002d 690 #define RT5663_CALIB_REC_MIX 0x0040 691 #define RT5663_PWR_DIG_1 0x0061 692 #define RT5663_PWR_DIG_2 0x0062 693 #define RT5663_PWR_ANLG_1 0x0063 694 #define RT5663_PWR_ANLG_2 0x0064 695 #define RT5663_PWR_ANLG_3 0x0065 696 #define RT5663_PWR_MIXER 0x0066 697 #define RT5663_SIG_CLK_DET 0x006b 698 #define RT5663_PRE_DIV_GATING_1 0x006e 699 #define RT5663_PRE_DIV_GATING_2 0x006f 700 #define RT5663_I2S1_SDP 0x0070 701 #define RT5663_ADDA_CLK_1 0x0073 702 #define RT5663_ADDA_RST 0x0074 703 #define RT5663_FRAC_DIV_1 0x0075 704 #define RT5663_FRAC_DIV_2 0x0076 705 #define RT5663_TDM_1 0x0077 706 #define RT5663_TDM_2 0x0078 707 #define RT5663_TDM_3 0x0079 708 #define RT5663_TDM_4 0x007a 709 #define RT5663_TDM_5 0x007b 710 #define RT5663_TDM_6 0x007c 711 #define RT5663_TDM_7 0x007d 712 #define RT5663_TDM_8 0x007e 713 #define RT5663_TDM_9 0x007f 714 #define RT5663_GLB_CLK 0x0080 715 #define RT5663_PLL_1 0x0081 716 #define RT5663_PLL_2 0x0082 717 #define RT5663_ASRC_1 0x0083 718 #define RT5663_ASRC_2 0x0084 719 #define RT5663_ASRC_4 0x0086 720 #define RT5663_DUMMY_REG 0x0087 721 #define RT5663_ASRC_8 0x008a 722 #define RT5663_ASRC_9 0x008b 723 #define RT5663_ASRC_11 0x008c 724 #define RT5663_DEPOP_1 0x008e 725 #define RT5663_DEPOP_2 0x008f 726 #define RT5663_DEPOP_3 0x0090 727 #define RT5663_HP_CHARGE_PUMP_1 0x0091 728 #define RT5663_HP_CHARGE_PUMP_2 0x0092 729 #define RT5663_MICBIAS_1 0x0093 730 #define RT5663_RC_CLK 0x0094 731 #define RT5663_ASRC_11_2 0x0097 732 #define RT5663_DUMMY_REG_2 0x0098 733 #define RT5663_REC_PATH_GAIN 0x009a 734 #define RT5663_AUTO_1MRC_CLK 0x009f 735 #define RT5663_ADC_EQ_1 0x00ae 736 #define RT5663_ADC_EQ_2 0x00af 737 #define RT5663_IRQ_1 0x00b6 738 #define RT5663_IRQ_2 0x00b7 739 #define RT5663_IRQ_3 0x00b8 740 #define RT5663_IRQ_4 0x00ba 741 #define RT5663_IRQ_5 0x00bb 742 #define RT5663_INT_ST_1 0x00be 743 #define RT5663_INT_ST_2 0x00bf 744 #define RT5663_GPIO_1 0x00c0 745 #define RT5663_GPIO_2 0x00c1 746 #define RT5663_GPIO_STA1 0x00c5 747 #define RT5663_SIN_GEN_1 0x00cb 748 #define RT5663_SIN_GEN_2 0x00cc 749 #define RT5663_SIN_GEN_3 0x00cd 750 #define RT5663_SOF_VOL_ZC1 0x00d9 751 #define RT5663_IL_CMD_1 0x00db 752 #define RT5663_IL_CMD_2 0x00dc 753 #define RT5663_IL_CMD_3 0x00dd 754 #define RT5663_IL_CMD_4 0x00de 755 #define RT5663_IL_CMD_5 0x00df 756 #define RT5663_IL_CMD_6 0x00e0 757 #define RT5663_IL_CMD_7 0x00e1 758 #define RT5663_IL_CMD_8 0x00e2 759 #define RT5663_IL_CMD_PWRSAV1 0x00e4 760 #define RT5663_IL_CMD_PWRSAV2 0x00e5 761 #define RT5663_EM_JACK_TYPE_1 0x00e6 762 #define RT5663_EM_JACK_TYPE_2 0x00e7 763 #define RT5663_EM_JACK_TYPE_3 0x00e8 764 #define RT5663_EM_JACK_TYPE_4 0x00e9 765 #define RT5663_EM_JACK_TYPE_5 0x00ea 766 #define RT5663_EM_JACK_TYPE_6 0x00eb 767 #define RT5663_STO1_HPF_ADJ1 0x00ec 768 #define RT5663_STO1_HPF_ADJ2 0x00ed 769 #define RT5663_FAST_OFF_MICBIAS 0x00f4 770 #define RT5663_JD_CTRL1 0x00f6 771 #define RT5663_JD_CTRL2 0x00f8 772 #define RT5663_DIG_MISC 0x00fa 773 #define RT5663_DIG_VOL_ZCD 0x0100 774 #define RT5663_ANA_BIAS_CUR_1 0x0108 775 #define RT5663_ANA_BIAS_CUR_2 0x0109 776 #define RT5663_ANA_BIAS_CUR_3 0x010a 777 #define RT5663_ANA_BIAS_CUR_4 0x010b 778 #define RT5663_ANA_BIAS_CUR_5 0x010c 779 #define RT5663_ANA_BIAS_CUR_6 0x010d 780 #define RT5663_BIAS_CUR_5 0x010e 781 #define RT5663_BIAS_CUR_6 0x010f 782 #define RT5663_BIAS_CUR_7 0x0110 783 #define RT5663_BIAS_CUR_8 0x0111 784 #define RT5663_DACREF_LDO 0x0112 785 #define RT5663_DUMMY_REG_3 0x0113 786 #define RT5663_BIAS_CUR_9 0x0114 787 #define RT5663_DUMMY_REG_4 0x0116 788 #define RT5663_VREFADJ_OP 0x0117 789 #define RT5663_VREF_RECMIX 0x0118 790 #define RT5663_CHARGE_PUMP_1 0x0125 791 #define RT5663_CHARGE_PUMP_1_2 0x0126 792 #define RT5663_CHARGE_PUMP_1_3 0x0127 793 #define RT5663_CHARGE_PUMP_2 0x0128 794 #define RT5663_DIG_IN_PIN1 0x0132 795 #define RT5663_PAD_DRV_CTL 0x0137 796 #define RT5663_PLL_INT_REG 0x0139 797 #define RT5663_CHOP_DAC_L 0x013a 798 #define RT5663_CHOP_ADC 0x013b 799 #define RT5663_CALIB_ADC 0x013c 800 #define RT5663_CHOP_DAC_R 0x013d 801 #define RT5663_DUMMY_CTL_DACLR 0x013e 802 #define RT5663_DUMMY_REG_5 0x0140 803 #define RT5663_SOFT_RAMP 0x0141 804 #define RT5663_TEST_MODE_1 0x0144 805 #define RT5663_TEST_MODE_2 0x0145 806 #define RT5663_TEST_MODE_3 0x0146 807 #define RT5663_TEST_MODE_4 0x0147 808 #define RT5663_TEST_MODE_5 0x0148 809 #define RT5663_STO_DRE_1 0x0160 810 #define RT5663_STO_DRE_2 0x0161 811 #define RT5663_STO_DRE_3 0x0162 812 #define RT5663_STO_DRE_4 0x0163 813 #define RT5663_STO_DRE_5 0x0164 814 #define RT5663_STO_DRE_6 0x0165 815 #define RT5663_STO_DRE_7 0x0166 816 #define RT5663_STO_DRE_8 0x0167 817 #define RT5663_STO_DRE_9 0x0168 818 #define RT5663_STO_DRE_10 0x0169 819 #define RT5663_MIC_DECRO_1 0x0180 820 #define RT5663_MIC_DECRO_2 0x0181 821 #define RT5663_MIC_DECRO_3 0x0182 822 #define RT5663_MIC_DECRO_4 0x0183 823 #define RT5663_MIC_DECRO_5 0x0184 824 #define RT5663_MIC_DECRO_6 0x0185 825 #define RT5663_HP_DECRO_1 0x01b0 826 #define RT5663_HP_DECRO_2 0x01b1 827 #define RT5663_HP_DECRO_3 0x01b2 828 #define RT5663_HP_DECRO_4 0x01b3 829 #define RT5663_HP_DECOUP 0x01b4 830 #define RT5663_HP_IMP_SEN_MAP8 0x01b5 831 #define RT5663_HP_IMP_SEN_MAP9 0x01b6 832 #define RT5663_HP_IMP_SEN_MAP10 0x01b7 833 #define RT5663_HP_IMP_SEN_MAP11 0x01b8 834 #define RT5663_HP_IMP_SEN_1 0x01c0 835 #define RT5663_HP_IMP_SEN_2 0x01c1 836 #define RT5663_HP_IMP_SEN_3 0x01c2 837 #define RT5663_HP_IMP_SEN_4 0x01c3 838 #define RT5663_HP_IMP_SEN_5 0x01c4 839 #define RT5663_HP_IMP_SEN_6 0x01c5 840 #define RT5663_HP_IMP_SEN_7 0x01c6 841 #define RT5663_HP_IMP_SEN_8 0x01c7 842 #define RT5663_HP_IMP_SEN_9 0x01c8 843 #define RT5663_HP_IMP_SEN_10 0x01c9 844 #define RT5663_HP_IMP_SEN_11 0x01ca 845 #define RT5663_HP_IMP_SEN_12 0x01cb 846 #define RT5663_HP_IMP_SEN_13 0x01cc 847 #define RT5663_HP_IMP_SEN_14 0x01cd 848 #define RT5663_HP_IMP_SEN_15 0x01ce 849 #define RT5663_HP_IMP_SEN_16 0x01cf 850 #define RT5663_HP_IMP_SEN_17 0x01d0 851 #define RT5663_HP_IMP_SEN_18 0x01d1 852 #define RT5663_HP_IMP_SEN_19 0x01d2 853 #define RT5663_HP_IMPSEN_DIG5 0x01d3 854 #define RT5663_HP_IMPSEN_MAP1 0x01d4 855 #define RT5663_HP_IMPSEN_MAP2 0x01d5 856 #define RT5663_HP_IMPSEN_MAP3 0x01d6 857 #define RT5663_HP_IMPSEN_MAP4 0x01d7 858 #define RT5663_HP_IMPSEN_MAP5 0x01d8 859 #define RT5663_HP_IMPSEN_MAP7 0x01d9 860 #define RT5663_HP_LOGIC_1 0x01da 861 #define RT5663_HP_LOGIC_2 0x01db 862 #define RT5663_HP_CALIB_1 0x01dd 863 #define RT5663_HP_CALIB_1_1 0x01de 864 #define RT5663_HP_CALIB_2 0x01df 865 #define RT5663_HP_CALIB_3 0x01e0 866 #define RT5663_HP_CALIB_4 0x01e1 867 #define RT5663_HP_CALIB_5 0x01e2 868 #define RT5663_HP_CALIB_5_1 0x01e3 869 #define RT5663_HP_CALIB_6 0x01e4 870 #define RT5663_HP_CALIB_7 0x01e5 871 #define RT5663_HP_CALIB_9 0x01e6 872 #define RT5663_HP_CALIB_10 0x01e7 873 #define RT5663_HP_CALIB_11 0x01e8 874 #define RT5663_HP_CALIB_ST1 0x01ea 875 #define RT5663_HP_CALIB_ST2 0x01eb 876 #define RT5663_HP_CALIB_ST3 0x01ec 877 #define RT5663_HP_CALIB_ST4 0x01ed 878 #define RT5663_HP_CALIB_ST5 0x01ee 879 #define RT5663_HP_CALIB_ST6 0x01ef 880 #define RT5663_HP_CALIB_ST7 0x01f0 881 #define RT5663_HP_CALIB_ST8 0x01f1 882 #define RT5663_HP_CALIB_ST9 0x01f2 883 #define RT5663_HP_AMP_DET 0x0200 884 #define RT5663_DUMMY_REG_6 0x0201 885 #define RT5663_HP_BIAS 0x0202 886 #define RT5663_CBJ_1 0x0250 887 #define RT5663_CBJ_2 0x0251 888 #define RT5663_CBJ_3 0x0252 889 #define RT5663_DUMMY_1 0x02fa 890 #define RT5663_DUMMY_2 0x02fb 891 #define RT5663_DUMMY_3 0x02fc 892 #define RT5663_ANA_JD 0x0300 893 #define RT5663_ADC_LCH_LPF1_A1 0x03d0 894 #define RT5663_ADC_RCH_LPF1_A1 0x03d1 895 #define RT5663_ADC_LCH_LPF1_H0 0x03d2 896 #define RT5663_ADC_RCH_LPF1_H0 0x03d3 897 #define RT5663_ADC_LCH_BPF1_A1 0x03d4 898 #define RT5663_ADC_RCH_BPF1_A1 0x03d5 899 #define RT5663_ADC_LCH_BPF1_A2 0x03d6 900 #define RT5663_ADC_RCH_BPF1_A2 0x03d7 901 #define RT5663_ADC_LCH_BPF1_H0 0x03d8 902 #define RT5663_ADC_RCH_BPF1_H0 0x03d9 903 #define RT5663_ADC_LCH_BPF2_A1 0x03da 904 #define RT5663_ADC_RCH_BPF2_A1 0x03db 905 #define RT5663_ADC_LCH_BPF2_A2 0x03dc 906 #define RT5663_ADC_RCH_BPF2_A2 0x03dd 907 #define RT5663_ADC_LCH_BPF2_H0 0x03de 908 #define RT5663_ADC_RCH_BPF2_H0 0x03df 909 #define RT5663_ADC_LCH_BPF3_A1 0x03e0 910 #define RT5663_ADC_RCH_BPF3_A1 0x03e1 911 #define RT5663_ADC_LCH_BPF3_A2 0x03e2 912 #define RT5663_ADC_RCH_BPF3_A2 0x03e3 913 #define RT5663_ADC_LCH_BPF3_H0 0x03e4 914 #define RT5663_ADC_RCH_BPF3_H0 0x03e5 915 #define RT5663_ADC_LCH_BPF4_A1 0x03e6 916 #define RT5663_ADC_RCH_BPF4_A1 0x03e7 917 #define RT5663_ADC_LCH_BPF4_A2 0x03e8 918 #define RT5663_ADC_RCH_BPF4_A2 0x03e9 919 #define RT5663_ADC_LCH_BPF4_H0 0x03ea 920 #define RT5663_ADC_RCH_BPF4_H0 0x03eb 921 #define RT5663_ADC_LCH_HPF1_A1 0x03ec 922 #define RT5663_ADC_RCH_HPF1_A1 0x03ed 923 #define RT5663_ADC_LCH_HPF1_H0 0x03ee 924 #define RT5663_ADC_RCH_HPF1_H0 0x03ef 925 #define RT5663_ADC_EQ_PRE_VOL_L 0x03f0 926 #define RT5663_ADC_EQ_PRE_VOL_R 0x03f1 927 #define RT5663_ADC_EQ_POST_VOL_L 0x03f2 928 #define RT5663_ADC_EQ_POST_VOL_R 0x03f3 929 930 /* RECMIX Control (0x0010) */ 931 #define RT5663_RECMIX1_BST1_MASK (0x1) 932 #define RT5663_RECMIX1_BST1_SHIFT 0 933 #define RT5663_RECMIX1_BST1_ON (0x0) 934 #define RT5663_RECMIX1_BST1_OFF (0x1) 935 936 /* Bypass Stereo1 DAC Mixer Control (0x002d) */ 937 #define RT5663_DACL1_SRC_MASK (0x1 << 3) 938 #define RT5663_DACL1_SRC_SHIFT 3 939 #define RT5663_DACR1_SRC_MASK (0x1 << 2) 940 #define RT5663_DACR1_SRC_SHIFT 2 941 942 /* TDM control 2 (0x0078) */ 943 #define RT5663_DATA_SWAP_ADCDAT1_MASK (0x3 << 14) 944 #define RT5663_DATA_SWAP_ADCDAT1_SHIFT 14 945 #define RT5663_DATA_SWAP_ADCDAT1_LR (0x0 << 14) 946 #define RT5663_DATA_SWAP_ADCDAT1_RL (0x1 << 14) 947 #define RT5663_DATA_SWAP_ADCDAT1_LL (0x2 << 14) 948 #define RT5663_DATA_SWAP_ADCDAT1_RR (0x3 << 14) 949 950 /* TDM control 5 (0x007b) */ 951 #define RT5663_TDM_LENGTN_MASK (0x3) 952 #define RT5663_TDM_LENGTN_SHIFT 0 953 #define RT5663_TDM_LENGTN_16 (0x0) 954 #define RT5663_TDM_LENGTN_20 (0x1) 955 #define RT5663_TDM_LENGTN_24 (0x2) 956 #define RT5663_TDM_LENGTN_32 (0x3) 957 958 /* PLL tracking mode 1 (0x0083) */ 959 #define RT5663_I2S1_ASRC_MASK (0x1 << 11) 960 #define RT5663_I2S1_ASRC_SHIFT 11 961 #define RT5663_DAC_STO1_ASRC_MASK (0x1 << 10) 962 #define RT5663_DAC_STO1_ASRC_SHIFT 10 963 #define RT5663_ADC_STO1_ASRC_MASK (0x1 << 3) 964 #define RT5663_ADC_STO1_ASRC_SHIFT 3 965 966 /* PLL tracking mode 2 (0x0084)*/ 967 #define RT5663_DA_STO1_TRACK_MASK (0x7 << 12) 968 #define RT5663_DA_STO1_TRACK_SHIFT 12 969 #define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12) 970 #define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12) 971 #define RT5663_AD_STO1_TRACK_MASK (0x7) 972 #define RT5663_AD_STO1_TRACK_SHIFT 0 973 #define RT5663_AD_STO1_TRACK_SYSCLK (0x0) 974 #define RT5663_AD_STO1_TRACK_I2S1 (0x1) 975 976 /* HPOUT Charge pump control 1 (0x0091) */ 977 #define RT5663_SI_HP_MASK (0x1 << 12) 978 #define RT5663_SI_HP_SHIFT 12 979 #define RT5663_SI_HP_EN (0x1 << 12) 980 #define RT5663_SI_HP_DIS (0x0 << 12) 981 982 /* GPIO Control 2 (0x00b6) */ 983 #define RT5663_GP1_PIN_CONF_MASK (0x1 << 2) 984 #define RT5663_GP1_PIN_CONF_SHIFT 2 985 #define RT5663_GP1_PIN_CONF_OUTPUT (0x1 << 2) 986 #define RT5663_GP1_PIN_CONF_INPUT (0x0 << 2) 987 988 /* GPIO Control 2 (0x00b7) */ 989 #define RT5663_EN_IRQ_INLINE_MASK (0x1 << 3) 990 #define RT5663_EN_IRQ_INLINE_SHIFT 3 991 #define RT5663_EN_IRQ_INLINE_NOR (0x1 << 3) 992 #define RT5663_EN_IRQ_INLINE_BYP (0x0 << 3) 993 994 /* GPIO Control 1 (0x00c0) */ 995 #define RT5663_GPIO1_TYPE_MASK (0x1 << 15) 996 #define RT5663_GPIO1_TYPE_SHIFT 15 997 #define RT5663_GPIO1_TYPE_EN (0x1 << 15) 998 #define RT5663_GPIO1_TYPE_DIS (0x0 << 15) 999 1000 /* IRQ Control 1 (0x00c1) */ 1001 #define RT5663_EN_IRQ_JD1_MASK (0x1 << 6) 1002 #define RT5663_EN_IRQ_JD1_SHIFT 6 1003 #define RT5663_EN_IRQ_JD1_EN (0x1 << 6) 1004 #define RT5663_EN_IRQ_JD1_DIS (0x0 << 6) 1005 #define RT5663_SEL_GPIO1_MASK (0x1 << 2) 1006 #define RT5663_SEL_GPIO1_SHIFT 6 1007 #define RT5663_SEL_GPIO1_EN (0x1 << 2) 1008 #define RT5663_SEL_GPIO1_DIS (0x0 << 2) 1009 1010 /* Inline Command Function 2 (0x00dc) */ 1011 #define RT5663_PWR_MIC_DET_MASK (0x1) 1012 #define RT5663_PWR_MIC_DET_SHIFT 0 1013 #define RT5663_PWR_MIC_DET_ON (0x1) 1014 #define RT5663_PWR_MIC_DET_OFF (0x0) 1015 1016 /* Embeeded Jack and Type Detection Control 1 (0x00e6)*/ 1017 #define RT5663_CBJ_DET_MASK (0x1 << 15) 1018 #define RT5663_CBJ_DET_SHIFT 15 1019 #define RT5663_CBJ_DET_DIS (0x0 << 15) 1020 #define RT5663_CBJ_DET_EN (0x1 << 15) 1021 #define RT5663_EXT_JD_MASK (0x1 << 11) 1022 #define RT5663_EXT_JD_SHIFT 11 1023 #define RT5663_EXT_JD_EN (0x1 << 11) 1024 #define RT5663_EXT_JD_DIS (0x0 << 11) 1025 #define RT5663_POL_EXT_JD_MASK (0x1 << 10) 1026 #define RT5663_POL_EXT_JD_SHIFT 10 1027 #define RT5663_POL_EXT_JD_EN (0x1 << 10) 1028 #define RT5663_POL_EXT_JD_DIS (0x0 << 10) 1029 #define RT5663_EM_JD_MASK (0x1 << 7) 1030 #define RT5663_EM_JD_SHIFT 7 1031 #define RT5663_EM_JD_NOR (0x1 << 7) 1032 #define RT5663_EM_JD_RST (0x0 << 7) 1033 1034 /* DACREF LDO Control (0x0112)*/ 1035 #define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9) 1036 #define RT5663_PWR_LDO_DACREFL_SHIFT 9 1037 #define RT5663_PWR_LDO_DACREFR_MASK (0x1 << 1) 1038 #define RT5663_PWR_LDO_DACREFR_SHIFT 1 1039 1040 /* Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/ 1041 #define RT5663_DRE_GAIN_HP_MASK (0x1f) 1042 #define RT5663_DRE_GAIN_HP_SHIFT 0 1043 1044 /* Combo Jack Control (0x0250) */ 1045 #define RT5663_INBUF_CBJ_BST1_MASK (0x1 << 11) 1046 #define RT5663_INBUF_CBJ_BST1_SHIFT 11 1047 #define RT5663_INBUF_CBJ_BST1_ON (0x1 << 11) 1048 #define RT5663_INBUF_CBJ_BST1_OFF (0x0 << 11) 1049 #define RT5663_CBJ_SENSE_BST1_MASK (0x1 << 10) 1050 #define RT5663_CBJ_SENSE_BST1_SHIFT 10 1051 #define RT5663_CBJ_SENSE_BST1_L (0x1 << 10) 1052 #define RT5663_CBJ_SENSE_BST1_R (0x0 << 10) 1053 1054 /* Combo Jack Control (0x0251) */ 1055 #define RT5663_GAIN_BST1_MASK (0xf) 1056 #define RT5663_GAIN_BST1_SHIFT 0 1057 1058 /* Dummy register 1 (0x02fa) */ 1059 #define RT5663_EMB_CLK_MASK (0x1 << 9) 1060 #define RT5663_EMB_CLK_SHIFT 9 1061 #define RT5663_EMB_CLK_EN (0x1 << 9) 1062 #define RT5663_EMB_CLK_DIS (0x0 << 9) 1063 #define RT5663_HPA_CPL_BIAS_MASK (0x7 << 6) 1064 #define RT5663_HPA_CPL_BIAS_SHIFT 6 1065 #define RT5663_HPA_CPL_BIAS_0_5 (0x0 << 6) 1066 #define RT5663_HPA_CPL_BIAS_1 (0x1 << 6) 1067 #define RT5663_HPA_CPL_BIAS_2 (0x2 << 6) 1068 #define RT5663_HPA_CPL_BIAS_3 (0x3 << 6) 1069 #define RT5663_HPA_CPL_BIAS_4_1 (0x4 << 6) 1070 #define RT5663_HPA_CPL_BIAS_4_2 (0x5 << 6) 1071 #define RT5663_HPA_CPL_BIAS_6 (0x6 << 6) 1072 #define RT5663_HPA_CPL_BIAS_8 (0x7 << 6) 1073 #define RT5663_HPA_CPR_BIAS_MASK (0x7 << 3) 1074 #define RT5663_HPA_CPR_BIAS_SHIFT 3 1075 #define RT5663_HPA_CPR_BIAS_0_5 (0x0 << 3) 1076 #define RT5663_HPA_CPR_BIAS_1 (0x1 << 3) 1077 #define RT5663_HPA_CPR_BIAS_2 (0x2 << 3) 1078 #define RT5663_HPA_CPR_BIAS_3 (0x3 << 3) 1079 #define RT5663_HPA_CPR_BIAS_4_1 (0x4 << 3) 1080 #define RT5663_HPA_CPR_BIAS_4_2 (0x5 << 3) 1081 #define RT5663_HPA_CPR_BIAS_6 (0x6 << 3) 1082 #define RT5663_HPA_CPR_BIAS_8 (0x7 << 3) 1083 #define RT5663_DUMMY_BIAS_MASK (0x7) 1084 #define RT5663_DUMMY_BIAS_SHIFT 0 1085 #define RT5663_DUMMY_BIAS_0_5 (0x0) 1086 #define RT5663_DUMMY_BIAS_1 (0x1) 1087 #define RT5663_DUMMY_BIAS_2 (0x2) 1088 #define RT5663_DUMMY_BIAS_3 (0x3) 1089 #define RT5663_DUMMY_BIAS_4_1 (0x4) 1090 #define RT5663_DUMMY_BIAS_4_2 (0x5) 1091 #define RT5663_DUMMY_BIAS_6 (0x6) 1092 #define RT5663_DUMMY_BIAS_8 (0x7) 1093 1094 1095 /* System Clock Source */ 1096 enum { 1097 RT5663_SCLK_S_MCLK, 1098 RT5663_SCLK_S_PLL1, 1099 RT5663_SCLK_S_RCCLK, 1100 }; 1101 1102 /* PLL1 Source */ 1103 enum { 1104 RT5663_PLL1_S_MCLK, 1105 RT5663_PLL1_S_BCLK1, 1106 }; 1107 1108 enum { 1109 RT5663_AIF, 1110 RT5663_AIFS, 1111 }; 1112 1113 /* asrc clock source */ 1114 enum { 1115 RT5663_CLK_SEL_SYS = 0x0, 1116 RT5663_CLK_SEL_I2S1_ASRC = 0x1, 1117 }; 1118 1119 /* filter mask */ 1120 enum { 1121 RT5663_DA_STEREO_FILTER = 0x1, 1122 RT5663_AD_STEREO_FILTER = 0x2, 1123 }; 1124 1125 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component, 1126 unsigned int filter_mask, unsigned int clk_src); 1127 1128 #endif /* __RT5663_H__ */ 1129
