1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 *
6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */
10
11 #ifndef _UFSHCI_H
12 #define _UFSHCI_H
13
14 enum {
15 TASK_REQ_UPIU_SIZE_DWORDS = 8,
16 TASK_RSP_UPIU_SIZE_DWORDS = 8,
17 ALIGNED_UPIU_SIZE = 512,
18 };
19
20 /* UFSHCI Registers */
21 enum {
22 REG_CONTROLLER_CAPABILITIES = 0x00,
23 REG_UFS_VERSION = 0x08,
24 REG_CONTROLLER_DEV_ID = 0x10,
25 REG_CONTROLLER_PROD_ID = 0x14,
26 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
27 REG_INTERRUPT_STATUS = 0x20,
28 REG_INTERRUPT_ENABLE = 0x24,
29 REG_CONTROLLER_STATUS = 0x30,
30 REG_CONTROLLER_ENABLE = 0x34,
31 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
32 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
33 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
34 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
35 REG_UIC_ERROR_CODE_DME = 0x48,
36 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
37 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
38 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
39 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
40 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
41 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
42 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
43 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
44 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
45 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
46 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
47 REG_UIC_COMMAND = 0x90,
48 REG_UIC_COMMAND_ARG_1 = 0x94,
49 REG_UIC_COMMAND_ARG_2 = 0x98,
50 REG_UIC_COMMAND_ARG_3 = 0x9C,
51
52 UFSHCI_REG_SPACE_SIZE = 0xA0,
53
54 REG_UFS_CCAP = 0x100,
55 REG_UFS_CRYPTOCAP = 0x104,
56
57 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
58 };
59
60 /* Controller capability masks */
61 enum {
62 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
63 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
64 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
65 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
66 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
67 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
68 MASK_CRYPTO_SUPPORT = 0x10000000,
69 };
70
71 #define UFS_MASK(mask, offset) ((mask) << (offset))
72
73 /* UFS Version 08h */
74 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
75 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
76
77 /*
78 * Controller UFSHCI version
79 * - 2.x and newer use the following scheme:
80 * major << 8 + minor << 4
81 * - 1.x has been converted to match this in
82 * ufshcd_get_ufs_version()
83 */
ufshci_version(u32 major,u32 minor)84 static inline u32 ufshci_version(u32 major, u32 minor)
85 {
86 return (major << 8) + (minor << 4);
87 }
88
89 /*
90 * HCDDID - Host Controller Identification Descriptor
91 * - Device ID and Device Class 10h
92 */
93 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
94 #define DEVICE_ID UFS_MASK(0xFF, 24)
95
96 /*
97 * HCPMID - Host Controller Identification Descriptor
98 * - Product/Manufacturer ID 14h
99 */
100 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
101 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
102
103 /* AHIT - Auto-Hibernate Idle Timer */
104 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
105 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
106 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
107 #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
108
109 /*
110 * IS - Interrupt Status - 20h
111 */
112 #define UTP_TRANSFER_REQ_COMPL 0x1
113 #define UIC_DME_END_PT_RESET 0x2
114 #define UIC_ERROR 0x4
115 #define UIC_TEST_MODE 0x8
116 #define UIC_POWER_MODE 0x10
117 #define UIC_HIBERNATE_EXIT 0x20
118 #define UIC_HIBERNATE_ENTER 0x40
119 #define UIC_LINK_LOST 0x80
120 #define UIC_LINK_STARTUP 0x100
121 #define UTP_TASK_REQ_COMPL 0x200
122 #define UIC_COMMAND_COMPL 0x400
123 #define DEVICE_FATAL_ERROR 0x800
124 #define CONTROLLER_FATAL_ERROR 0x10000
125 #define SYSTEM_BUS_FATAL_ERROR 0x20000
126 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000
127
128 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
129 UIC_HIBERNATE_EXIT)
130
131 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
132 UIC_POWER_MODE)
133
134 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
135
136 #define UFSHCD_ERROR_MASK (UIC_ERROR |\
137 DEVICE_FATAL_ERROR |\
138 CONTROLLER_FATAL_ERROR |\
139 SYSTEM_BUS_FATAL_ERROR |\
140 CRYPTO_ENGINE_FATAL_ERROR)
141
142 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
143 CONTROLLER_FATAL_ERROR |\
144 SYSTEM_BUS_FATAL_ERROR |\
145 CRYPTO_ENGINE_FATAL_ERROR)
146
147 /* HCS - Host Controller Status 30h */
148 #define DEVICE_PRESENT 0x1
149 #define UTP_TRANSFER_REQ_LIST_READY 0x2
150 #define UTP_TASK_REQ_LIST_READY 0x4
151 #define UIC_COMMAND_READY 0x8
152 #define HOST_ERROR_INDICATOR 0x10
153 #define DEVICE_ERROR_INDICATOR 0x20
154 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
155
156 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
157 UTP_TASK_REQ_LIST_READY |\
158 UIC_COMMAND_READY)
159
160 enum {
161 PWR_OK = 0x0,
162 PWR_LOCAL = 0x01,
163 PWR_REMOTE = 0x02,
164 PWR_BUSY = 0x03,
165 PWR_ERROR_CAP = 0x04,
166 PWR_FATAL_ERROR = 0x05,
167 };
168
169 /* HCE - Host Controller Enable 34h */
170 #define CONTROLLER_ENABLE 0x1
171 #define CONTROLLER_DISABLE 0x0
172 #define CRYPTO_GENERAL_ENABLE 0x2
173
174 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
175 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
176 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
177 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
178 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
179
180 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
181 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
182 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
183 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
184 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
185 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
186 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
187 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
188 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
189 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
190
191 /* UECN - Host UIC Error Code Network Layer 40h */
192 #define UIC_NETWORK_LAYER_ERROR 0x80000000
193 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
194 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
195 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
196 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
197
198 /* UECT - Host UIC Error Code Transport Layer 44h */
199 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
200 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
201 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
202 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
203 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
204 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
205 #define UIC_TRANSPORT_BAD_TC 0x10
206 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
207 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
208
209 /* UECDME - Host UIC Error Code DME 48h */
210 #define UIC_DME_ERROR 0x80000000
211 #define UIC_DME_ERROR_CODE_MASK 0x1
212
213 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
214 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
215 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
216 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
217 #define INT_AGGR_STATUS_BIT 0x100000
218 #define INT_AGGR_PARAM_WRITE 0x1000000
219 #define INT_AGGR_ENABLE 0x80000000
220
221 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
222 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
223
224 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
225 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
226
227 /* UICCMD - UIC Command */
228 #define COMMAND_OPCODE_MASK 0xFF
229 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
230
231 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
232 #define RESET_LEVEL 0xFF
233
234 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
235 #define CONFIG_RESULT_CODE_MASK 0xFF
236 #define GENERIC_ERROR_CODE_MASK 0xFF
237
238 /* GenSelectorIndex calculation macros for M-PHY attributes */
239 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
240 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
241
242 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
243 ((sel) & 0xFFFF))
244 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
245 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
246 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
247
248 /* Link Status*/
249 enum link_status {
250 UFSHCD_LINK_IS_DOWN = 1,
251 UFSHCD_LINK_IS_UP = 2,
252 };
253
254 /* UIC Commands */
255 enum uic_cmd_dme {
256 UIC_CMD_DME_GET = 0x01,
257 UIC_CMD_DME_SET = 0x02,
258 UIC_CMD_DME_PEER_GET = 0x03,
259 UIC_CMD_DME_PEER_SET = 0x04,
260 UIC_CMD_DME_POWERON = 0x10,
261 UIC_CMD_DME_POWEROFF = 0x11,
262 UIC_CMD_DME_ENABLE = 0x12,
263 UIC_CMD_DME_RESET = 0x14,
264 UIC_CMD_DME_END_PT_RST = 0x15,
265 UIC_CMD_DME_LINK_STARTUP = 0x16,
266 UIC_CMD_DME_HIBER_ENTER = 0x17,
267 UIC_CMD_DME_HIBER_EXIT = 0x18,
268 UIC_CMD_DME_TEST_MODE = 0x1A,
269 };
270
271 /* UIC Config result code / Generic error code */
272 enum {
273 UIC_CMD_RESULT_SUCCESS = 0x00,
274 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
275 UIC_CMD_RESULT_FAILURE = 0x01,
276 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
277 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
278 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
279 UIC_CMD_RESULT_BAD_INDEX = 0x05,
280 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
281 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
282 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
283 UIC_CMD_RESULT_BUSY = 0x09,
284 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
285 };
286
287 #define MASK_UIC_COMMAND_RESULT 0xFF
288
289 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
290 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
291
292 /* Interrupt disable masks */
293 enum {
294 /* Interrupt disable mask for UFSHCI v1.0 */
295 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
296 INTERRUPT_MASK_RW_VER_10 = 0x30000,
297
298 /* Interrupt disable mask for UFSHCI v1.1 */
299 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
300
301 /* Interrupt disable mask for UFSHCI v2.1 */
302 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
303 };
304
305 /* CCAP - Crypto Capability 100h */
306 union ufs_crypto_capabilities {
307 __le32 reg_val;
308 struct {
309 u8 num_crypto_cap;
310 u8 config_count;
311 u8 reserved;
312 u8 config_array_ptr;
313 };
314 };
315
316 enum ufs_crypto_key_size {
317 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
318 UFS_CRYPTO_KEY_SIZE_128 = 0x1,
319 UFS_CRYPTO_KEY_SIZE_192 = 0x2,
320 UFS_CRYPTO_KEY_SIZE_256 = 0x3,
321 UFS_CRYPTO_KEY_SIZE_512 = 0x4,
322 };
323
324 enum ufs_crypto_alg {
325 UFS_CRYPTO_ALG_AES_XTS = 0x0,
326 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
327 UFS_CRYPTO_ALG_AES_ECB = 0x2,
328 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
329 };
330
331 /* x-CRYPTOCAP - Crypto Capability X */
332 union ufs_crypto_cap_entry {
333 __le32 reg_val;
334 struct {
335 u8 algorithm_id;
336 u8 sdus_mask; /* Supported data unit size mask */
337 u8 key_size;
338 u8 reserved;
339 };
340 };
341
342 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
343 #define UFS_CRYPTO_KEY_MAX_SIZE 64
344 /* x-CRYPTOCFG - Crypto Configuration X */
345 union ufs_crypto_cfg_entry {
346 __le32 reg_val[32];
347 struct {
348 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
349 u8 data_unit_size;
350 u8 crypto_cap_idx;
351 u8 reserved_1;
352 u8 config_enable;
353 u8 reserved_multi_host;
354 u8 reserved_2;
355 u8 vsb[2];
356 u8 reserved_3[56];
357 };
358 };
359
360 /*
361 * Request Descriptor Definitions
362 */
363
364 /* Transfer request command type */
365 enum {
366 UTP_CMD_TYPE_SCSI = 0x0,
367 UTP_CMD_TYPE_UFS = 0x1,
368 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
369 };
370
371 /* To accommodate UFS2.0 required Command type */
372 enum {
373 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
374 };
375
376 enum {
377 UTP_SCSI_COMMAND = 0x00000000,
378 UTP_NATIVE_UFS_COMMAND = 0x10000000,
379 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
380 UTP_REQ_DESC_INT_CMD = 0x01000000,
381 UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
382 };
383
384 /* UTP Transfer Request Data Direction (DD) */
385 enum {
386 UTP_NO_DATA_TRANSFER = 0x00000000,
387 UTP_HOST_TO_DEVICE = 0x02000000,
388 UTP_DEVICE_TO_HOST = 0x04000000,
389 };
390
391 /* Overall command status values */
392 enum {
393 OCS_SUCCESS = 0x0,
394 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
395 OCS_INVALID_PRDT_ATTR = 0x2,
396 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
397 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
398 OCS_PEER_COMM_FAILURE = 0x5,
399 OCS_ABORTED = 0x6,
400 OCS_FATAL_ERROR = 0x7,
401 OCS_DEVICE_FATAL_ERROR = 0x8,
402 OCS_INVALID_CRYPTO_CONFIG = 0x9,
403 OCS_GENERAL_CRYPTO_ERROR = 0xA,
404 OCS_INVALID_COMMAND_STATUS = 0x0F,
405 MASK_OCS = 0x0F,
406 };
407
408 /* The maximum length of the data byte count field in the PRDT is 256KB */
409 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
410 /* The granularity of the data byte count field in the PRDT is 32-bit */
411 #define PRDT_DATA_BYTE_COUNT_PAD 4
412
413 /**
414 * struct ufshcd_sg_entry - UFSHCI PRD Entry
415 * @base_addr: Lower 32bit physical address DW-0
416 * @upper_addr: Upper 32bit physical address DW-1
417 * @reserved: Reserved for future use DW-2
418 * @size: size of physical segment DW-3
419 */
420 struct ufshcd_sg_entry {
421 __le32 base_addr;
422 __le32 upper_addr;
423 __le32 reserved;
424 __le32 size;
425 };
426
427 /**
428 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
429 * @command_upiu: Command UPIU Frame address
430 * @response_upiu: Response UPIU Frame address
431 * @prd_table: Physical Region Descriptor
432 */
433 struct utp_transfer_cmd_desc {
434 u8 command_upiu[ALIGNED_UPIU_SIZE];
435 u8 response_upiu[ALIGNED_UPIU_SIZE];
436 struct ufshcd_sg_entry prd_table[SG_ALL];
437 };
438
439 /**
440 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
441 * @dword0: Descriptor Header DW0
442 * @dword1: Descriptor Header DW1
443 * @dword2: Descriptor Header DW2
444 * @dword3: Descriptor Header DW3
445 */
446 struct request_desc_header {
447 __le32 dword_0;
448 __le32 dword_1;
449 __le32 dword_2;
450 __le32 dword_3;
451 };
452
453 /**
454 * struct utp_transfer_req_desc - UTRD structure
455 * @header: UTRD header DW-0 to DW-3
456 * @command_desc_base_addr_lo: UCD base address low DW-4
457 * @command_desc_base_addr_hi: UCD base address high DW-5
458 * @response_upiu_length: response UPIU length DW-6
459 * @response_upiu_offset: response UPIU offset DW-6
460 * @prd_table_length: Physical region descriptor length DW-7
461 * @prd_table_offset: Physical region descriptor offset DW-7
462 */
463 struct utp_transfer_req_desc {
464
465 /* DW 0-3 */
466 struct request_desc_header header;
467
468 /* DW 4-5*/
469 __le32 command_desc_base_addr_lo;
470 __le32 command_desc_base_addr_hi;
471
472 /* DW 6 */
473 __le16 response_upiu_length;
474 __le16 response_upiu_offset;
475
476 /* DW 7 */
477 __le16 prd_table_length;
478 __le16 prd_table_offset;
479 };
480
481 /*
482 * UTMRD structure.
483 */
484 struct utp_task_req_desc {
485 /* DW 0-3 */
486 struct request_desc_header header;
487
488 /* DW 4-11 - Task request UPIU structure */
489 struct {
490 struct utp_upiu_header req_header;
491 __be32 input_param1;
492 __be32 input_param2;
493 __be32 input_param3;
494 __be32 __reserved1[2];
495 } upiu_req;
496
497 /* DW 12-19 - Task Management Response UPIU structure */
498 struct {
499 struct utp_upiu_header rsp_header;
500 __be32 output_param1;
501 __be32 output_param2;
502 __be32 __reserved2[3];
503 } upiu_rsp;
504 };
505
506 #endif /* End of Header */
507
