1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 /* ************************************************************ 15 * File Name: odm_reg.h 16 * 17 * Description: 18 * 19 * This file is for general register definition. 20 * 21 * 22 * *************************************************************/ 23 #ifndef __HAL_ODM_REG_H__ 24 #define __HAL_ODM_REG_H__ 25 26 /* 27 * Register Definition 28 */ 29 30 /* MAC REG */ 31 #define ODM_BB_RESET 0x002 32 #define ODM_DUMMY 0x4fe 33 #define RF_T_METER_OLD 0x24 34 #define RF_T_METER_NEW 0x42 35 36 #define ODM_EDCA_VO_PARAM 0x500 37 #define ODM_EDCA_VI_PARAM 0x504 38 #define ODM_EDCA_BE_PARAM 0x508 39 #define ODM_EDCA_BK_PARAM 0x50C 40 #define ODM_TXPAUSE 0x522 41 42 /* LTE_COEX */ 43 #define REG_LTECOEX_CTRL 0x07C0 44 #define REG_LTECOEX_WRITE_DATA 0x07C4 45 #define REG_LTECOEX_READ_DATA 0x07C8 46 #define REG_LTECOEX_PATH_CONTROL 0x70 47 48 /* BB REG */ 49 #define ODM_FPGA_PHY0_PAGE8 0x800 50 #define ODM_PSD_SETTING 0x808 51 #define ODM_AFE_SETTING 0x818 52 #define ODM_TXAGC_B_6_18 0x830 53 #define ODM_TXAGC_B_24_54 0x834 54 #define ODM_TXAGC_B_MCS32_5 0x838 55 #define ODM_TXAGC_B_MCS0_MCS3 0x83c 56 #define ODM_TXAGC_B_MCS4_MCS7 0x848 57 #define ODM_TXAGC_B_MCS8_MCS11 0x84c 58 #define ODM_ANALOG_REGISTER 0x85c 59 #define ODM_RF_INTERFACE_OUTPUT 0x860 60 #define ODM_TXAGC_B_MCS12_MCS15 0x868 61 #define ODM_TXAGC_B_11_A_2_11 0x86c 62 #define ODM_AD_DA_LSB_MASK 0x874 63 #define ODM_ENABLE_3_WIRE 0x88c 64 #define ODM_PSD_REPORT 0x8b4 65 #define ODM_R_ANT_SELECT 0x90c 66 #define ODM_CCK_ANT_SELECT 0xa07 67 #define ODM_CCK_PD_THRESH 0xa0a 68 #define ODM_CCK_RF_REG1 0xa11 69 #define ODM_CCK_MATCH_FILTER 0xa20 70 #define ODM_CCK_RAKE_MAC 0xa2e 71 #define ODM_CCK_CNT_RESET 0xa2d 72 #define ODM_CCK_TX_DIVERSITY 0xa2f 73 #define ODM_CCK_FA_CNT_MSB 0xa5b 74 #define ODM_CCK_FA_CNT_LSB 0xa5c 75 #define ODM_CCK_NEW_FUNCTION 0xa75 76 #define ODM_OFDM_PHY0_PAGE_C 0xc00 77 #define ODM_OFDM_RX_ANT 0xc04 78 #define ODM_R_A_RXIQI 0xc14 79 #define ODM_R_A_AGC_CORE1 0xc50 80 #define ODM_R_A_AGC_CORE2 0xc54 81 #define ODM_R_B_AGC_CORE1 0xc58 82 #define ODM_R_AGC_PAR 0xc70 83 #define ODM_R_HTSTF_AGC_PAR 0xc7c 84 #define ODM_TX_PWR_TRAINING_A 0xc90 85 #define ODM_TX_PWR_TRAINING_B 0xc98 86 #define ODM_OFDM_FA_CNT1 0xcf0 87 #define ODM_OFDM_PHY0_PAGE_D 0xd00 88 #define ODM_OFDM_FA_CNT2 0xda0 89 #define ODM_OFDM_FA_CNT3 0xda4 90 #define ODM_OFDM_FA_CNT4 0xda8 91 #define ODM_TXAGC_A_6_18 0xe00 92 #define ODM_TXAGC_A_24_54 0xe04 93 #define ODM_TXAGC_A_1_MCS32 0xe08 94 #define ODM_TXAGC_A_MCS0_MCS3 0xe10 95 #define ODM_TXAGC_A_MCS4_MCS7 0xe14 96 #define ODM_TXAGC_A_MCS8_MCS11 0xe18 97 #define ODM_TXAGC_A_MCS12_MCS15 0xe1c 98 99 /* RF REG */ 100 #define ODM_GAIN_SETTING 0x00 101 #define ODM_CHANNEL 0x18 102 #define ODM_RF_T_METER 0x24 103 #define ODM_RF_T_METER_92D 0x42 104 #define ODM_RF_T_METER_88E 0x42 105 #define ODM_RF_T_METER_92E 0x42 106 #define ODM_RF_T_METER_8812 0x42 107 #define REG_RF_TX_GAIN_OFFSET 0x55 108 109 /* ant Detect Reg */ 110 #define ODM_DPDT 0x300 111 112 /* PSD Init */ 113 #define ODM_PSDREG 0x808 114 115 /* 92D path Div */ 116 #define PATHDIV_REG 0xB30 117 #define PATHDIV_TRI 0xBA0 118 119 /* 120 * Bitmap Definition 121 */ 122 123 #define BIT_FA_RESET BIT(0) 124 125 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0xC80 126 #define REG_OFDM_0_ECCA_THRESHOLD 0xC4C 127 #define REG_FPGA0_XB_LSSI_READ_BACK 0x8A4 128 #define REG_FPGA0_TX_GAIN_STAGE 0x80C 129 #define REG_OFDM_0_XA_AGC_CORE1 0xC50 130 #define REG_OFDM_0_XB_AGC_CORE1 0xC58 131 #define REG_A_TX_SCALE_JAGUAR 0xC1C 132 #define REG_B_TX_SCALE_JAGUAR 0xE1C 133 134 #define REG_AFE_XTAL_CTRL 0x0024 135 #define REG_AFE_PLL_CTRL 0x0028 136 #define REG_MAC_PHY_CTRL 0x002C 137 138 #define RF_CHNLBW 0x18 139 140 #endif 141
