1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 15 #ifndef __PHYDMRAINFO_H__ 16 #define __PHYDMRAINFO_H__ 17 18 /*#define RAINFO_VERSION "2.0"*/ /*2014.11.04*/ 19 /*#define RAINFO_VERSION "3.0"*/ /*2015.01.13 Dino*/ 20 /*#define RAINFO_VERSION "3.1"*/ /*2015.01.14 Dino*/ 21 /*#define RAINFO_VERSION "3.3"*/ /*2015.07.29 YuChen*/ 22 /*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/ 23 /*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask 24 *state and Phydm-lize partial ra mask 25 *function 26 */ 27 /*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to 28 *adjust PCR RA threshold 29 */ 30 /*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */ 31 #define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem*/ 32 33 #define FORCED_UPDATE_RAMASK_PERIOD 5 34 35 #define H2C_0X42_LENGTH 5 36 #define H2C_MAX_LENGTH 7 37 38 #define RA_FLOOR_UP_GAP 3 39 #define RA_FLOOR_TABLE_SIZE 7 40 41 #define ACTIVE_TP_THRESHOLD 150 42 #define RA_RETRY_DESCEND_NUM 2 43 #define RA_RETRY_LIMIT_LOW 4 44 #define RA_RETRY_LIMIT_HIGH 32 45 46 #define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */ 47 #define RAINFO_STBC_STATE BIT(1) 48 /* #define RAINFO_LDPC_STATE BIT2 */ 49 #define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */ 50 #define RAINFO_SHURTCUT_STATE BIT(3) 51 #define RAINFO_SHURTCUT_FLAG BIT(4) 52 #define RAINFO_INIT_RSSI_RATE_STATE BIT(5) 53 #define RAINFO_BF_STATE BIT(6) 54 #define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */ 55 56 #define RA_MASK_CCK 0xf 57 #define RA_MASK_OFDM 0xff0 58 #define RA_MASK_HT1SS 0xff000 59 #define RA_MASK_HT2SS 0xff00000 60 /*#define RA_MASK_MCS3SS */ 61 #define RA_MASK_HT4SS 0xff0 62 #define RA_MASK_VHT1SS 0x3ff000 63 #define RA_MASK_VHT2SS 0xffc00000 64 65 #define RA_FIRST_MACID 0 66 67 #define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init 68 69 #define DM_RATR_STA_INIT 0 70 #define DM_RATR_STA_HIGH 1 71 #define DM_RATR_STA_MIDDLE 2 72 #define DM_RATR_STA_LOW 3 73 #define DM_RATR_STA_ULTRA_LOW 4 74 75 enum phydm_ra_arfr_num { 76 ARFR_0_RATE_ID = 0x9, 77 ARFR_1_RATE_ID = 0xa, 78 ARFR_2_RATE_ID = 0xb, 79 ARFR_3_RATE_ID = 0xc, 80 ARFR_4_RATE_ID = 0xd, 81 ARFR_5_RATE_ID = 0xe 82 }; 83 84 enum phydm_ra_dbg_para { 85 RADBG_PCR_TH_OFFSET = 0, 86 RADBG_RTY_PENALTY = 1, 87 RADBG_N_HIGH = 2, 88 RADBG_N_LOW = 3, 89 RADBG_TRATE_UP_TABLE = 4, 90 RADBG_TRATE_DOWN_TABLE = 5, 91 RADBG_TRYING_NECESSARY = 6, 92 RADBG_TDROPING_NECESSARY = 7, 93 RADBG_RATE_UP_RTY_RATIO = 8, 94 RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ 95 96 RADBG_DEBUG_MONITOR1 = 0xc, 97 RADBG_DEBUG_MONITOR2 = 0xd, 98 RADBG_DEBUG_MONITOR3 = 0xe, 99 RADBG_DEBUG_MONITOR4 = 0xf, 100 RADBG_DEBUG_MONITOR5 = 0x10, 101 NUM_RA_PARA 102 }; 103 104 enum phydm_wireless_mode { 105 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, 106 PHYDM_WIRELESS_MODE_A = 0x01, 107 PHYDM_WIRELESS_MODE_B = 0x02, 108 PHYDM_WIRELESS_MODE_G = 0x04, 109 PHYDM_WIRELESS_MODE_AUTO = 0x08, 110 PHYDM_WIRELESS_MODE_N_24G = 0x10, 111 PHYDM_WIRELESS_MODE_N_5G = 0x20, 112 PHYDM_WIRELESS_MODE_AC_5G = 0x40, 113 PHYDM_WIRELESS_MODE_AC_24G = 0x80, 114 PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, 115 PHYDM_WIRELESS_MODE_MAX = 0x800, 116 PHYDM_WIRELESS_MODE_ALL = 0xFFFF 117 }; 118 119 enum phydm_rateid_idx { 120 PHYDM_BGN_40M_2SS = 0, 121 PHYDM_BGN_40M_1SS = 1, 122 PHYDM_BGN_20M_2SS = 2, 123 PHYDM_BGN_20M_1SS = 3, 124 PHYDM_GN_N2SS = 4, 125 PHYDM_GN_N1SS = 5, 126 PHYDM_BG = 6, 127 PHYDM_G = 7, 128 PHYDM_B_20M = 8, 129 PHYDM_ARFR0_AC_2SS = 9, 130 PHYDM_ARFR1_AC_1SS = 10, 131 PHYDM_ARFR2_AC_2G_1SS = 11, 132 PHYDM_ARFR3_AC_2G_2SS = 12, 133 PHYDM_ARFR4_AC_3SS = 13, 134 PHYDM_ARFR5_N_3SS = 14 135 }; 136 137 enum phydm_rf_type_def { 138 PHYDM_RF_1T1R = 0, 139 PHYDM_RF_1T2R, 140 PHYDM_RF_2T2R, 141 PHYDM_RF_2T2R_GREEN, 142 PHYDM_RF_2T3R, 143 PHYDM_RF_2T4R, 144 PHYDM_RF_3T3R, 145 PHYDM_RF_3T4R, 146 PHYDM_RF_4T4R, 147 PHYDM_RF_MAX_TYPE 148 }; 149 150 enum phydm_bw { 151 PHYDM_BW_20 = 0, 152 PHYDM_BW_40, 153 PHYDM_BW_80, 154 PHYDM_BW_80_80, 155 PHYDM_BW_160, 156 PHYDM_BW_10, 157 PHYDM_BW_5 158 }; 159 160 struct ra_table { 161 u8 firstconnect; 162 163 u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; 164 u8 highest_client_tx_order; 165 u16 highest_client_tx_rate_order; 166 u8 power_tracking_flag; 167 u8 RA_threshold_offset; 168 u8 RA_offset_direction; 169 u8 force_update_ra_mask_count; 170 }; 171 172 struct odm_rate_adaptive { 173 /* dm_type_by_fw/dm_type_by_driver */ 174 u8 type; 175 /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */ 176 u8 high_rssi_thresh; 177 /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */ 178 u8 low_rssi_thresh; 179 /* Cur RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW*/ 180 u8 ratr_state; 181 182 /* if RSSI > ldpc_thres => switch from LPDC to BCC */ 183 u8 ldpc_thres; 184 bool is_lower_rts_rate; 185 186 bool is_use_ldpc; 187 }; 188 189 void phydm_h2C_debug(void *dm_void, u32 *const dm_value, u32 *_used, 190 char *output, u32 *_out_len); 191 192 void phydm_RA_debug_PCR(void *dm_void, u32 *const dm_value, u32 *_used, 193 char *output, u32 *_out_len); 194 195 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); 196 197 void odm_ra_para_adjust(void *dm_void); 198 199 void phydm_ra_dynamic_retry_count(void *dm_void); 200 201 void phydm_ra_dynamic_retry_limit(void *dm_void); 202 203 void phydm_ra_dynamic_rate_id_on_assoc(void *dm_void, u8 wireless_mode, 204 u8 init_rate_id); 205 206 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component); 207 208 void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); 209 210 u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx); 211 212 void phydm_ra_info_watchdog(void *dm_void); 213 214 void phydm_ra_info_init(void *dm_void); 215 216 void odm_rssi_monitor_init(void *dm_void); 217 218 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 RA_offset_direction, 219 u8 RA_threshold_offset); 220 221 void odm_rssi_monitor_check(void *dm_void); 222 223 void phydm_init_ra_info(void *dm_void); 224 225 u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode); 226 227 u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw); 228 229 void phydm_update_hal_ra_mask(void *dm_void, u32 wireless_mode, u8 rf_type, 230 u8 BW, u8 mimo_ps_enable, u8 disable_cck_rate, 231 u32 *ratr_bitmap_msb_in, u32 *ratr_bitmap_in, 232 u8 tx_rate_level); 233 234 void odm_rate_adaptive_mask_init(void *dm_void); 235 236 void odm_refresh_rate_adaptive_mask(void *dm_void); 237 238 void odm_refresh_rate_adaptive_mask_mp(void *dm_void); 239 240 void odm_refresh_rate_adaptive_mask_ce(void *dm_void); 241 242 void odm_refresh_rate_adaptive_mask_apadsl(void *dm_void); 243 244 u8 phydm_RA_level_decision(void *dm_void, u32 rssi, u8 ratr_state); 245 246 bool odm_ra_state_check(void *dm_void, s32 RSSI, bool is_force_update, 247 u8 *ra_tr_state); 248 249 void odm_refresh_basic_rate_mask(void *dm_void); 250 void odm_ra_post_action_on_assoc(void *dm); 251 252 u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, bool is_erp_protect); 253 254 void odm_update_noisy_state(void *dm_void, bool is_noisy_state_from_c2h); 255 256 void phydm_update_pwr_track(void *dm_void, u8 rate); 257 258 #endif /*#ifndef __ODMRAINFO_H__*/ 259