1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H
3 #define _ASM_POWERPC_PGTABLE_RADIX_H
4
5 #include <asm/asm-const.h>
6
7 #ifndef __ASSEMBLY__
8 #include <asm/cmpxchg.h>
9 #endif
10
11 #ifdef CONFIG_PPC_64K_PAGES
12 #include <asm/book3s/64/radix-64k.h>
13 #else
14 #include <asm/book3s/64/radix-4k.h>
15 #endif
16
17 #ifndef __ASSEMBLY__
18 #include <asm/book3s/64/tlbflush-radix.h>
19 #include <asm/cpu_has_feature.h>
20 #endif
21
22 /* An empty PTE can still have a R or C writeback */
23 #define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
24
25 /* Bits to set in a RPMD/RPUD/RPGD */
26 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
27 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
28 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
29
30 /* Don't have anything in the reserved bits and leaf bits */
31 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
32 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
33 #define RADIX_PGD_BAD_BITS 0x60000000000000e0UL
34
35 #define RADIX_PMD_SHIFT (PAGE_SHIFT + RADIX_PTE_INDEX_SIZE)
36 #define RADIX_PUD_SHIFT (RADIX_PMD_SHIFT + RADIX_PMD_INDEX_SIZE)
37 #define RADIX_PGD_SHIFT (RADIX_PUD_SHIFT + RADIX_PUD_INDEX_SIZE)
38 /*
39 * Size of EA range mapped by our pagetables.
40 */
41 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
42 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
43 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
44
45 /*
46 * We support 52 bit address space, Use top bit for kernel
47 * virtual mapping. Also make sure kernel fit in the top
48 * quadrant.
49 *
50 * +------------------+
51 * +------------------+ Kernel virtual map (0xc008000000000000)
52 * | |
53 * | |
54 * | |
55 * 0b11......+------------------+ Kernel linear map (0xc....)
56 * | |
57 * | 2 quadrant |
58 * | |
59 * 0b10......+------------------+
60 * | |
61 * | 1 quadrant |
62 * | |
63 * 0b01......+------------------+
64 * | |
65 * | 0 quadrant |
66 * | |
67 * 0b00......+------------------+
68 *
69 *
70 * 3rd quadrant expanded:
71 * +------------------------------+
72 * | |
73 * | |
74 * | |
75 * +------------------------------+ Kernel IO map end (0xc010000000000000)
76 * | |
77 * | |
78 * | 1/2 of virtual map |
79 * | |
80 * | |
81 * +------------------------------+ Kernel IO map start
82 * | |
83 * | 1/4 of virtual map |
84 * | |
85 * +------------------------------+ Kernel vmemap start
86 * | |
87 * | 1/4 of virtual map |
88 * | |
89 * +------------------------------+ Kernel virt start (0xc008000000000000)
90 * | |
91 * | |
92 * | |
93 * +------------------------------+ Kernel linear (0xc.....)
94 */
95
96 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
97 #define RADIX_KERN_VIRT_SIZE ASM_CONST(0x0008000000000000)
98
99 /*
100 * The vmalloc space starts at the beginning of that region, and
101 * occupies a quarter of it on radix config.
102 * (we keep a quarter for the virtual memmap)
103 */
104 #define RADIX_VMALLOC_START RADIX_KERN_VIRT_START
105 #define RADIX_VMALLOC_SIZE (RADIX_KERN_VIRT_SIZE >> 2)
106 #define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
107 /*
108 * Defines the address of the vmemap area, in its own region on
109 * hash table CPUs.
110 */
111 #define RADIX_VMEMMAP_BASE (RADIX_VMALLOC_END)
112
113 #define RADIX_KERN_IO_START (RADIX_KERN_VIRT_START + (RADIX_KERN_VIRT_SIZE >> 1))
114
115 #ifndef __ASSEMBLY__
116 #define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
117 #define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
118 #define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
119 #define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
120
121 #ifdef CONFIG_STRICT_KERNEL_RWX
122 extern void radix__mark_rodata_ro(void);
123 extern void radix__mark_initmem_nx(void);
124 #endif
125
126 extern void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
127 pte_t entry, unsigned long address,
128 int psize);
129
__radix_pte_update(pte_t * ptep,unsigned long clr,unsigned long set)130 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
131 unsigned long set)
132 {
133 __be64 old_be, tmp_be;
134
135 __asm__ __volatile__(
136 "1: ldarx %0,0,%3 # pte_update\n"
137 " andc %1,%0,%5 \n"
138 " or %1,%1,%4 \n"
139 " stdcx. %1,0,%3 \n"
140 " bne- 1b"
141 : "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
142 : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr))
143 : "cc" );
144
145 return be64_to_cpu(old_be);
146 }
147
radix__pte_update(struct mm_struct * mm,unsigned long addr,pte_t * ptep,unsigned long clr,unsigned long set,int huge)148 static inline unsigned long radix__pte_update(struct mm_struct *mm,
149 unsigned long addr,
150 pte_t *ptep, unsigned long clr,
151 unsigned long set,
152 int huge)
153 {
154 unsigned long old_pte;
155
156 old_pte = __radix_pte_update(ptep, clr, set);
157 if (!huge)
158 assert_pte_locked(mm, addr);
159
160 return old_pte;
161 }
162
radix__ptep_get_and_clear_full(struct mm_struct * mm,unsigned long addr,pte_t * ptep,int full)163 static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
164 unsigned long addr,
165 pte_t *ptep, int full)
166 {
167 unsigned long old_pte;
168
169 if (full) {
170 old_pte = pte_val(*ptep);
171 *ptep = __pte(0);
172 } else
173 old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
174
175 return __pte(old_pte);
176 }
177
radix__pte_same(pte_t pte_a,pte_t pte_b)178 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
179 {
180 return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
181 }
182
radix__pte_none(pte_t pte)183 static inline int radix__pte_none(pte_t pte)
184 {
185 return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
186 }
187
radix__set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte,int percpu)188 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
189 pte_t *ptep, pte_t pte, int percpu)
190 {
191 *ptep = pte;
192
193 /*
194 * The architecture suggests a ptesync after setting the pte, which
195 * orders the store that updates the pte with subsequent page table
196 * walk accesses which may load the pte. Without this it may be
197 * possible for a subsequent access to result in spurious fault.
198 *
199 * This is not necessary for correctness, because a spurious fault
200 * is tolerated by the page fault handler, and this store will
201 * eventually be seen. In testing, there was no noticable increase
202 * in user faults on POWER9. Avoiding ptesync here is a significant
203 * win for things like fork. If a future microarchitecture benefits
204 * from ptesync, it should probably go into update_mmu_cache, rather
205 * than set_pte_at (which is used to set ptes unrelated to faults).
206 *
207 * Spurious faults to vmalloc region are not tolerated, so there is
208 * a ptesync in flush_cache_vmap.
209 */
210 }
211
radix__pmd_bad(pmd_t pmd)212 static inline int radix__pmd_bad(pmd_t pmd)
213 {
214 return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
215 }
216
radix__pmd_same(pmd_t pmd_a,pmd_t pmd_b)217 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
218 {
219 return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
220 }
221
radix__pud_bad(pud_t pud)222 static inline int radix__pud_bad(pud_t pud)
223 {
224 return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
225 }
226
227
radix__pgd_bad(pgd_t pgd)228 static inline int radix__pgd_bad(pgd_t pgd)
229 {
230 return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
231 }
232
233 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
234
radix__pmd_trans_huge(pmd_t pmd)235 static inline int radix__pmd_trans_huge(pmd_t pmd)
236 {
237 return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE;
238 }
239
radix__pmd_mkhuge(pmd_t pmd)240 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
241 {
242 return __pmd(pmd_val(pmd) | _PAGE_PTE);
243 }
244
245 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
246 pmd_t *pmdp, unsigned long clr,
247 unsigned long set);
248 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
249 unsigned long address, pmd_t *pmdp);
250 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
251 pgtable_t pgtable);
252 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
253 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
254 unsigned long addr, pmd_t *pmdp);
255 extern int radix__has_transparent_hugepage(void);
256 #endif
257
258 extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
259 unsigned long page_size,
260 unsigned long phys);
261 extern void radix__vmemmap_remove_mapping(unsigned long start,
262 unsigned long page_size);
263
264 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
265 pgprot_t flags, unsigned int psz);
266
radix__get_tree_size(void)267 static inline unsigned long radix__get_tree_size(void)
268 {
269 unsigned long rts_field;
270 /*
271 * We support 52 bits, hence:
272 * bits 52 - 31 = 21, 0b10101
273 * RTS encoding details
274 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
275 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
276 */
277 rts_field = (0x5UL << 5); /* 6 - 8 bits */
278 rts_field |= (0x2UL << 61);
279
280 return rts_field;
281 }
282
283 #ifdef CONFIG_MEMORY_HOTPLUG
284 int radix__create_section_mapping(unsigned long start, unsigned long end, int nid);
285 int radix__remove_section_mapping(unsigned long start, unsigned long end);
286 #endif /* CONFIG_MEMORY_HOTPLUG */
287 #endif /* __ASSEMBLY__ */
288 #endif
289
