1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2021, Intel Corporation. */
3
4 #ifndef _ICE_PTP_HW_H_
5 #define _ICE_PTP_HW_H_
6
7 enum ice_ptp_tmr_cmd {
8 INIT_TIME,
9 INIT_INCVAL,
10 ADJ_TIME,
11 ADJ_TIME_AT_TIME,
12 READ_TIME
13 };
14
15 enum ice_ptp_serdes {
16 ICE_PTP_SERDES_1G,
17 ICE_PTP_SERDES_10G,
18 ICE_PTP_SERDES_25G,
19 ICE_PTP_SERDES_40G,
20 ICE_PTP_SERDES_50G,
21 ICE_PTP_SERDES_100G
22 };
23
24 enum ice_ptp_link_spd {
25 ICE_PTP_LNK_SPD_1G,
26 ICE_PTP_LNK_SPD_10G,
27 ICE_PTP_LNK_SPD_25G,
28 ICE_PTP_LNK_SPD_25G_RS,
29 ICE_PTP_LNK_SPD_40G,
30 ICE_PTP_LNK_SPD_50G,
31 ICE_PTP_LNK_SPD_50G_RS,
32 ICE_PTP_LNK_SPD_100G_RS,
33 NUM_ICE_PTP_LNK_SPD /* Must be last */
34 };
35
36 enum ice_ptp_fec_mode {
37 ICE_PTP_FEC_MODE_NONE,
38 ICE_PTP_FEC_MODE_CLAUSE74,
39 ICE_PTP_FEC_MODE_RS_FEC
40 };
41
42 /**
43 * struct ice_time_ref_info_e822
44 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
45 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
46 * @pps_delay: propagation delay of the PPS output signal
47 *
48 * Characteristic information for the various TIME_REF sources possible in the
49 * E822 devices
50 */
51 struct ice_time_ref_info_e822 {
52 u64 pll_freq;
53 u64 nominal_incval;
54 u8 pps_delay;
55 };
56
57 /**
58 * struct ice_vernier_info_e822
59 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
60 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
61 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
62 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
63 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
64 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
65 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
66 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
67 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
68 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
69 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
70 *
71 * Table of constants used during as part of the Vernier calibration of the Tx
72 * and Rx timestamps. This includes frequency values used to compute TUs per
73 * PAR/PCS clock cycle, and static delay values measured during hardware
74 * design.
75 *
76 * Note that some values are not used for all link speeds, and the
77 * P_REG_DESK_PAR* registers may represent different clock markers at
78 * different link speeds, either the deskew marker for multi-lane link speeds
79 * or the Reed Solomon gearbox marker for RS-FEC.
80 */
81 struct ice_vernier_info_e822 {
82 u32 tx_par_clk;
83 u32 rx_par_clk;
84 u32 tx_pcs_clk;
85 u32 rx_pcs_clk;
86 u32 tx_desk_rsgb_par;
87 u32 rx_desk_rsgb_par;
88 u32 tx_desk_rsgb_pcs;
89 u32 rx_desk_rsgb_pcs;
90 u32 tx_fixed_delay;
91 u32 pmd_adj_divisor;
92 u32 rx_fixed_delay;
93 };
94
95 /**
96 * struct ice_cgu_pll_params_e822
97 * @refclk_pre_div: Reference clock pre-divisor
98 * @feedback_div: Feedback divisor
99 * @frac_n_div: Fractional divisor
100 * @post_pll_div: Post PLL divisor
101 *
102 * Clock Generation Unit parameters used to program the PLL based on the
103 * selected TIME_REF frequency.
104 */
105 struct ice_cgu_pll_params_e822 {
106 u32 refclk_pre_div;
107 u32 feedback_div;
108 u32 frac_n_div;
109 u32 post_pll_div;
110 };
111
112 extern const struct
113 ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
114
115 /* Table of constants related to possible TIME_REF sources */
116 extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
117
118 /* Table of constants for Vernier calibration on E822 */
119 extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
120
121 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
122 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
123 */
124 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
125
126 /* Device agnostic functions */
127 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
128 bool ice_ptp_lock(struct ice_hw *hw);
129 void ice_ptp_unlock(struct ice_hw *hw);
130 int ice_ptp_init_time(struct ice_hw *hw, u64 time);
131 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
132 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
133 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
134 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
135 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
136 int ice_ptp_init_phc(struct ice_hw *hw);
137
138 /* E822 family functions */
139 int ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
140 int ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val);
141 int ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
142 int ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
143 int ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time);
144
145 /**
146 * ice_e822_time_ref - Get the current TIME_REF from capabilities
147 * @hw: pointer to the HW structure
148 *
149 * Returns the current TIME_REF from the capabilities structure.
150 */
ice_e822_time_ref(struct ice_hw * hw)151 static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)
152 {
153 return hw->func_caps.ts_func_info.time_ref;
154 }
155
156 /**
157 * ice_set_e822_time_ref - Set new TIME_REF
158 * @hw: pointer to the HW structure
159 * @time_ref: new TIME_REF to set
160 *
161 * Update the TIME_REF in the capabilities structure in response to some
162 * change, such as an update to the CGU registers.
163 */
164 static inline void
ice_set_e822_time_ref(struct ice_hw * hw,enum ice_time_ref_freq time_ref)165 ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
166 {
167 hw->func_caps.ts_func_info.time_ref = time_ref;
168 }
169
ice_e822_pll_freq(enum ice_time_ref_freq time_ref)170 static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
171 {
172 return e822_time_ref[time_ref].pll_freq;
173 }
174
ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)175 static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)
176 {
177 return e822_time_ref[time_ref].nominal_incval;
178 }
179
ice_e822_pps_delay(enum ice_time_ref_freq time_ref)180 static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)
181 {
182 return e822_time_ref[time_ref].pps_delay;
183 }
184
185 /* E822 Vernier calibration functions */
186 int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
187 int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
188 int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);
189
190 /* E810 family functions */
191 int ice_ptp_init_phy_e810(struct ice_hw *hw);
192 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
193 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
194 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
195 bool ice_is_pca9575_present(struct ice_hw *hw);
196
197 #define PFTSYN_SEM_BYTES 4
198
199 #define ICE_PTP_CLOCK_INDEX_0 0x00
200 #define ICE_PTP_CLOCK_INDEX_1 0x01
201
202 /* PHY timer commands */
203 #define SEL_CPK_SRC 8
204 #define SEL_PHY_SRC 3
205
206 /* Time Sync command Definitions */
207 #define GLTSYN_CMD_INIT_TIME BIT(0)
208 #define GLTSYN_CMD_INIT_INCVAL BIT(1)
209 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
210 #define GLTSYN_CMD_ADJ_TIME BIT(2)
211 #define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
212 #define GLTSYN_CMD_READ_TIME BIT(7)
213
214 /* PHY port Time Sync command definitions */
215 #define PHY_CMD_INIT_TIME BIT(0)
216 #define PHY_CMD_INIT_INCVAL BIT(1)
217 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
218 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
219 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
220
221 #define TS_CMD_MASK_E810 0xFF
222 #define TS_CMD_MASK 0xF
223 #define SYNC_EXEC_CMD 0x3
224
225 /* Macros to derive port low and high addresses on both quads */
226 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
227 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
228 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
229 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
230
231 /* PHY QUAD register base addresses */
232 #define Q_0_BASE 0x94000
233 #define Q_1_BASE 0x114000
234
235 /* Timestamp memory reset registers */
236 #define Q_REG_TS_CTRL 0x618
237 #define Q_REG_TS_CTRL_S 0
238 #define Q_REG_TS_CTRL_M BIT(0)
239
240 /* Timestamp availability status registers */
241 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
242 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
243
244 /* Tx FIFO status registers */
245 #define Q_REG_FIFO23_STATUS 0xCF8
246 #define Q_REG_FIFO01_STATUS 0xCFC
247 #define Q_REG_FIFO02_S 0
248 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
249 #define Q_REG_FIFO13_S 10
250 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
251
252 /* Interrupt control Config registers */
253 #define Q_REG_TX_MEM_GBL_CFG 0xC08
254 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
255 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
256 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
257 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
258 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
259 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
260 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
261 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
262
263 /* Tx Timestamp data registers */
264 #define Q_REG_TX_MEMORY_BANK_START 0xA00
265
266 /* PHY port register base addresses */
267 #define P_0_BASE 0x80000
268 #define P_4_BASE 0x106000
269
270 /* Timestamp init registers */
271 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
272 #define P_REG_RX_TIMER_INC_PRE_U 0x470
273 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
274 #define P_REG_TX_TIMER_INC_PRE_U 0x450
275
276 /* Timestamp match and adjust target registers */
277 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
278 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
279 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
280 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
281
282 /* Timestamp capture registers */
283 #define P_REG_RX_CAPTURE_L 0x4D8
284 #define P_REG_RX_CAPTURE_U 0x4DC
285 #define P_REG_TX_CAPTURE_L 0x4B4
286 #define P_REG_TX_CAPTURE_U 0x4B8
287
288 /* Timestamp PHY incval registers */
289 #define P_REG_TIMETUS_L 0x410
290 #define P_REG_TIMETUS_U 0x414
291
292 #define P_REG_40B_LOW_M 0xFF
293 #define P_REG_40B_HIGH_S 8
294
295 /* PHY window length registers */
296 #define P_REG_WL 0x40C
297
298 #define PTP_VERNIER_WL 0x111ed
299
300 /* PHY start registers */
301 #define P_REG_PS 0x408
302 #define P_REG_PS_START_S 0
303 #define P_REG_PS_START_M BIT(0)
304 #define P_REG_PS_BYPASS_MODE_S 1
305 #define P_REG_PS_BYPASS_MODE_M BIT(1)
306 #define P_REG_PS_ENA_CLK_S 2
307 #define P_REG_PS_ENA_CLK_M BIT(2)
308 #define P_REG_PS_LOAD_OFFSET_S 3
309 #define P_REG_PS_LOAD_OFFSET_M BIT(3)
310 #define P_REG_PS_SFT_RESET_S 11
311 #define P_REG_PS_SFT_RESET_M BIT(11)
312
313 /* PHY offset valid registers */
314 #define P_REG_TX_OV_STATUS 0x4D4
315 #define P_REG_TX_OV_STATUS_OV_S 0
316 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
317 #define P_REG_RX_OV_STATUS 0x4F8
318 #define P_REG_RX_OV_STATUS_OV_S 0
319 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
320
321 /* PHY offset ready registers */
322 #define P_REG_TX_OR 0x45C
323 #define P_REG_RX_OR 0x47C
324
325 /* PHY total offset registers */
326 #define P_REG_TOTAL_RX_OFFSET_L 0x460
327 #define P_REG_TOTAL_RX_OFFSET_U 0x464
328 #define P_REG_TOTAL_TX_OFFSET_L 0x440
329 #define P_REG_TOTAL_TX_OFFSET_U 0x444
330
331 /* Timestamp PAR/PCS registers */
332 #define P_REG_UIX66_10G_40G_L 0x480
333 #define P_REG_UIX66_10G_40G_U 0x484
334 #define P_REG_UIX66_25G_100G_L 0x488
335 #define P_REG_UIX66_25G_100G_U 0x48C
336 #define P_REG_DESK_PAR_RX_TUS_L 0x490
337 #define P_REG_DESK_PAR_RX_TUS_U 0x494
338 #define P_REG_DESK_PAR_TX_TUS_L 0x498
339 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
340 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
341 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
342 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
343 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
344 #define P_REG_PAR_RX_TUS_L 0x420
345 #define P_REG_PAR_RX_TUS_U 0x424
346 #define P_REG_PAR_TX_TUS_L 0x428
347 #define P_REG_PAR_TX_TUS_U 0x42C
348 #define P_REG_PCS_RX_TUS_L 0x430
349 #define P_REG_PCS_RX_TUS_U 0x434
350 #define P_REG_PCS_TX_TUS_L 0x438
351 #define P_REG_PCS_TX_TUS_U 0x43C
352 #define P_REG_PAR_RX_TIME_L 0x4F0
353 #define P_REG_PAR_RX_TIME_U 0x4F4
354 #define P_REG_PAR_TX_TIME_L 0x4CC
355 #define P_REG_PAR_TX_TIME_U 0x4D0
356 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
357 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
358 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
359 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
360 #define P_REG_LINK_SPEED 0x4FC
361 #define P_REG_LINK_SPEED_SERDES_S 0
362 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
363 #define P_REG_LINK_SPEED_FEC_MODE_S 3
364 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
365 #define P_REG_LINK_SPEED_FEC_MODE(reg) \
366 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
367 P_REG_LINK_SPEED_FEC_MODE_S)
368
369 /* PHY timestamp related registers */
370 #define P_REG_PMD_ALIGNMENT 0x0FC
371 #define P_REG_RX_80_TO_160_CNT 0x6FC
372 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
373 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
374 #define P_REG_RX_40_TO_160_CNT 0x8FC
375 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
376 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
377
378 /* Rx FIFO status registers */
379 #define P_REG_RX_OV_FS 0x4F8
380 #define P_REG_RX_OV_FS_FIFO_STATUS_S 2
381 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
382
383 /* Timestamp command registers */
384 #define P_REG_TX_TMR_CMD 0x448
385 #define P_REG_RX_TMR_CMD 0x468
386
387 /* E810 timesync enable register */
388 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
389
390 /* E810 shadow init time registers */
391 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
392 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
393
394 /* E810 shadow time adjust registers */
395 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
396 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
397
398 /* E810 timer command register */
399 #define ETH_GLTSYN_CMD 0x03000344
400
401 /* Source timer incval macros */
402 #define INCVAL_HIGH_M 0xFF
403
404 /* Timestamp block macros */
405 #define TS_VALID BIT(0)
406 #define TS_LOW_M 0xFFFFFFFF
407 #define TS_HIGH_M 0xFF
408 #define TS_HIGH_S 32
409
410 #define TS_PHY_LOW_M 0xFF
411 #define TS_PHY_HIGH_M 0xFFFFFFFF
412 #define TS_PHY_HIGH_S 8
413
414 #define BYTES_PER_IDX_ADDR_L_U 8
415 #define BYTES_PER_IDX_ADDR_L 4
416
417 /* Tx timestamp low latency read definitions */
418 #define TS_LL_READ_RETRIES 200
419 #define TS_LL_READ_TS_HIGH GENMASK(23, 16)
420 #define TS_LL_READ_TS_IDX GENMASK(29, 24)
421 #define TS_LL_READ_TS BIT(31)
422
423 /* Internal PHY timestamp address */
424 #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
425 #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
426 BYTES_PER_IDX_ADDR_L))
427
428 /* External PHY timestamp address */
429 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
430 ((idx) * BYTES_PER_IDX_ADDR_L_U))
431
432 #define LOW_TX_MEMORY_BANK_START 0x03090000
433 #define HIGH_TX_MEMORY_BANK_START 0x03090004
434
435 /* E810T SMA controller pin control */
436 #define ICE_SMA1_DIR_EN_E810T BIT(4)
437 #define ICE_SMA1_TX_EN_E810T BIT(5)
438 #define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
439 #define ICE_SMA2_DIR_EN_E810T BIT(6)
440 #define ICE_SMA2_TX_EN_E810T BIT(7)
441
442 #define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
443 ICE_SMA1_TX_EN_E810T)
444 #define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
445 ICE_SMA2_DIR_EN_E810T | \
446 ICE_SMA2_TX_EN_E810T)
447 #define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
448 ICE_SMA2_MASK_E810T)
449
450 #define ICE_SMA_MIN_BIT_E810T 3
451 #define ICE_SMA_MAX_BIT_E810T 7
452 #define ICE_PCA9575_P1_OFFSET 8
453
454 /* E810T PCA9575 IO controller registers */
455 #define ICE_PCA9575_P0_IN 0x0
456
457 /* E810T PCA9575 IO controller pin control */
458 #define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
459
460 #endif /* _ICE_PTP_HW_H_ */
461
