1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright © 2006-2015, Intel Corporation.
4 *
5 * Authors: Ashok Raj <ashok.raj@intel.com>
6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
7 * David Woodhouse <David.Woodhouse@intel.com>
8 */
9
10 #ifndef _INTEL_IOMMU_H_
11 #define _INTEL_IOMMU_H_
12
13 #include <linux/types.h>
14 #include <linux/iova.h>
15 #include <linux/io.h>
16 #include <linux/idr.h>
17 #include <linux/mmu_notifier.h>
18 #include <linux/list.h>
19 #include <linux/iommu.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
21 #include <linux/dmar.h>
22 #include <linux/ioasid.h>
23
24 #include <asm/cacheflush.h>
25 #include <asm/iommu.h>
26
27 /*
28 * VT-d hardware uses 4KiB page size regardless of host page size.
29 */
30 #define VTD_PAGE_SHIFT (12)
31 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
32 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
33 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
34
35 #define VTD_STRIDE_SHIFT (9)
36 #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
37
38 #define DMA_PTE_READ BIT_ULL(0)
39 #define DMA_PTE_WRITE BIT_ULL(1)
40 #define DMA_PTE_LARGE_PAGE BIT_ULL(7)
41 #define DMA_PTE_SNP BIT_ULL(11)
42
43 #define DMA_FL_PTE_PRESENT BIT_ULL(0)
44 #define DMA_FL_PTE_US BIT_ULL(2)
45 #define DMA_FL_PTE_XD BIT_ULL(63)
46
47 #define ADDR_WIDTH_5LEVEL (57)
48 #define ADDR_WIDTH_4LEVEL (48)
49
50 #define CONTEXT_TT_MULTI_LEVEL 0
51 #define CONTEXT_TT_DEV_IOTLB 1
52 #define CONTEXT_TT_PASS_THROUGH 2
53 #define CONTEXT_PASIDE BIT_ULL(3)
54
55 /*
56 * Intel IOMMU register specification per version 1.0 public spec.
57 */
58 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
59 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
60 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
61 #define DMAR_GCMD_REG 0x18 /* Global command register */
62 #define DMAR_GSTS_REG 0x1c /* Global status register */
63 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
64 #define DMAR_CCMD_REG 0x28 /* Context command reg */
65 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
66 #define DMAR_FECTL_REG 0x38 /* Fault control register */
67 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
68 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
69 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
70 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
71 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
72 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
73 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
74 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
75 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
76 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
77 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
78 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
79 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
80 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
81 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
82 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */
83 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
84 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */
85 #define DMAR_PRS_REG 0xdc /* Page request status register */
86 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */
87 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
88 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
89 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
90 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */
91 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */
92 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
93 #define DMAR_MTRR_FIX16K_80000_REG 0x128
94 #define DMAR_MTRR_FIX16K_A0000_REG 0x130
95 #define DMAR_MTRR_FIX4K_C0000_REG 0x138
96 #define DMAR_MTRR_FIX4K_C8000_REG 0x140
97 #define DMAR_MTRR_FIX4K_D0000_REG 0x148
98 #define DMAR_MTRR_FIX4K_D8000_REG 0x150
99 #define DMAR_MTRR_FIX4K_E0000_REG 0x158
100 #define DMAR_MTRR_FIX4K_E8000_REG 0x160
101 #define DMAR_MTRR_FIX4K_F0000_REG 0x168
102 #define DMAR_MTRR_FIX4K_F8000_REG 0x170
103 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
104 #define DMAR_MTRR_PHYSMASK0_REG 0x188
105 #define DMAR_MTRR_PHYSBASE1_REG 0x190
106 #define DMAR_MTRR_PHYSMASK1_REG 0x198
107 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0
108 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8
109 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0
110 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8
111 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0
112 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8
113 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0
114 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8
115 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0
116 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8
117 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0
118 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8
119 #define DMAR_MTRR_PHYSBASE8_REG 0x200
120 #define DMAR_MTRR_PHYSMASK8_REG 0x208
121 #define DMAR_MTRR_PHYSBASE9_REG 0x210
122 #define DMAR_MTRR_PHYSMASK9_REG 0x218
123 #define DMAR_VCCAP_REG 0xe00 /* Virtual command capability register */
124 #define DMAR_VCMD_REG 0xe10 /* Virtual command register */
125 #define DMAR_VCRSP_REG 0xe20 /* Virtual command response register */
126
127 #define OFFSET_STRIDE (9)
128
129 #define dmar_readq(a) readq(a)
130 #define dmar_writeq(a,v) writeq(v,a)
131 #define dmar_readl(a) readl(a)
132 #define dmar_writel(a, v) writel(v, a)
133
134 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
135 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
136
137 /*
138 * Decoding Capability Register
139 */
140 #define cap_5lp_support(c) (((c) >> 60) & 1)
141 #define cap_pi_support(c) (((c) >> 59) & 1)
142 #define cap_fl1gp_support(c) (((c) >> 56) & 1)
143 #define cap_read_drain(c) (((c) >> 55) & 1)
144 #define cap_write_drain(c) (((c) >> 54) & 1)
145 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
146 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
147 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
148
149 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
150 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
151 * OFFSET_STRIDE) + 21)
152
153 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
154 #define cap_max_fault_reg_offset(c) \
155 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
156
157 #define cap_zlr(c) (((c) >> 22) & 1)
158 #define cap_isoch(c) (((c) >> 23) & 1)
159 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
160 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
161 #define cap_caching_mode(c) (((c) >> 7) & 1)
162 #define cap_phmr(c) (((c) >> 6) & 1)
163 #define cap_plmr(c) (((c) >> 5) & 1)
164 #define cap_rwbf(c) (((c) >> 4) & 1)
165 #define cap_afl(c) (((c) >> 3) & 1)
166 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
167 /*
168 * Extended Capability Register
169 */
170
171 #define ecap_smpwc(e) (((e) >> 48) & 0x1)
172 #define ecap_flts(e) (((e) >> 47) & 0x1)
173 #define ecap_slts(e) (((e) >> 46) & 0x1)
174 #define ecap_vcs(e) (((e) >> 44) & 0x1)
175 #define ecap_smts(e) (((e) >> 43) & 0x1)
176 #define ecap_dit(e) ((e >> 41) & 0x1)
177 #define ecap_pasid(e) ((e >> 40) & 0x1)
178 #define ecap_pss(e) ((e >> 35) & 0x1f)
179 #define ecap_eafs(e) ((e >> 34) & 0x1)
180 #define ecap_nwfs(e) ((e >> 33) & 0x1)
181 #define ecap_srs(e) ((e >> 31) & 0x1)
182 #define ecap_ers(e) ((e >> 30) & 0x1)
183 #define ecap_prs(e) ((e >> 29) & 0x1)
184 #define ecap_broken_pasid(e) ((e >> 28) & 0x1)
185 #define ecap_dis(e) ((e >> 27) & 0x1)
186 #define ecap_nest(e) ((e >> 26) & 0x1)
187 #define ecap_mts(e) ((e >> 25) & 0x1)
188 #define ecap_ecs(e) ((e >> 24) & 0x1)
189 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
190 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
191 #define ecap_coherent(e) ((e) & 0x1)
192 #define ecap_qis(e) ((e) & 0x2)
193 #define ecap_pass_through(e) ((e >> 6) & 0x1)
194 #define ecap_eim_support(e) ((e >> 4) & 0x1)
195 #define ecap_ir_support(e) ((e >> 3) & 0x1)
196 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
197 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
198 #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
199
200 /* Virtual command interface capability */
201 #define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */
202
203 /* IOTLB_REG */
204 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
205 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
206 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
207 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
208 #define DMA_TLB_IIRG(type) ((type >> 60) & 3)
209 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
210 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
211 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
212 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
213 #define DMA_TLB_IVT (((u64)1) << 63)
214 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
215 #define DMA_TLB_MAX_SIZE (0x3f)
216
217 /* INVALID_DESC */
218 #define DMA_CCMD_INVL_GRANU_OFFSET 61
219 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
220 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
221 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
222 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
223 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
224 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
225 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
226 #define DMA_ID_TLB_ADDR(addr) (addr)
227 #define DMA_ID_TLB_ADDR_MASK(mask) (mask)
228
229 /* PMEN_REG */
230 #define DMA_PMEN_EPM (((u32)1)<<31)
231 #define DMA_PMEN_PRS (((u32)1)<<0)
232
233 /* GCMD_REG */
234 #define DMA_GCMD_TE (((u32)1) << 31)
235 #define DMA_GCMD_SRTP (((u32)1) << 30)
236 #define DMA_GCMD_SFL (((u32)1) << 29)
237 #define DMA_GCMD_EAFL (((u32)1) << 28)
238 #define DMA_GCMD_WBF (((u32)1) << 27)
239 #define DMA_GCMD_QIE (((u32)1) << 26)
240 #define DMA_GCMD_SIRTP (((u32)1) << 24)
241 #define DMA_GCMD_IRE (((u32) 1) << 25)
242 #define DMA_GCMD_CFI (((u32) 1) << 23)
243
244 /* GSTS_REG */
245 #define DMA_GSTS_TES (((u32)1) << 31)
246 #define DMA_GSTS_RTPS (((u32)1) << 30)
247 #define DMA_GSTS_FLS (((u32)1) << 29)
248 #define DMA_GSTS_AFLS (((u32)1) << 28)
249 #define DMA_GSTS_WBFS (((u32)1) << 27)
250 #define DMA_GSTS_QIES (((u32)1) << 26)
251 #define DMA_GSTS_IRTPS (((u32)1) << 24)
252 #define DMA_GSTS_IRES (((u32)1) << 25)
253 #define DMA_GSTS_CFIS (((u32)1) << 23)
254
255 /* DMA_RTADDR_REG */
256 #define DMA_RTADDR_RTT (((u64)1) << 11)
257 #define DMA_RTADDR_SMT (((u64)1) << 10)
258
259 /* CCMD_REG */
260 #define DMA_CCMD_ICC (((u64)1) << 63)
261 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
262 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
263 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
264 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
265 #define DMA_CCMD_MASK_NOBIT 0
266 #define DMA_CCMD_MASK_1BIT 1
267 #define DMA_CCMD_MASK_2BIT 2
268 #define DMA_CCMD_MASK_3BIT 3
269 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
270 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
271
272 /* FECTL_REG */
273 #define DMA_FECTL_IM (((u32)1) << 31)
274
275 /* FSTS_REG */
276 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
277 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
278 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
279 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
280 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
281 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
282 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
283
284 /* FRCD_REG, 32 bits access */
285 #define DMA_FRCD_F (((u32)1) << 31)
286 #define dma_frcd_type(d) ((d >> 30) & 1)
287 #define dma_frcd_fault_reason(c) (c & 0xff)
288 #define dma_frcd_source_id(c) (c & 0xffff)
289 #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff)
290 #define dma_frcd_pasid_present(c) (((c) >> 31) & 1)
291 /* low 64 bit */
292 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
293
294 /* PRS_REG */
295 #define DMA_PRS_PPR ((u32)1)
296 #define DMA_PRS_PRO ((u32)2)
297
298 #define DMA_VCS_PAS ((u64)1)
299
300 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
301 do { \
302 cycles_t start_time = get_cycles(); \
303 while (1) { \
304 sts = op(iommu->reg + offset); \
305 if (cond) \
306 break; \
307 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
308 panic("DMAR hardware is malfunctioning\n"); \
309 cpu_relax(); \
310 } \
311 } while (0)
312
313 #define QI_LENGTH 256 /* queue length */
314
315 enum {
316 QI_FREE,
317 QI_IN_USE,
318 QI_DONE,
319 QI_ABORT
320 };
321
322 #define QI_CC_TYPE 0x1
323 #define QI_IOTLB_TYPE 0x2
324 #define QI_DIOTLB_TYPE 0x3
325 #define QI_IEC_TYPE 0x4
326 #define QI_IWD_TYPE 0x5
327 #define QI_EIOTLB_TYPE 0x6
328 #define QI_PC_TYPE 0x7
329 #define QI_DEIOTLB_TYPE 0x8
330 #define QI_PGRP_RESP_TYPE 0x9
331 #define QI_PSTRM_RESP_TYPE 0xa
332
333 #define QI_IEC_SELECTIVE (((u64)1) << 4)
334 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
335 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
336
337 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
338 #define QI_IWD_STATUS_WRITE (((u64)1) << 5)
339 #define QI_IWD_FENCE (((u64)1) << 6)
340 #define QI_IWD_PRQ_DRAIN (((u64)1) << 7)
341
342 #define QI_IOTLB_DID(did) (((u64)did) << 16)
343 #define QI_IOTLB_DR(dr) (((u64)dr) << 7)
344 #define QI_IOTLB_DW(dw) (((u64)dw) << 6)
345 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
346 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
347 #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
348 #define QI_IOTLB_AM(am) (((u8)am) & 0x3f)
349
350 #define QI_CC_FM(fm) (((u64)fm) << 48)
351 #define QI_CC_SID(sid) (((u64)sid) << 32)
352 #define QI_CC_DID(did) (((u64)did) << 16)
353 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
354
355 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
356 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
357 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
358 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
359 ((u64)((pfsid >> 4) & 0xfff) << 52))
360 #define QI_DEV_IOTLB_SIZE 1
361 #define QI_DEV_IOTLB_MAX_INVS 32
362
363 #define QI_PC_PASID(pasid) (((u64)pasid) << 32)
364 #define QI_PC_DID(did) (((u64)did) << 16)
365 #define QI_PC_GRAN(gran) (((u64)gran) << 4)
366
367 /* PASID cache invalidation granu */
368 #define QI_PC_ALL_PASIDS 0
369 #define QI_PC_PASID_SEL 1
370
371 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
372 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
373 #define QI_EIOTLB_AM(am) (((u64)am) & 0x3f)
374 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
375 #define QI_EIOTLB_DID(did) (((u64)did) << 16)
376 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
377
378 /* QI Dev-IOTLB inv granu */
379 #define QI_DEV_IOTLB_GRAN_ALL 1
380 #define QI_DEV_IOTLB_GRAN_PASID_SEL 0
381
382 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
383 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
384 #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32)
385 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
386 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
387 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
388 ((u64)((pfsid >> 4) & 0xfff) << 52))
389 #define QI_DEV_EIOTLB_MAX_INVS 32
390
391 /* Page group response descriptor QW0 */
392 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
393 #define QI_PGRP_PDP(p) (((u64)(p)) << 5)
394 #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
395 #define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
396 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
397
398 /* Page group response descriptor QW1 */
399 #define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
400 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
401
402
403 #define QI_RESP_SUCCESS 0x0
404 #define QI_RESP_INVALID 0x1
405 #define QI_RESP_FAILURE 0xf
406
407 #define QI_GRAN_NONG_PASID 2
408 #define QI_GRAN_PSI_PASID 3
409
410 #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
411
412 struct qi_desc {
413 u64 qw0;
414 u64 qw1;
415 u64 qw2;
416 u64 qw3;
417 };
418
419 struct q_inval {
420 raw_spinlock_t q_lock;
421 void *desc; /* invalidation queue */
422 int *desc_status; /* desc status */
423 int free_head; /* first free entry */
424 int free_tail; /* last free entry */
425 int free_cnt;
426 };
427
428 struct dmar_pci_notify_info;
429
430 #ifdef CONFIG_IRQ_REMAP
431 /* 1MB - maximum possible interrupt remapping table size */
432 #define INTR_REMAP_PAGE_ORDER 8
433 #define INTR_REMAP_TABLE_REG_SIZE 0xf
434 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
435
436 #define INTR_REMAP_TABLE_ENTRIES 65536
437
438 struct irq_domain;
439
440 struct ir_table {
441 struct irte *base;
442 unsigned long *bitmap;
443 };
444
445 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info);
446 #else
447 static inline void
intel_irq_remap_add_device(struct dmar_pci_notify_info * info)448 intel_irq_remap_add_device(struct dmar_pci_notify_info *info) { }
449 #endif
450
451 struct iommu_flush {
452 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
453 u8 fm, u64 type);
454 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
455 unsigned int size_order, u64 type);
456 };
457
458 enum {
459 SR_DMAR_FECTL_REG,
460 SR_DMAR_FEDATA_REG,
461 SR_DMAR_FEADDR_REG,
462 SR_DMAR_FEUADDR_REG,
463 MAX_SR_DMAR_REGS
464 };
465
466 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
467 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
468 #define VTD_FLAG_SVM_CAPABLE (1 << 2)
469
470 extern int intel_iommu_sm;
471 extern spinlock_t device_domain_lock;
472
473 #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))
474 #define pasid_supported(iommu) (sm_supported(iommu) && \
475 ecap_pasid((iommu)->ecap))
476
477 struct pasid_entry;
478 struct pasid_state_entry;
479 struct page_req_dsc;
480
481 /*
482 * 0: Present
483 * 1-11: Reserved
484 * 12-63: Context Ptr (12 - (haw-1))
485 * 64-127: Reserved
486 */
487 struct root_entry {
488 u64 lo;
489 u64 hi;
490 };
491
492 /*
493 * low 64 bits:
494 * 0: present
495 * 1: fault processing disable
496 * 2-3: translation type
497 * 12-63: address space root
498 * high 64 bits:
499 * 0-2: address width
500 * 3-6: aval
501 * 8-23: domain id
502 */
503 struct context_entry {
504 u64 lo;
505 u64 hi;
506 };
507
508 /* si_domain contains mulitple devices */
509 #define DOMAIN_FLAG_STATIC_IDENTITY BIT(0)
510
511 /*
512 * When VT-d works in the scalable mode, it allows DMA translation to
513 * happen through either first level or second level page table. This
514 * bit marks that the DMA translation for the domain goes through the
515 * first level page table, otherwise, it goes through the second level.
516 */
517 #define DOMAIN_FLAG_USE_FIRST_LEVEL BIT(1)
518
519 /*
520 * Domain represents a virtual machine which demands iommu nested
521 * translation mode support.
522 */
523 #define DOMAIN_FLAG_NESTING_MODE BIT(2)
524
525 struct dmar_domain {
526 int nid; /* node id */
527
528 unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED];
529 /* Refcount of devices per iommu */
530
531
532 u16 iommu_did[DMAR_UNITS_SUPPORTED];
533 /* Domain ids per IOMMU. Use u16 since
534 * domain ids are 16 bit wide according
535 * to VT-d spec, section 9.3 */
536 unsigned int auxd_refcnt; /* Refcount of auxiliary attaching */
537
538 bool has_iotlb_device;
539 struct list_head devices; /* all devices' list */
540 struct list_head auxd; /* link to device's auxiliary list */
541 struct iova_domain iovad; /* iova's that belong to this domain */
542
543 struct dma_pte *pgd; /* virtual address */
544 int gaw; /* max guest address width */
545
546 /* adjusted guest address width, 0 is level 2 30-bit */
547 int agaw;
548
549 int flags; /* flags to find out type of domain */
550
551 int iommu_coherency;/* indicate coherency of iommu access */
552 int iommu_snooping; /* indicate snooping control feature*/
553 int iommu_count; /* reference count of iommu */
554 int iommu_superpage;/* Level of superpages supported:
555 0 == 4KiB (no superpages), 1 == 2MiB,
556 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
557 u64 max_addr; /* maximum mapped address */
558
559 u32 default_pasid; /*
560 * The default pasid used for non-SVM
561 * traffic on mediated devices.
562 */
563
564 struct iommu_domain domain; /* generic domain data structure for
565 iommu core */
566 };
567
568 struct intel_iommu {
569 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
570 u64 reg_phys; /* physical address of hw register set */
571 u64 reg_size; /* size of hw register set */
572 u64 cap;
573 u64 ecap;
574 u64 vccap;
575 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
576 raw_spinlock_t register_lock; /* protect register handling */
577 int seq_id; /* sequence id of the iommu */
578 int agaw; /* agaw of this iommu */
579 int msagaw; /* max sagaw of this iommu */
580 unsigned int irq, pr_irq;
581 u16 segment; /* PCI segment# */
582 unsigned char name[13]; /* Device Name */
583
584 #ifdef CONFIG_INTEL_IOMMU
585 unsigned long *domain_ids; /* bitmap of domains */
586 struct dmar_domain ***domains; /* ptr to domains */
587 spinlock_t lock; /* protect context, domain ids */
588 struct root_entry *root_entry; /* virtual address */
589
590 struct iommu_flush flush;
591 #endif
592 #ifdef CONFIG_INTEL_IOMMU_SVM
593 struct page_req_dsc *prq;
594 unsigned char prq_name[16]; /* Name for PRQ interrupt */
595 struct completion prq_complete;
596 struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASIDs */
597 #endif
598 struct q_inval *qi; /* Queued invalidation info */
599 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
600
601 #ifdef CONFIG_IRQ_REMAP
602 struct ir_table *ir_table; /* Interrupt remapping info */
603 struct irq_domain *ir_domain;
604 struct irq_domain *ir_msi_domain;
605 #endif
606 struct iommu_device iommu; /* IOMMU core code handle */
607 int node;
608 u32 flags; /* Software defined flags */
609
610 struct dmar_drhd_unit *drhd;
611 };
612
613 /* PCI domain-device relationship */
614 struct device_domain_info {
615 struct list_head link; /* link to domain siblings */
616 struct list_head global; /* link to global list */
617 struct list_head table; /* link to pasid table */
618 struct list_head auxiliary_domains; /* auxiliary domains
619 * attached to this device
620 */
621 u32 segment; /* PCI segment number */
622 u8 bus; /* PCI bus number */
623 u8 devfn; /* PCI devfn number */
624 u16 pfsid; /* SRIOV physical function source ID */
625 u8 pasid_supported:3;
626 u8 pasid_enabled:1;
627 u8 pri_supported:1;
628 u8 pri_enabled:1;
629 u8 ats_supported:1;
630 u8 ats_enabled:1;
631 u8 auxd_enabled:1; /* Multiple domains per device */
632 u8 ats_qdep;
633 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
634 struct intel_iommu *iommu; /* IOMMU used by this device */
635 struct dmar_domain *domain; /* pointer to domain */
636 struct pasid_table *pasid_table; /* pasid table */
637 };
638
__iommu_flush_cache(struct intel_iommu * iommu,void * addr,int size)639 static inline void __iommu_flush_cache(
640 struct intel_iommu *iommu, void *addr, int size)
641 {
642 if (!ecap_coherent(iommu->ecap))
643 clflush_cache_range(addr, size);
644 }
645
646 /* Convert generic struct iommu_domain to private struct dmar_domain */
to_dmar_domain(struct iommu_domain * dom)647 static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
648 {
649 return container_of(dom, struct dmar_domain, domain);
650 }
651
652 /*
653 * 0: readable
654 * 1: writable
655 * 2-6: reserved
656 * 7: super page
657 * 8-10: available
658 * 11: snoop behavior
659 * 12-63: Host physcial address
660 */
661 struct dma_pte {
662 u64 val;
663 };
664
dma_clear_pte(struct dma_pte * pte)665 static inline void dma_clear_pte(struct dma_pte *pte)
666 {
667 pte->val = 0;
668 }
669
dma_pte_addr(struct dma_pte * pte)670 static inline u64 dma_pte_addr(struct dma_pte *pte)
671 {
672 #ifdef CONFIG_64BIT
673 return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
674 #else
675 /* Must have a full atomic 64-bit read */
676 return __cmpxchg64(&pte->val, 0ULL, 0ULL) &
677 VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
678 #endif
679 }
680
dma_pte_present(struct dma_pte * pte)681 static inline bool dma_pte_present(struct dma_pte *pte)
682 {
683 return (pte->val & 3) != 0;
684 }
685
dma_pte_superpage(struct dma_pte * pte)686 static inline bool dma_pte_superpage(struct dma_pte *pte)
687 {
688 return (pte->val & DMA_PTE_LARGE_PAGE);
689 }
690
first_pte_in_page(struct dma_pte * pte)691 static inline int first_pte_in_page(struct dma_pte *pte)
692 {
693 return !((unsigned long)pte & ~VTD_PAGE_MASK);
694 }
695
696 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
697 extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
698
699 extern int dmar_enable_qi(struct intel_iommu *iommu);
700 extern void dmar_disable_qi(struct intel_iommu *iommu);
701 extern int dmar_reenable_qi(struct intel_iommu *iommu);
702 extern void qi_global_iec(struct intel_iommu *iommu);
703
704 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
705 u8 fm, u64 type);
706 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
707 unsigned int size_order, u64 type);
708 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
709 u16 qdep, u64 addr, unsigned mask);
710
711 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
712 unsigned long npages, bool ih);
713
714 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
715 u32 pasid, u16 qdep, u64 addr,
716 unsigned int size_order);
717 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,
718 u32 pasid);
719
720 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,
721 unsigned int count, unsigned long options);
722 /*
723 * Options used in qi_submit_sync:
724 * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8.
725 */
726 #define QI_OPT_WAIT_DRAIN BIT(0)
727
728 extern int dmar_ir_support(void);
729
730 void *alloc_pgtable_page(int node);
731 void free_pgtable_page(void *vaddr);
732 struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
733 int for_each_device_domain(int (*fn)(struct device_domain_info *info,
734 void *data), void *data);
735 void iommu_flush_write_buffer(struct intel_iommu *iommu);
736 int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
737 struct dmar_domain *find_domain(struct device *dev);
738 struct device_domain_info *get_domain_info(struct device *dev);
739 struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn);
740
741 #ifdef CONFIG_INTEL_IOMMU_SVM
742 extern void intel_svm_check(struct intel_iommu *iommu);
743 extern int intel_svm_enable_prq(struct intel_iommu *iommu);
744 extern int intel_svm_finish_prq(struct intel_iommu *iommu);
745 int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev,
746 struct iommu_gpasid_bind_data *data);
747 int intel_svm_unbind_gpasid(struct device *dev, u32 pasid);
748 struct iommu_sva *intel_svm_bind(struct device *dev, struct mm_struct *mm,
749 void *drvdata);
750 void intel_svm_unbind(struct iommu_sva *handle);
751 u32 intel_svm_get_pasid(struct iommu_sva *handle);
752 int intel_svm_page_response(struct device *dev, struct iommu_fault_event *evt,
753 struct iommu_page_response *msg);
754
755 struct svm_dev_ops;
756
757 struct intel_svm_dev {
758 struct list_head list;
759 struct rcu_head rcu;
760 struct device *dev;
761 struct svm_dev_ops *ops;
762 struct iommu_sva sva;
763 u32 pasid;
764 int users;
765 u16 did;
766 u16 dev_iotlb:1;
767 u16 sid, qdep;
768 };
769
770 struct intel_svm {
771 struct mmu_notifier notifier;
772 struct mm_struct *mm;
773
774 struct intel_iommu *iommu;
775 unsigned int flags;
776 u32 pasid;
777 int gpasid; /* In case that guest PASID is different from host PASID */
778 struct list_head devs;
779 struct list_head list;
780 };
781 #else
intel_svm_check(struct intel_iommu * iommu)782 static inline void intel_svm_check(struct intel_iommu *iommu) {}
783 #endif
784
785 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS
786 void intel_iommu_debugfs_init(void);
787 #else
intel_iommu_debugfs_init(void)788 static inline void intel_iommu_debugfs_init(void) {}
789 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
790
791 extern const struct attribute_group *intel_iommu_groups[];
792 bool context_present(struct context_entry *context);
793 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
794 u8 devfn, int alloc);
795
796 #ifdef CONFIG_INTEL_IOMMU
797 extern int iommu_calculate_agaw(struct intel_iommu *iommu);
798 extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
799 extern int dmar_disabled;
800 extern int intel_iommu_enabled;
801 extern int intel_iommu_gfx_mapped;
802 #else
iommu_calculate_agaw(struct intel_iommu * iommu)803 static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
804 {
805 return 0;
806 }
iommu_calculate_max_sagaw(struct intel_iommu * iommu)807 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
808 {
809 return 0;
810 }
811 #define dmar_disabled (1)
812 #define intel_iommu_enabled (0)
813 #endif
814
815 #endif
816
