1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
2 /*
3 * Copyright(c) 2015 - 2019 Intel Corporation.
4 */
5
6 #include <linux/pci.h>
7 #include <linux/io.h>
8 #include <linux/delay.h>
9 #include <linux/vmalloc.h>
10 #include <linux/module.h>
11
12 #include "hfi.h"
13 #include "chip_registers.h"
14 #include "aspm.h"
15
16 /*
17 * This file contains PCIe utility routines.
18 */
19
20 /*
21 * Do all the common PCIe setup and initialization.
22 */
hfi1_pcie_init(struct hfi1_devdata * dd)23 int hfi1_pcie_init(struct hfi1_devdata *dd)
24 {
25 int ret;
26 struct pci_dev *pdev = dd->pcidev;
27
28 ret = pci_enable_device(pdev);
29 if (ret) {
30 /*
31 * This can happen (in theory) iff:
32 * We did a chip reset, and then failed to reprogram the
33 * BAR, or the chip reset due to an internal error. We then
34 * unloaded the driver and reloaded it.
35 *
36 * Both reset cases set the BAR back to initial state. For
37 * the latter case, the AER sticky error bit at offset 0x718
38 * should be set, but the Linux kernel doesn't yet know
39 * about that, it appears. If the original BAR was retained
40 * in the kernel data structures, this may be OK.
41 */
42 dd_dev_err(dd, "pci enable failed: error %d\n", -ret);
43 return ret;
44 }
45
46 ret = pci_request_regions(pdev, DRIVER_NAME);
47 if (ret) {
48 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret);
49 goto bail;
50 }
51
52 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
53 if (ret) {
54 /*
55 * If the 64 bit setup fails, try 32 bit. Some systems
56 * do not setup 64 bit maps on systems with 2GB or less
57 * memory installed.
58 */
59 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
60 if (ret) {
61 dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret);
62 goto bail;
63 }
64 }
65
66 pci_set_master(pdev);
67 return 0;
68
69 bail:
70 hfi1_pcie_cleanup(pdev);
71 return ret;
72 }
73
74 /*
75 * Clean what was done in hfi1_pcie_init()
76 */
hfi1_pcie_cleanup(struct pci_dev * pdev)77 void hfi1_pcie_cleanup(struct pci_dev *pdev)
78 {
79 pci_disable_device(pdev);
80 /*
81 * Release regions should be called after the disable. OK to
82 * call if request regions has not been called or failed.
83 */
84 pci_release_regions(pdev);
85 }
86
87 /*
88 * Do remaining PCIe setup, once dd is allocated, and save away
89 * fields required to re-initialize after a chip reset, or for
90 * various other purposes
91 */
hfi1_pcie_ddinit(struct hfi1_devdata * dd,struct pci_dev * pdev)92 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
93 {
94 unsigned long len;
95 resource_size_t addr;
96 int ret = 0;
97 u32 rcv_array_count;
98
99 addr = pci_resource_start(pdev, 0);
100 len = pci_resource_len(pdev, 0);
101
102 /*
103 * The TXE PIO buffers are at the tail end of the chip space.
104 * Cut them off and map them separately.
105 */
106
107 /* sanity check vs expectations */
108 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) {
109 dd_dev_err(dd, "chip PIO range does not match\n");
110 return -EINVAL;
111 }
112
113 dd->kregbase1 = ioremap(addr, RCV_ARRAY);
114 if (!dd->kregbase1) {
115 dd_dev_err(dd, "UC mapping of kregbase1 failed\n");
116 return -ENOMEM;
117 }
118 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY);
119
120 /* verify that reads actually work, save revision for reset check */
121 dd->revision = readq(dd->kregbase1 + CCE_REVISION);
122 if (dd->revision == ~(u64)0) {
123 dd_dev_err(dd, "Cannot read chip CSRs\n");
124 goto nomem;
125 }
126
127 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT);
128 dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count);
129 dd->base2_start = RCV_ARRAY + rcv_array_count * 8;
130
131 dd->kregbase2 = ioremap(
132 addr + dd->base2_start,
133 TXE_PIO_SEND - dd->base2_start);
134 if (!dd->kregbase2) {
135 dd_dev_err(dd, "UC mapping of kregbase2 failed\n");
136 goto nomem;
137 }
138 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2,
139 TXE_PIO_SEND - dd->base2_start);
140
141 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE);
142 if (!dd->piobase) {
143 dd_dev_err(dd, "WC mapping of send buffers failed\n");
144 goto nomem;
145 }
146 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE);
147
148 dd->physaddr = addr; /* used for io_remap, etc. */
149
150 /*
151 * Map the chip's RcvArray as write-combining to allow us
152 * to write an entire cacheline worth of entries in one shot.
153 */
154 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY,
155 rcv_array_count * 8);
156 if (!dd->rcvarray_wc) {
157 dd_dev_err(dd, "WC mapping of receive array failed\n");
158 goto nomem;
159 }
160 dd_dev_info(dd, "WC RcvArray: %p for %x\n",
161 dd->rcvarray_wc, rcv_array_count * 8);
162
163 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */
164 return 0;
165 nomem:
166 ret = -ENOMEM;
167 hfi1_pcie_ddcleanup(dd);
168 return ret;
169 }
170
171 /*
172 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
173 * to releasing the dd memory.
174 * Void because all of the core pcie cleanup functions are void.
175 */
hfi1_pcie_ddcleanup(struct hfi1_devdata * dd)176 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd)
177 {
178 dd->flags &= ~HFI1_PRESENT;
179 if (dd->kregbase1)
180 iounmap(dd->kregbase1);
181 dd->kregbase1 = NULL;
182 if (dd->kregbase2)
183 iounmap(dd->kregbase2);
184 dd->kregbase2 = NULL;
185 if (dd->rcvarray_wc)
186 iounmap(dd->rcvarray_wc);
187 dd->rcvarray_wc = NULL;
188 if (dd->piobase)
189 iounmap(dd->piobase);
190 dd->piobase = NULL;
191 }
192
193 /* return the PCIe link speed from the given link status */
extract_speed(u16 linkstat)194 static u32 extract_speed(u16 linkstat)
195 {
196 u32 speed;
197
198 switch (linkstat & PCI_EXP_LNKSTA_CLS) {
199 default: /* not defined, assume Gen1 */
200 case PCI_EXP_LNKSTA_CLS_2_5GB:
201 speed = 2500; /* Gen 1, 2.5GHz */
202 break;
203 case PCI_EXP_LNKSTA_CLS_5_0GB:
204 speed = 5000; /* Gen 2, 5GHz */
205 break;
206 case PCI_EXP_LNKSTA_CLS_8_0GB:
207 speed = 8000; /* Gen 3, 8GHz */
208 break;
209 }
210 return speed;
211 }
212
213 /* return the PCIe link speed from the given link status */
extract_width(u16 linkstat)214 static u32 extract_width(u16 linkstat)
215 {
216 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
217 }
218
219 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
update_lbus_info(struct hfi1_devdata * dd)220 static void update_lbus_info(struct hfi1_devdata *dd)
221 {
222 u16 linkstat;
223 int ret;
224
225 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
226 if (ret) {
227 dd_dev_err(dd, "Unable to read from PCI config\n");
228 return;
229 }
230
231 dd->lbus_width = extract_width(linkstat);
232 dd->lbus_speed = extract_speed(linkstat);
233 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
234 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width);
235 }
236
237 /*
238 * Read in the current PCIe link width and speed. Find if the link is
239 * Gen3 capable.
240 */
pcie_speeds(struct hfi1_devdata * dd)241 int pcie_speeds(struct hfi1_devdata *dd)
242 {
243 u32 linkcap;
244 struct pci_dev *parent = dd->pcidev->bus->self;
245 int ret;
246
247 if (!pci_is_pcie(dd->pcidev)) {
248 dd_dev_err(dd, "Can't find PCI Express capability!\n");
249 return -EINVAL;
250 }
251
252 /* find if our max speed is Gen3 and parent supports Gen3 speeds */
253 dd->link_gen3_capable = 1;
254
255 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap);
256 if (ret) {
257 dd_dev_err(dd, "Unable to read from PCI config\n");
258 return pcibios_err_to_errno(ret);
259 }
260
261 if ((linkcap & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_8_0GB) {
262 dd_dev_info(dd,
263 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n",
264 linkcap & PCI_EXP_LNKCAP_SLS);
265 dd->link_gen3_capable = 0;
266 }
267
268 /*
269 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed
270 */
271 if (parent &&
272 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT ||
273 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) {
274 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n");
275 dd->link_gen3_capable = 0;
276 }
277
278 /* obtain the link width and current speed */
279 update_lbus_info(dd);
280
281 dd_dev_info(dd, "%s\n", dd->lbus_info);
282
283 return 0;
284 }
285
286 /*
287 * Restore command and BARs after a reset has wiped them out
288 *
289 * Returns 0 on success, otherwise a negative error value
290 */
restore_pci_variables(struct hfi1_devdata * dd)291 int restore_pci_variables(struct hfi1_devdata *dd)
292 {
293 int ret;
294
295 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command);
296 if (ret)
297 goto error;
298
299 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
300 dd->pcibar0);
301 if (ret)
302 goto error;
303
304 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
305 dd->pcibar1);
306 if (ret)
307 goto error;
308
309 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom);
310 if (ret)
311 goto error;
312
313 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL,
314 dd->pcie_devctl);
315 if (ret)
316 goto error;
317
318 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL,
319 dd->pcie_lnkctl);
320 if (ret)
321 goto error;
322
323 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2,
324 dd->pcie_devctl2);
325 if (ret)
326 goto error;
327
328 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0);
329 if (ret)
330 goto error;
331
332 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
333 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2,
334 dd->pci_tph2);
335 if (ret)
336 goto error;
337 }
338 return 0;
339
340 error:
341 dd_dev_err(dd, "Unable to write to PCI config\n");
342 return pcibios_err_to_errno(ret);
343 }
344
345 /*
346 * Save BARs and command to rewrite after device reset
347 *
348 * Returns 0 on success, otherwise a negative error value
349 */
save_pci_variables(struct hfi1_devdata * dd)350 int save_pci_variables(struct hfi1_devdata *dd)
351 {
352 int ret;
353
354 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
355 &dd->pcibar0);
356 if (ret)
357 goto error;
358
359 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
360 &dd->pcibar1);
361 if (ret)
362 goto error;
363
364 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
365 if (ret)
366 goto error;
367
368 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);
369 if (ret)
370 goto error;
371
372 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL,
373 &dd->pcie_devctl);
374 if (ret)
375 goto error;
376
377 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL,
378 &dd->pcie_lnkctl);
379 if (ret)
380 goto error;
381
382 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2,
383 &dd->pcie_devctl2);
384 if (ret)
385 goto error;
386
387 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0);
388 if (ret)
389 goto error;
390
391 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
392 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2,
393 &dd->pci_tph2);
394 if (ret)
395 goto error;
396 }
397 return 0;
398
399 error:
400 dd_dev_err(dd, "Unable to read from PCI config\n");
401 return pcibios_err_to_errno(ret);
402 }
403
404 /*
405 * BIOS may not set PCIe bus-utilization parameters for best performance.
406 * Check and optionally adjust them to maximize our throughput.
407 */
408 static int hfi1_pcie_caps;
409 module_param_named(pcie_caps, hfi1_pcie_caps, int, 0444);
410 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
411
412 /**
413 * tune_pcie_caps() - Code to adjust PCIe capabilities.
414 * @dd: Valid device data structure
415 *
416 */
tune_pcie_caps(struct hfi1_devdata * dd)417 void tune_pcie_caps(struct hfi1_devdata *dd)
418 {
419 struct pci_dev *parent;
420 u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
421 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl;
422 int ret;
423
424 /*
425 * Turn on extended tags in DevCtl in case the BIOS has turned it off
426 * to improve WFR SDMA bandwidth
427 */
428 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
429 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) {
430 dd_dev_info(dd, "Enabling PCIe extended tags\n");
431 ectl |= PCI_EXP_DEVCTL_EXT_TAG;
432 ret = pcie_capability_write_word(dd->pcidev,
433 PCI_EXP_DEVCTL, ectl);
434 if (ret)
435 dd_dev_info(dd, "Unable to write to PCI config\n");
436 }
437 /* Find out supported and configured values for parent (root) */
438 parent = dd->pcidev->bus->self;
439 /*
440 * The driver cannot perform the tuning if it does not have
441 * access to the upstream component.
442 */
443 if (!parent) {
444 dd_dev_info(dd, "Parent not found\n");
445 return;
446 }
447 if (!pci_is_root_bus(parent->bus)) {
448 dd_dev_info(dd, "Parent not root\n");
449 return;
450 }
451 if (!pci_is_pcie(parent)) {
452 dd_dev_info(dd, "Parent is not PCI Express capable\n");
453 return;
454 }
455 if (!pci_is_pcie(dd->pcidev)) {
456 dd_dev_info(dd, "PCI device is not PCI Express capable\n");
457 return;
458 }
459 rc_mpss = parent->pcie_mpss;
460 rc_mps = ffs(pcie_get_mps(parent)) - 8;
461 /* Find out supported and configured values for endpoint (us) */
462 ep_mpss = dd->pcidev->pcie_mpss;
463 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
464
465 /* Find max payload supported by root, endpoint */
466 if (rc_mpss > ep_mpss)
467 rc_mpss = ep_mpss;
468
469 /* If Supported greater than limit in module param, limit it */
470 if (rc_mpss > (hfi1_pcie_caps & 7))
471 rc_mpss = hfi1_pcie_caps & 7;
472 /* If less than (allowed, supported), bump root payload */
473 if (rc_mpss > rc_mps) {
474 rc_mps = rc_mpss;
475 pcie_set_mps(parent, 128 << rc_mps);
476 }
477 /* If less than (allowed, supported), bump endpoint payload */
478 if (rc_mpss > ep_mps) {
479 ep_mps = rc_mpss;
480 pcie_set_mps(dd->pcidev, 128 << ep_mps);
481 }
482
483 /*
484 * Now the Read Request size.
485 * No field for max supported, but PCIe spec limits it to 4096,
486 * which is code '5' (log2(4096) - 7)
487 */
488 max_mrrs = 5;
489 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7))
490 max_mrrs = (hfi1_pcie_caps >> 4) & 7;
491
492 max_mrrs = 128 << max_mrrs;
493 rc_mrrs = pcie_get_readrq(parent);
494 ep_mrrs = pcie_get_readrq(dd->pcidev);
495
496 if (max_mrrs > rc_mrrs) {
497 rc_mrrs = max_mrrs;
498 pcie_set_readrq(parent, rc_mrrs);
499 }
500 if (max_mrrs > ep_mrrs) {
501 ep_mrrs = max_mrrs;
502 pcie_set_readrq(dd->pcidev, ep_mrrs);
503 }
504 }
505
506 /* End of PCIe capability tuning */
507
508 /*
509 * From here through hfi1_pci_err_handler definition is invoked via
510 * PCI error infrastructure, registered via pci
511 */
512 static pci_ers_result_t
pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)513 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
514 {
515 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
516 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
517
518 switch (state) {
519 case pci_channel_io_normal:
520 dd_dev_info(dd, "State Normal, ignoring\n");
521 break;
522
523 case pci_channel_io_frozen:
524 dd_dev_info(dd, "State Frozen, requesting reset\n");
525 pci_disable_device(pdev);
526 ret = PCI_ERS_RESULT_NEED_RESET;
527 break;
528
529 case pci_channel_io_perm_failure:
530 if (dd) {
531 dd_dev_info(dd, "State Permanent Failure, disabling\n");
532 /* no more register accesses! */
533 dd->flags &= ~HFI1_PRESENT;
534 hfi1_disable_after_error(dd);
535 }
536 /* else early, or other problem */
537 ret = PCI_ERS_RESULT_DISCONNECT;
538 break;
539
540 default: /* shouldn't happen */
541 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n",
542 state);
543 break;
544 }
545 return ret;
546 }
547
548 static pci_ers_result_t
pci_mmio_enabled(struct pci_dev * pdev)549 pci_mmio_enabled(struct pci_dev *pdev)
550 {
551 u64 words = 0U;
552 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
553 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
554
555 if (dd && dd->pport) {
556 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL);
557 if (words == ~0ULL)
558 ret = PCI_ERS_RESULT_NEED_RESET;
559 dd_dev_info(dd,
560 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n",
561 words, ret);
562 }
563 return ret;
564 }
565
566 static pci_ers_result_t
pci_slot_reset(struct pci_dev * pdev)567 pci_slot_reset(struct pci_dev *pdev)
568 {
569 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
570
571 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n");
572 return PCI_ERS_RESULT_CAN_RECOVER;
573 }
574
575 static void
pci_resume(struct pci_dev * pdev)576 pci_resume(struct pci_dev *pdev)
577 {
578 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
579
580 dd_dev_info(dd, "HFI1 resume function called\n");
581 /*
582 * Running jobs will fail, since it's asynchronous
583 * unlike sysfs-requested reset. Better than
584 * doing nothing.
585 */
586 hfi1_init(dd, 1); /* same as re-init after reset */
587 }
588
589 const struct pci_error_handlers hfi1_pci_err_handler = {
590 .error_detected = pci_error_detected,
591 .mmio_enabled = pci_mmio_enabled,
592 .slot_reset = pci_slot_reset,
593 .resume = pci_resume,
594 };
595
596 /*============================================================================*/
597 /* PCIe Gen3 support */
598
599 /*
600 * This code is separated out because it is expected to be removed in the
601 * final shipping product. If not, then it will be revisited and items
602 * will be moved to more standard locations.
603 */
604
605 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */
606 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */
607 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */
608 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */
609
610 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */
611 #define DL_ERR_NONE 0x0 /* no error */
612 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */
613 /* or response data */
614 #define DL_ERR_DISABLED 0x2 /* hfi disabled */
615 #define DL_ERR_SECURITY 0x3 /* security check failed */
616 #define DL_ERR_SBUS 0x4 /* SBus status error */
617 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/
618
619 /* gasket block secondary bus reset delay */
620 #define SBR_DELAY_US 200000 /* 200ms */
621
622 static uint pcie_target = 3;
623 module_param(pcie_target, uint, S_IRUGO);
624 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)");
625
626 static uint pcie_force;
627 module_param(pcie_force, uint, S_IRUGO);
628 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed");
629
630 static uint pcie_retry = 5;
631 module_param(pcie_retry, uint, S_IRUGO);
632 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed");
633
634 #define UNSET_PSET 255
635 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */
636 #define DEFAULT_MCP_PSET 6 /* MCP HFI */
637 static uint pcie_pset = UNSET_PSET;
638 module_param(pcie_pset, uint, S_IRUGO);
639 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
640
641 static uint pcie_ctle = 3; /* discrete on, integrated on */
642 module_param(pcie_ctle, uint, S_IRUGO);
643 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off");
644
645 /* equalization columns */
646 #define PREC 0
647 #define ATTN 1
648 #define POST 2
649
650 /* discrete silicon preliminary equalization values */
651 static const u8 discrete_preliminary_eq[11][3] = {
652 /* prec attn post */
653 { 0x00, 0x00, 0x12 }, /* p0 */
654 { 0x00, 0x00, 0x0c }, /* p1 */
655 { 0x00, 0x00, 0x0f }, /* p2 */
656 { 0x00, 0x00, 0x09 }, /* p3 */
657 { 0x00, 0x00, 0x00 }, /* p4 */
658 { 0x06, 0x00, 0x00 }, /* p5 */
659 { 0x09, 0x00, 0x00 }, /* p6 */
660 { 0x06, 0x00, 0x0f }, /* p7 */
661 { 0x09, 0x00, 0x09 }, /* p8 */
662 { 0x0c, 0x00, 0x00 }, /* p9 */
663 { 0x00, 0x00, 0x18 }, /* p10 */
664 };
665
666 /* integrated silicon preliminary equalization values */
667 static const u8 integrated_preliminary_eq[11][3] = {
668 /* prec attn post */
669 { 0x00, 0x1e, 0x07 }, /* p0 */
670 { 0x00, 0x1e, 0x05 }, /* p1 */
671 { 0x00, 0x1e, 0x06 }, /* p2 */
672 { 0x00, 0x1e, 0x04 }, /* p3 */
673 { 0x00, 0x1e, 0x00 }, /* p4 */
674 { 0x03, 0x1e, 0x00 }, /* p5 */
675 { 0x04, 0x1e, 0x00 }, /* p6 */
676 { 0x03, 0x1e, 0x06 }, /* p7 */
677 { 0x03, 0x1e, 0x04 }, /* p8 */
678 { 0x05, 0x1e, 0x00 }, /* p9 */
679 { 0x00, 0x1e, 0x0a }, /* p10 */
680 };
681
682 static const u8 discrete_ctle_tunings[11][4] = {
683 /* DC LF HF BW */
684 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */
685 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */
686 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */
687 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */
688 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */
689 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */
690 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */
691 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
692 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */
693 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */
694 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */
695 };
696
697 static const u8 integrated_ctle_tunings[11][4] = {
698 /* DC LF HF BW */
699 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */
700 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */
701 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */
702 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */
703 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */
704 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */
705 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */
706 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
707 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */
708 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */
709 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */
710 };
711
712 /* helper to format the value to write to hardware */
713 #define eq_value(pre, curr, post) \
714 ((((u32)(pre)) << \
715 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \
716 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \
717 | (((u32)(post)) << \
718 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT))
719
720 /*
721 * Load the given EQ preset table into the PCIe hardware.
722 */
load_eq_table(struct hfi1_devdata * dd,const u8 eq[11][3],u8 fs,u8 div)723 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs,
724 u8 div)
725 {
726 struct pci_dev *pdev = dd->pcidev;
727 u32 hit_error = 0;
728 u32 violation;
729 u32 i;
730 u8 c_minus1, c0, c_plus1;
731 int ret;
732
733 for (i = 0; i < 11; i++) {
734 /* set index */
735 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i);
736 /* write the value */
737 c_minus1 = eq[i][PREC] / div;
738 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div);
739 c_plus1 = eq[i][POST] / div;
740 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102,
741 eq_value(c_minus1, c0, c_plus1));
742 /* check if these coefficients violate EQ rules */
743 ret = pci_read_config_dword(dd->pcidev,
744 PCIE_CFG_REG_PL105, &violation);
745 if (ret) {
746 dd_dev_err(dd, "Unable to read from PCI config\n");
747 hit_error = 1;
748 break;
749 }
750
751 if (violation
752 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){
753 if (hit_error == 0) {
754 dd_dev_err(dd,
755 "Gen3 EQ Table Coefficient rule violations\n");
756 dd_dev_err(dd, " prec attn post\n");
757 }
758 dd_dev_err(dd, " p%02d: %02x %02x %02x\n",
759 i, (u32)eq[i][0], (u32)eq[i][1],
760 (u32)eq[i][2]);
761 dd_dev_err(dd, " %02x %02x %02x\n",
762 (u32)c_minus1, (u32)c0, (u32)c_plus1);
763 hit_error = 1;
764 }
765 }
766 if (hit_error)
767 return -EINVAL;
768 return 0;
769 }
770
771 /*
772 * Steps to be done after the PCIe firmware is downloaded and
773 * before the SBR for the Pcie Gen3.
774 * The SBus resource is already being held.
775 */
pcie_post_steps(struct hfi1_devdata * dd)776 static void pcie_post_steps(struct hfi1_devdata *dd)
777 {
778 int i;
779
780 set_sbus_fast_mode(dd);
781 /*
782 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1.
783 * This avoids a spurious framing error that can otherwise be
784 * generated by the MAC layer.
785 *
786 * Use individual addresses since no broadcast is set up.
787 */
788 for (i = 0; i < NUM_PCIE_SERDES; i++) {
789 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i],
790 0x03, WRITE_SBUS_RECEIVER, 0x00022132);
791 }
792
793 clear_sbus_fast_mode(dd);
794 }
795
796 /*
797 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
798 *
799 * Based on pci_parent_bus_reset() which is not exported by the
800 * kernel core.
801 */
trigger_sbr(struct hfi1_devdata * dd)802 static int trigger_sbr(struct hfi1_devdata *dd)
803 {
804 struct pci_dev *dev = dd->pcidev;
805 struct pci_dev *pdev;
806
807 /* need a parent */
808 if (!dev->bus->self) {
809 dd_dev_err(dd, "%s: no parent device\n", __func__);
810 return -ENOTTY;
811 }
812
813 /* should not be anyone else on the bus */
814 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
815 if (pdev != dev) {
816 dd_dev_err(dd,
817 "%s: another device is on the same bus\n",
818 __func__);
819 return -ENOTTY;
820 }
821
822 /*
823 * This is an end around to do an SBR during probe time. A new API needs
824 * to be implemented to have cleaner interface but this fixes the
825 * current brokenness
826 */
827 return pci_bridge_secondary_bus_reset(dev->bus->self);
828 }
829
830 /*
831 * Write the given gasket interrupt register.
832 */
write_gasket_interrupt(struct hfi1_devdata * dd,int index,u16 code,u16 data)833 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index,
834 u16 code, u16 data)
835 {
836 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
837 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) |
838 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT)));
839 }
840
841 /*
842 * Tell the gasket logic how to react to the reset.
843 */
arm_gasket_logic(struct hfi1_devdata * dd)844 static void arm_gasket_logic(struct hfi1_devdata *dd)
845 {
846 u64 reg;
847
848 reg = (((u64)1 << dd->hfi1_id) <<
849 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) |
850 ((u64)pcie_serdes_broadcast[dd->hfi1_id] <<
851 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT |
852 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK |
853 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) <<
854 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT);
855 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
856 /* read back to push the write */
857 read_csr(dd, ASIC_PCIE_SD_HOST_CMD);
858 }
859
860 /*
861 * CCE_PCIE_CTRL long name helpers
862 * We redefine these shorter macros to use in the code while leaving
863 * chip_registers.h to be autogenerated from the hardware spec.
864 */
865 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK
866 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT
867 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK
868 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT
869 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT
870 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT
871 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK
872 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT
873 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK
874 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT
875
876 /*
877 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
878 */
write_xmt_margin(struct hfi1_devdata * dd,const char * fname)879 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname)
880 {
881 u64 pcie_ctrl;
882 u64 xmt_margin;
883 u64 xmt_margin_oe;
884 u64 lane_delay;
885 u64 lane_bundle;
886
887 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL);
888
889 /*
890 * For Discrete, use full-swing.
891 * - PCIe TX defaults to full-swing.
892 * Leave this register as default.
893 * For Integrated, use half-swing
894 * - Copy xmt_margin and xmt_margin_oe
895 * from Gen1/Gen2 to Gen3.
896 */
897 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */
898 /* extract initial fields */
899 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT)
900 & MARGIN_GEN1_GEN2_MASK;
901 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT)
902 & MARGIN_G1_G2_OVERWRITE_MASK;
903 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK;
904 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT)
905 & LANE_BUNDLE_MASK;
906
907 /*
908 * For A0, EFUSE values are not set. Override with the
909 * correct values.
910 */
911 if (is_ax(dd)) {
912 /*
913 * xmt_margin and OverwiteEnabel should be the
914 * same for Gen1/Gen2 and Gen3
915 */
916 xmt_margin = 0x5;
917 xmt_margin_oe = 0x1;
918 lane_delay = 0xF; /* Delay 240ns. */
919 lane_bundle = 0x0; /* Set to 1 lane. */
920 }
921
922 /* overwrite existing values */
923 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT)
924 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT)
925 | (xmt_margin << MARGIN_SHIFT)
926 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT)
927 | (lane_delay << LANE_DELAY_SHIFT)
928 | (lane_bundle << LANE_BUNDLE_SHIFT);
929
930 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl);
931 }
932
933 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n",
934 fname, pcie_ctrl);
935 }
936
937 /*
938 * Do all the steps needed to transition the PCIe link to Gen3 speed.
939 */
do_pcie_gen3_transition(struct hfi1_devdata * dd)940 int do_pcie_gen3_transition(struct hfi1_devdata *dd)
941 {
942 struct pci_dev *parent = dd->pcidev->bus->self;
943 u64 fw_ctrl;
944 u64 reg, therm;
945 u32 reg32, fs, lf;
946 u32 status, err;
947 int ret;
948 int do_retry, retry_count = 0;
949 int intnum = 0;
950 uint default_pset;
951 uint pset = pcie_pset;
952 u16 target_vector, target_speed;
953 u16 lnkctl2, vendor;
954 u8 div;
955 const u8 (*eq)[3];
956 const u8 (*ctle_tunings)[4];
957 uint static_ctle_mode;
958 int return_error = 0;
959 u32 target_width;
960
961 /* PCIe Gen3 is for the ASIC only */
962 if (dd->icode != ICODE_RTL_SILICON)
963 return 0;
964
965 if (pcie_target == 1) { /* target Gen1 */
966 target_vector = PCI_EXP_LNKCTL2_TLS_2_5GT;
967 target_speed = 2500;
968 } else if (pcie_target == 2) { /* target Gen2 */
969 target_vector = PCI_EXP_LNKCTL2_TLS_5_0GT;
970 target_speed = 5000;
971 } else if (pcie_target == 3) { /* target Gen3 */
972 target_vector = PCI_EXP_LNKCTL2_TLS_8_0GT;
973 target_speed = 8000;
974 } else {
975 /* off or invalid target - skip */
976 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__);
977 return 0;
978 }
979
980 /* if already at target speed, done (unless forced) */
981 if (dd->lbus_speed == target_speed) {
982 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__,
983 pcie_target,
984 pcie_force ? "re-doing anyway" : "skipping");
985 if (!pcie_force)
986 return 0;
987 }
988
989 /*
990 * The driver cannot do the transition if it has no access to the
991 * upstream component
992 */
993 if (!parent) {
994 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n",
995 __func__);
996 return 0;
997 }
998
999 /* Previous Gen1/Gen2 bus width */
1000 target_width = dd->lbus_width;
1001
1002 /*
1003 * Do the Gen3 transition. Steps are those of the PCIe Gen3
1004 * recipe.
1005 */
1006
1007 /* step 1: pcie link working in gen1/gen2 */
1008
1009 /* step 2: if either side is not capable of Gen3, done */
1010 if (pcie_target == 3 && !dd->link_gen3_capable) {
1011 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n");
1012 ret = -ENOSYS;
1013 goto done_no_mutex;
1014 }
1015
1016 /* hold the SBus resource across the firmware download and SBR */
1017 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1018 if (ret) {
1019 dd_dev_err(dd, "%s: unable to acquire SBus resource\n",
1020 __func__);
1021 return ret;
1022 }
1023
1024 /* make sure thermal polling is not causing interrupts */
1025 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN);
1026 if (therm) {
1027 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
1028 msleep(100);
1029 dd_dev_info(dd, "%s: Disabled therm polling\n",
1030 __func__);
1031 }
1032
1033 retry:
1034 /* the SBus download will reset the spico for thermal */
1035
1036 /* step 3: download SBus Master firmware */
1037 /* step 4: download PCIe Gen3 SerDes firmware */
1038 dd_dev_info(dd, "%s: downloading firmware\n", __func__);
1039 ret = load_pcie_firmware(dd);
1040 if (ret) {
1041 /* do not proceed if the firmware cannot be downloaded */
1042 return_error = 1;
1043 goto done;
1044 }
1045
1046 /* step 5: set up device parameter settings */
1047 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__);
1048
1049 /*
1050 * PcieCfgSpcie1 - Link Control 3
1051 * Leave at reset value. No need to set PerfEq - link equalization
1052 * will be performed automatically after the SBR when the target
1053 * speed is 8GT/s.
1054 */
1055
1056 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */
1057 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff);
1058
1059 /* step 5a: Set Synopsys Port Logic registers */
1060
1061 /*
1062 * PcieCfgRegPl2 - Port Force Link
1063 *
1064 * Set the low power field to 0x10 to avoid unnecessary power
1065 * management messages. All other fields are zero.
1066 */
1067 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT;
1068 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32);
1069
1070 /*
1071 * PcieCfgRegPl100 - Gen3 Control
1072 *
1073 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl
1074 * turn on PcieCfgRegPl100.EqEieosCnt
1075 * Everything else zero.
1076 */
1077 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK;
1078 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32);
1079
1080 /*
1081 * PcieCfgRegPl101 - Gen3 EQ FS and LF
1082 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping
1083 * PcieCfgRegPl103 - Gen3 EQ Preset Index
1084 * PcieCfgRegPl105 - Gen3 EQ Status
1085 *
1086 * Give initial EQ settings.
1087 */
1088 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */
1089 /* 1000mV, FS=24, LF = 8 */
1090 fs = 24;
1091 lf = 8;
1092 div = 3;
1093 eq = discrete_preliminary_eq;
1094 default_pset = DEFAULT_DISCRETE_PSET;
1095 ctle_tunings = discrete_ctle_tunings;
1096 /* bit 0 - discrete on/off */
1097 static_ctle_mode = pcie_ctle & 0x1;
1098 } else {
1099 /* 400mV, FS=29, LF = 9 */
1100 fs = 29;
1101 lf = 9;
1102 div = 1;
1103 eq = integrated_preliminary_eq;
1104 default_pset = DEFAULT_MCP_PSET;
1105 ctle_tunings = integrated_ctle_tunings;
1106 /* bit 1 - integrated on/off */
1107 static_ctle_mode = (pcie_ctle >> 1) & 0x1;
1108 }
1109 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101,
1110 (fs <<
1111 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) |
1112 (lf <<
1113 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT));
1114 ret = load_eq_table(dd, eq, fs, div);
1115 if (ret)
1116 goto done;
1117
1118 /*
1119 * PcieCfgRegPl106 - Gen3 EQ Control
1120 *
1121 * Set Gen3EqPsetReqVec, leave other fields 0.
1122 */
1123 if (pset == UNSET_PSET)
1124 pset = default_pset;
1125 if (pset > 10) { /* valid range is 0-10, inclusive */
1126 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n",
1127 __func__, pset, default_pset);
1128 pset = default_pset;
1129 }
1130 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset);
1131 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106,
1132 ((1 << pset) <<
1133 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) |
1134 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK |
1135 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK);
1136
1137 /*
1138 * step 5b: Do post firmware download steps via SBus
1139 */
1140 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__);
1141 pcie_post_steps(dd);
1142
1143 /*
1144 * step 5c: Program gasket interrupts
1145 */
1146 /* set the Rx Bit Rate to REFCLK ratio */
1147 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050);
1148 /* disable pCal for PCIe Gen3 RX equalization */
1149 /* select adaptive or static CTLE */
1150 write_gasket_interrupt(dd, intnum++, 0x0026,
1151 0x5b01 | (static_ctle_mode << 3));
1152 /*
1153 * Enable iCal for PCIe Gen3 RX equalization, and set which
1154 * evaluation of RX_EQ_EVAL will launch the iCal procedure.
1155 */
1156 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202);
1157
1158 if (static_ctle_mode) {
1159 /* apply static CTLE tunings */
1160 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw;
1161
1162 pcie_dc = ctle_tunings[pset][0];
1163 pcie_lf = ctle_tunings[pset][1];
1164 pcie_hf = ctle_tunings[pset][2];
1165 pcie_bw = ctle_tunings[pset][3];
1166 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc);
1167 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf);
1168 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf);
1169 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw);
1170 }
1171
1172 /* terminate list */
1173 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000);
1174
1175 /*
1176 * step 5d: program XMT margin
1177 */
1178 write_xmt_margin(dd, __func__);
1179
1180 /*
1181 * step 5e: disable active state power management (ASPM). It
1182 * will be enabled if required later
1183 */
1184 dd_dev_info(dd, "%s: clearing ASPM\n", __func__);
1185 aspm_hw_disable_l1(dd);
1186
1187 /*
1188 * step 5f: clear DirectSpeedChange
1189 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the
1190 * change in the speed target from starting before we are ready.
1191 * This field defaults to 0 and we are not changing it, so nothing
1192 * needs to be done.
1193 */
1194
1195 /* step 5g: Set target link speed */
1196 /*
1197 * Set target link speed to be target on both device and parent.
1198 * On setting the parent: Some system BIOSs "helpfully" set the
1199 * parent target speed to Gen2 to match the ASIC's initial speed.
1200 * We can set the target Gen3 because we have already checked
1201 * that it is Gen3 capable earlier.
1202 */
1203 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__);
1204 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2);
1205 if (ret) {
1206 dd_dev_err(dd, "Unable to read from PCI config\n");
1207 return_error = 1;
1208 goto done;
1209 }
1210
1211 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1212 (u32)lnkctl2);
1213 /* only write to parent if target is not as high as ours */
1214 if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) {
1215 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
1216 lnkctl2 |= target_vector;
1217 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1218 (u32)lnkctl2);
1219 ret = pcie_capability_write_word(parent,
1220 PCI_EXP_LNKCTL2, lnkctl2);
1221 if (ret) {
1222 dd_dev_err(dd, "Unable to write to PCI config\n");
1223 return_error = 1;
1224 goto done;
1225 }
1226 } else {
1227 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__);
1228 }
1229
1230 dd_dev_info(dd, "%s: setting target link speed\n", __func__);
1231 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2);
1232 if (ret) {
1233 dd_dev_err(dd, "Unable to read from PCI config\n");
1234 return_error = 1;
1235 goto done;
1236 }
1237
1238 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1239 (u32)lnkctl2);
1240 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
1241 lnkctl2 |= target_vector;
1242 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1243 (u32)lnkctl2);
1244 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2);
1245 if (ret) {
1246 dd_dev_err(dd, "Unable to write to PCI config\n");
1247 return_error = 1;
1248 goto done;
1249 }
1250
1251 /* step 5h: arm gasket logic */
1252 /* hold DC in reset across the SBR */
1253 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
1254 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */
1255 /* save firmware control across the SBR */
1256 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL);
1257
1258 dd_dev_info(dd, "%s: arming gasket logic\n", __func__);
1259 arm_gasket_logic(dd);
1260
1261 /*
1262 * step 6: quiesce PCIe link
1263 * The chip has already been reset, so there will be no traffic
1264 * from the chip. Linux has no easy way to enforce that it will
1265 * not try to access the device, so we just need to hope it doesn't
1266 * do it while we are doing the reset.
1267 */
1268
1269 /*
1270 * step 7: initiate the secondary bus reset (SBR)
1271 * step 8: hardware brings the links back up
1272 * step 9: wait for link speed transition to be complete
1273 */
1274 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__);
1275 ret = trigger_sbr(dd);
1276 if (ret)
1277 goto done;
1278
1279 /* step 10: decide what to do next */
1280
1281 /* check if we can read PCI space */
1282 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor);
1283 if (ret) {
1284 dd_dev_info(dd,
1285 "%s: read of VendorID failed after SBR, err %d\n",
1286 __func__, ret);
1287 return_error = 1;
1288 goto done;
1289 }
1290 if (vendor == 0xffff) {
1291 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__);
1292 return_error = 1;
1293 ret = -EIO;
1294 goto done;
1295 }
1296
1297 /* restore PCI space registers we know were reset */
1298 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__);
1299 ret = restore_pci_variables(dd);
1300 if (ret) {
1301 dd_dev_err(dd, "%s: Could not restore PCI variables\n",
1302 __func__);
1303 return_error = 1;
1304 goto done;
1305 }
1306
1307 /* restore firmware control */
1308 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl);
1309
1310 /*
1311 * Check the gasket block status.
1312 *
1313 * This is the first CSR read after the SBR. If the read returns
1314 * all 1s (fails), the link did not make it back.
1315 *
1316 * Once we're sure we can read and write, clear the DC reset after
1317 * the SBR. Then check for any per-lane errors. Then look over
1318 * the status.
1319 */
1320 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS);
1321 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg);
1322 if (reg == ~0ull) { /* PCIe read failed/timeout */
1323 dd_dev_err(dd, "SBR failed - unable to read from device\n");
1324 return_error = 1;
1325 ret = -ENOSYS;
1326 goto done;
1327 }
1328
1329 /* clear the DC reset */
1330 write_csr(dd, CCE_DC_CTRL, 0);
1331
1332 /* Set the LED off */
1333 setextled(dd, 0);
1334
1335 /* check for any per-lane errors */
1336 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32);
1337 if (ret) {
1338 dd_dev_err(dd, "Unable to read from PCI config\n");
1339 return_error = 1;
1340 goto done;
1341 }
1342
1343 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32);
1344
1345 /* extract status, look for our HFI */
1346 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT)
1347 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK;
1348 if ((status & (1 << dd->hfi1_id)) == 0) {
1349 dd_dev_err(dd,
1350 "%s: gasket status 0x%x, expecting 0x%x\n",
1351 __func__, status, 1 << dd->hfi1_id);
1352 ret = -EIO;
1353 goto done;
1354 }
1355
1356 /* extract error */
1357 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT)
1358 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK;
1359 if (err) {
1360 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err);
1361 ret = -EIO;
1362 goto done;
1363 }
1364
1365 /* update our link information cache */
1366 update_lbus_info(dd);
1367 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__,
1368 dd->lbus_info);
1369
1370 if (dd->lbus_speed != target_speed ||
1371 dd->lbus_width < target_width) { /* not target */
1372 /* maybe retry */
1373 do_retry = retry_count < pcie_retry;
1374 dd_dev_err(dd, "PCIe link speed or width did not match target%s\n",
1375 do_retry ? ", retrying" : "");
1376 retry_count++;
1377 if (do_retry) {
1378 msleep(100); /* allow time to settle */
1379 goto retry;
1380 }
1381 ret = -EIO;
1382 }
1383
1384 done:
1385 if (therm) {
1386 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
1387 msleep(100);
1388 dd_dev_info(dd, "%s: Re-enable therm polling\n",
1389 __func__);
1390 }
1391 release_chip_resource(dd, CR_SBUS);
1392 done_no_mutex:
1393 /* return no error if it is OK to be at current speed */
1394 if (ret && !return_error) {
1395 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n");
1396 ret = 0;
1397 }
1398
1399 dd_dev_info(dd, "%s: done\n", __func__);
1400 return ret;
1401 }
1402
