1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * SuperH Pin Function Controller Support 4 * 5 * Copyright (c) 2008 Magnus Damm 6 */ 7 8 #ifndef __SH_PFC_H 9 #define __SH_PFC_H 10 11 #include <linux/bug.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 #include <linux/spinlock.h> 14 #include <linux/stringify.h> 15 16 enum { 17 PINMUX_TYPE_NONE, 18 PINMUX_TYPE_FUNCTION, 19 PINMUX_TYPE_GPIO, 20 PINMUX_TYPE_OUTPUT, 21 PINMUX_TYPE_INPUT, 22 }; 23 24 #define SH_PFC_PIN_NONE U16_MAX 25 26 #define SH_PFC_PIN_CFG_INPUT (1 << 0) 27 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) 28 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) 29 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) 30 #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \ 31 SH_PFC_PIN_CFG_PULL_DOWN) 32 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) 33 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) 34 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) 35 36 struct sh_pfc_pin { 37 u16 pin; 38 u16 enum_id; 39 const char *name; 40 unsigned int configs; 41 }; 42 43 #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ 44 { \ 45 .name = #alias, \ 46 .pins = n##_pins, \ 47 .mux = n##_mux, \ 48 .nr_pins = ARRAY_SIZE(n##_pins) + \ 49 BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ 50 } 51 #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) 52 53 struct sh_pfc_pin_group { 54 const char *name; 55 const unsigned int *pins; 56 const unsigned int *mux; 57 unsigned int nr_pins; 58 }; 59 60 /* 61 * Using union vin_data{,12,16} saves memory occupied by the VIN data pins. 62 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups 63 * in this case. It accepts an optional 'version' argument used when the 64 * same group can appear on a different set of pins. 65 */ 66 #define VIN_DATA_PIN_GROUP(n, s, ...) \ 67 { \ 68 .name = #n#s#__VA_ARGS__, \ 69 .pins = n##__VA_ARGS__##_pins.data##s, \ 70 .mux = n##__VA_ARGS__##_mux.data##s, \ 71 .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \ 72 } 73 74 union vin_data12 { 75 unsigned int data12[12]; 76 unsigned int data10[10]; 77 unsigned int data8[8]; 78 }; 79 80 union vin_data16 { 81 unsigned int data16[16]; 82 unsigned int data12[12]; 83 unsigned int data10[10]; 84 unsigned int data8[8]; 85 }; 86 87 union vin_data { 88 unsigned int data24[24]; 89 unsigned int data20[20]; 90 unsigned int data16[16]; 91 unsigned int data12[12]; 92 unsigned int data10[10]; 93 unsigned int data8[8]; 94 unsigned int data4[4]; 95 }; 96 97 #define SH_PFC_FUNCTION(n) \ 98 { \ 99 .name = #n, \ 100 .groups = n##_groups, \ 101 .nr_groups = ARRAY_SIZE(n##_groups), \ 102 } 103 104 struct sh_pfc_function { 105 const char *name; 106 const char * const *groups; 107 unsigned int nr_groups; 108 }; 109 110 struct pinmux_func { 111 u16 enum_id; 112 const char *name; 113 }; 114 115 struct pinmux_cfg_reg { 116 u32 reg; 117 u8 reg_width, field_width; 118 #ifdef DEBUG 119 u16 nr_enum_ids; /* for variable width regs only */ 120 #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, 121 #else 122 #define SET_NR_ENUM_IDS(n) 123 #endif 124 const u16 *enum_ids; 125 const u8 *var_field_width; 126 }; 127 128 #define GROUP(...) __VA_ARGS__ 129 130 /* 131 * Describe a config register consisting of several fields of the same width 132 * - name: Register name (unused, for documentation purposes only) 133 * - r: Physical register address 134 * - r_width: Width of the register (in bits) 135 * - f_width: Width of the fixed-width register fields (in bits) 136 * - ids: For each register field (from left to right, i.e. MSB to LSB), 137 * 2^f_width enum IDs must be specified, one for each possible 138 * combination of the register field bit values, all wrapped using 139 * the GROUP() macro. 140 */ 141 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ 142 .reg = r, .reg_width = r_width, \ 143 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ 144 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ 145 (r_width / f_width) * (1 << f_width)), \ 146 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ 147 { ids } 148 149 /* 150 * Describe a config register consisting of several fields of different widths 151 * - name: Register name (unused, for documentation purposes only) 152 * - r: Physical register address 153 * - r_width: Width of the register (in bits) 154 * - f_widths: List of widths of the register fields (in bits), from left 155 * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. 156 * - ids: For each register field (from left to right, i.e. MSB to LSB), 157 * 2^f_widths[i] enum IDs must be specified, one for each possible 158 * combination of the register field bit values, all wrapped using 159 * the GROUP() macro. 160 */ 161 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ 162 .reg = r, .reg_width = r_width, \ 163 .var_field_width = (const u8 []) { f_widths, 0 }, \ 164 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ 165 .enum_ids = (const u16 []) { ids } 166 167 struct pinmux_drive_reg_field { 168 u16 pin; 169 u8 offset; 170 u8 size; 171 }; 172 173 struct pinmux_drive_reg { 174 u32 reg; 175 const struct pinmux_drive_reg_field fields[8]; 176 }; 177 178 #define PINMUX_DRIVE_REG(name, r) \ 179 .reg = r, \ 180 .fields = 181 182 struct pinmux_bias_reg { 183 u32 puen; /* Pull-enable or pull-up control register */ 184 u32 pud; /* Pull-up/down control register (optional) */ 185 const u16 pins[32]; 186 }; 187 188 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \ 189 .puen = r1, \ 190 .pud = r2, \ 191 .pins = 192 193 struct pinmux_ioctrl_reg { 194 u32 reg; 195 }; 196 197 struct pinmux_data_reg { 198 u32 reg; 199 u8 reg_width; 200 const u16 *enum_ids; 201 }; 202 203 /* 204 * Describe a data register 205 * - name: Register name (unused, for documentation purposes only) 206 * - r: Physical register address 207 * - r_width: Width of the register (in bits) 208 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one 209 * enum ID must be specified, all wrapped using the GROUP() macro. 210 */ 211 #define PINMUX_DATA_REG(name, r, r_width, ids) \ 212 .reg = r, .reg_width = r_width + \ 213 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ 214 r_width), \ 215 .enum_ids = (const u16 [r_width]) { ids } 216 217 struct pinmux_irq { 218 const short *gpios; 219 }; 220 221 /* 222 * Describe the mapping from GPIOs to a single IRQ 223 * - ids...: List of GPIOs that are mapped to the same IRQ 224 */ 225 #define PINMUX_IRQ(ids...) \ 226 { .gpios = (const short []) { ids, -1 } } 227 228 struct pinmux_range { 229 u16 begin; 230 u16 end; 231 u16 force; 232 }; 233 234 struct sh_pfc_window { 235 phys_addr_t phys; 236 void __iomem *virt; 237 unsigned long size; 238 }; 239 240 struct sh_pfc_pin_range; 241 242 struct sh_pfc { 243 struct device *dev; 244 const struct sh_pfc_soc_info *info; 245 spinlock_t lock; 246 247 unsigned int num_windows; 248 struct sh_pfc_window *windows; 249 unsigned int num_irqs; 250 unsigned int *irqs; 251 252 struct sh_pfc_pin_range *ranges; 253 unsigned int nr_ranges; 254 255 unsigned int nr_gpio_pins; 256 257 struct sh_pfc_chip *gpio; 258 u32 *saved_regs; 259 }; 260 261 struct sh_pfc_soc_operations { 262 int (*init)(struct sh_pfc *pfc); 263 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 264 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 265 unsigned int bias); 266 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); 267 }; 268 269 struct sh_pfc_soc_info { 270 const char *name; 271 const struct sh_pfc_soc_operations *ops; 272 273 struct pinmux_range input; 274 struct pinmux_range output; 275 struct pinmux_range function; 276 277 const struct sh_pfc_pin *pins; 278 unsigned int nr_pins; 279 const struct sh_pfc_pin_group *groups; 280 unsigned int nr_groups; 281 const struct sh_pfc_function *functions; 282 unsigned int nr_functions; 283 284 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO 285 const struct pinmux_func *func_gpios; 286 unsigned int nr_func_gpios; 287 #endif 288 289 const struct pinmux_cfg_reg *cfg_regs; 290 const struct pinmux_drive_reg *drive_regs; 291 const struct pinmux_bias_reg *bias_regs; 292 const struct pinmux_ioctrl_reg *ioctrl_regs; 293 const struct pinmux_data_reg *data_regs; 294 295 const u16 *pinmux_data; 296 unsigned int pinmux_data_size; 297 298 const struct pinmux_irq *gpio_irq; 299 unsigned int gpio_irq_size; 300 301 u32 unlock_reg; 302 }; 303 304 extern const struct sh_pfc_soc_info emev2_pinmux_info; 305 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; 306 extern const struct sh_pfc_soc_info r8a7740_pinmux_info; 307 extern const struct sh_pfc_soc_info r8a7742_pinmux_info; 308 extern const struct sh_pfc_soc_info r8a7743_pinmux_info; 309 extern const struct sh_pfc_soc_info r8a7744_pinmux_info; 310 extern const struct sh_pfc_soc_info r8a7745_pinmux_info; 311 extern const struct sh_pfc_soc_info r8a77470_pinmux_info; 312 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; 313 extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; 314 extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; 315 extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; 316 extern const struct sh_pfc_soc_info r8a7778_pinmux_info; 317 extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 318 extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 319 extern const struct sh_pfc_soc_info r8a7791_pinmux_info; 320 extern const struct sh_pfc_soc_info r8a7792_pinmux_info; 321 extern const struct sh_pfc_soc_info r8a7793_pinmux_info; 322 extern const struct sh_pfc_soc_info r8a7794_pinmux_info; 323 extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak; 324 extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak; 325 extern const struct sh_pfc_soc_info r8a77960_pinmux_info; 326 extern const struct sh_pfc_soc_info r8a77961_pinmux_info; 327 extern const struct sh_pfc_soc_info r8a77965_pinmux_info; 328 extern const struct sh_pfc_soc_info r8a77970_pinmux_info; 329 extern const struct sh_pfc_soc_info r8a77980_pinmux_info; 330 extern const struct sh_pfc_soc_info r8a77990_pinmux_info; 331 extern const struct sh_pfc_soc_info r8a77995_pinmux_info; 332 extern const struct sh_pfc_soc_info sh7203_pinmux_info; 333 extern const struct sh_pfc_soc_info sh7264_pinmux_info; 334 extern const struct sh_pfc_soc_info sh7269_pinmux_info; 335 extern const struct sh_pfc_soc_info sh73a0_pinmux_info; 336 extern const struct sh_pfc_soc_info sh7720_pinmux_info; 337 extern const struct sh_pfc_soc_info sh7722_pinmux_info; 338 extern const struct sh_pfc_soc_info sh7723_pinmux_info; 339 extern const struct sh_pfc_soc_info sh7724_pinmux_info; 340 extern const struct sh_pfc_soc_info sh7734_pinmux_info; 341 extern const struct sh_pfc_soc_info sh7757_pinmux_info; 342 extern const struct sh_pfc_soc_info sh7785_pinmux_info; 343 extern const struct sh_pfc_soc_info sh7786_pinmux_info; 344 extern const struct sh_pfc_soc_info shx3_pinmux_info; 345 346 /* ----------------------------------------------------------------------------- 347 * Helper macros to create pin and port lists 348 */ 349 350 /* 351 * sh_pfc_soc_info pinmux_data array macros 352 */ 353 354 /* 355 * Describe generic pinmux data 356 * - data_or_mark: *_DATA or *_MARK enum ID 357 * - ids...: List of enum IDs to associate with data_or_mark 358 */ 359 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 360 361 /* 362 * Describe a pinmux configuration without GPIO function that needs 363 * configuration in a Peripheral Function Select Register (IPSR) 364 * - ipsr: IPSR field (unused, for documentation purposes only) 365 * - fn: Function name, referring to a field in the IPSR 366 */ 367 #define PINMUX_IPSR_NOGP(ipsr, fn) \ 368 PINMUX_DATA(fn##_MARK, FN_##fn) 369 370 /* 371 * Describe a pinmux configuration with GPIO function that needs configuration 372 * in both a Peripheral Function Select Register (IPSR) and in a 373 * GPIO/Peripheral Function Select Register (GPSR) 374 * - ipsr: IPSR field 375 * - fn: Function name, also referring to the IPSR field 376 */ 377 #define PINMUX_IPSR_GPSR(ipsr, fn) \ 378 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) 379 380 /* 381 * Describe a pinmux configuration without GPIO function that needs 382 * configuration in a Peripheral Function Select Register (IPSR), and where the 383 * pinmux function has a representation in a Module Select Register (MOD_SEL). 384 * - ipsr: IPSR field (unused, for documentation purposes only) 385 * - fn: Function name, also referring to the IPSR field 386 * - msel: Module selector 387 */ 388 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \ 389 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel) 390 391 /* 392 * Describe a pinmux configuration with GPIO function where the pinmux function 393 * has no representation in a Peripheral Function Select Register (IPSR), but 394 * instead solely depends on a group selection. 395 * - gpsr: GPSR field 396 * - fn: Function name, also referring to the GPSR field 397 * - gsel: Group selector 398 */ 399 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \ 400 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel) 401 402 /* 403 * Describe a pinmux configuration with GPIO function that needs configuration 404 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral 405 * Function Select Register (GPSR), and where the pinmux function has a 406 * representation in a Module Select Register (MOD_SEL). 407 * - ipsr: IPSR field 408 * - fn: Function name, also referring to the IPSR field 409 * - msel: Module selector 410 */ 411 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ 412 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) 413 414 /* 415 * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with 416 * an additional select register that controls physical multiplexing 417 * with another pin. 418 * - ipsr: IPSR field 419 * - fn: Function name, also referring to the IPSR field 420 * - psel: Physical multiplexing selector 421 * - msel: Module selector 422 */ 423 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \ 424 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr) 425 426 /* 427 * Describe a pinmux configuration in which a pin is physically multiplexed 428 * with other pins. 429 * - ipsr: IPSR field 430 * - fn: Function name 431 * - psel: Physical multiplexing selector 432 */ 433 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ 434 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr) 435 436 /* 437 * Describe a pinmux configuration for a single-function pin with GPIO 438 * capability. 439 * - fn: Function name 440 */ 441 #define PINMUX_SINGLE(fn) \ 442 PINMUX_DATA(fn##_MARK, FN_##fn) 443 444 /* 445 * GP port style (32 ports banks) 446 */ 447 448 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ 449 fn(bank, pin, GP_##bank##_##pin, sfx, cfg) 450 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) 451 452 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ 453 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ 454 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ 455 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ 456 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) 457 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) 458 459 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ 460 PORT_GP_CFG_4(bank, fn, sfx, cfg), \ 461 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ 462 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) 463 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) 464 465 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ 466 PORT_GP_CFG_6(bank, fn, sfx, cfg), \ 467 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ 468 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) 469 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) 470 471 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ 472 PORT_GP_CFG_8(bank, fn, sfx, cfg), \ 473 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) 474 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) 475 476 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \ 477 PORT_GP_CFG_9(bank, fn, sfx, cfg), \ 478 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) 479 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) 480 481 #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ 482 PORT_GP_CFG_10(bank, fn, sfx, cfg), \ 483 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) 484 #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) 485 486 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ 487 PORT_GP_CFG_11(bank, fn, sfx, cfg), \ 488 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) 489 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) 490 491 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ 492 PORT_GP_CFG_12(bank, fn, sfx, cfg), \ 493 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ 494 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) 495 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) 496 497 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ 498 PORT_GP_CFG_14(bank, fn, sfx, cfg), \ 499 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) 500 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) 501 502 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ 503 PORT_GP_CFG_15(bank, fn, sfx, cfg), \ 504 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) 505 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) 506 507 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ 508 PORT_GP_CFG_16(bank, fn, sfx, cfg), \ 509 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) 510 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) 511 512 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ 513 PORT_GP_CFG_17(bank, fn, sfx, cfg), \ 514 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) 515 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) 516 517 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ 518 PORT_GP_CFG_18(bank, fn, sfx, cfg), \ 519 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ 520 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) 521 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) 522 523 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \ 524 PORT_GP_CFG_20(bank, fn, sfx, cfg), \ 525 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) 526 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) 527 528 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \ 529 PORT_GP_CFG_21(bank, fn, sfx, cfg), \ 530 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) 531 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0) 532 533 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ 534 PORT_GP_CFG_22(bank, fn, sfx, cfg), \ 535 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) 536 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) 537 538 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ 539 PORT_GP_CFG_23(bank, fn, sfx, cfg), \ 540 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) 541 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) 542 543 #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \ 544 PORT_GP_CFG_24(bank, fn, sfx, cfg), \ 545 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg) 546 #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0) 547 548 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ 549 PORT_GP_CFG_25(bank, fn, sfx, cfg), \ 550 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) 551 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) 552 553 #define PORT_GP_CFG_27(bank, fn, sfx, cfg) \ 554 PORT_GP_CFG_26(bank, fn, sfx, cfg), \ 555 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg) 556 #define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0) 557 558 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ 559 PORT_GP_CFG_27(bank, fn, sfx, cfg), \ 560 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) 561 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) 562 563 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ 564 PORT_GP_CFG_28(bank, fn, sfx, cfg), \ 565 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) 566 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) 567 568 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ 569 PORT_GP_CFG_29(bank, fn, sfx, cfg), \ 570 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) 571 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) 572 573 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ 574 PORT_GP_CFG_30(bank, fn, sfx, cfg), \ 575 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \ 576 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) 577 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) 578 579 #define PORT_GP_32_REV(bank, fn, sfx) \ 580 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ 581 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ 582 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ 583 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ 584 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ 585 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ 586 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ 587 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ 588 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ 589 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ 590 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ 591 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ 592 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ 593 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ 594 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ 595 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) 596 597 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ 598 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx 599 #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str) 600 601 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ 602 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ 603 { \ 604 .pin = (bank * 32) + _pin, \ 605 .name = __stringify(_name), \ 606 .enum_id = _name##_DATA, \ 607 .configs = cfg, \ 608 } 609 #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused) 610 611 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ 612 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) 613 #define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused) 614 615 /* 616 * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin 617 * 618 * The largest GP pin index is obtained by taking the size of a union, 619 * containing one array per GP pin, sized by the corresponding pin index. 620 * As the fields in the CPU_ALL_GP() macro definition are separated by commas, 621 * while the members of a union must be terminated by semicolons, the commas 622 * are absorbed by wrapping them inside dummy attributes. 623 */ 624 #define _GP_ENTRY(bank, pin, name, sfx, cfg) \ 625 deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated 626 #define GP_ASSIGN_LAST() \ 627 GP_LAST = sizeof(union { \ 628 char dummy[0] __attribute__((deprecated, \ 629 CPU_ALL_GP(_GP_ENTRY, unused), \ 630 deprecated)); \ 631 }) 632 633 /* 634 * PORT style (linear pin space) 635 */ 636 637 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) 638 639 #define PORT_10(pn, fn, pfx, sfx) \ 640 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ 641 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ 642 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ 643 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ 644 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) 645 646 #define PORT_90(pn, fn, pfx, sfx) \ 647 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ 648 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ 649 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ 650 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ 651 PORT_10(pn+90, fn, pfx##9, sfx) 652 653 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ 654 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx 655 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 656 657 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ 658 #define PINMUX_GPIO(_pin) \ 659 [GPIO_##_pin] = { \ 660 .pin = (u16)-1, \ 661 .name = __stringify(GPIO_##_pin), \ 662 .enum_id = _pin##_DATA, \ 663 } 664 665 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ 666 #define SH_PFC_PIN_CFG(_pin, cfgs) \ 667 { \ 668 .pin = _pin, \ 669 .name = __stringify(PORT##_pin), \ 670 .enum_id = PORT##_pin##_DATA, \ 671 .configs = cfgs, \ 672 } 673 674 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, 675 * PORT_name_OUT, PORT_name_IN marks 676 */ 677 #define _PORT_DATA(pn, pfx, sfx) \ 678 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ 679 PORT##pfx##_OUT, PORT##pfx##_IN) 680 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) 681 682 /* 683 * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin 684 * 685 * The largest PORT pin index is obtained by taking the size of a union, 686 * containing one array per PORT pin, sized by the corresponding pin index. 687 * As the fields in the CPU_ALL_PORT() macro definition are separated by 688 * commas, while the members of a union must be terminated by semicolons, the 689 * commas are absorbed by wrapping them inside dummy attributes. 690 */ 691 #define _PORT_ENTRY(pn, pfx, sfx) \ 692 deprecated)); char pfx[pn] __attribute__((deprecated 693 #define PORT_ASSIGN_LAST() \ 694 PORT_LAST = sizeof(union { \ 695 char dummy[0] __attribute__((deprecated, \ 696 CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \ 697 deprecated)); \ 698 }) 699 700 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ 701 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ 702 [gpio - (base)] = { \ 703 .name = __stringify(gpio), \ 704 .enum_id = data_or_mark, \ 705 } 706 #define GPIO_FN(str) \ 707 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) 708 709 /* 710 * Pins not associated with a GPIO port 711 */ 712 713 #define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg) 714 #define PIN_NOGP(pin, name, fn) fn(pin, name, 0) 715 716 /* NOGP_ALL - Expand to a list of PIN_id */ 717 #define _NOGP_ALL(pin, name, cfg) PIN_##pin 718 #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL) 719 720 /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ 721 #define _NOGP_PINMUX(_pin, _name, cfg) \ 722 { \ 723 .pin = PIN_##_pin, \ 724 .name = "PIN_" _name, \ 725 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ 726 } 727 #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX) 728 729 /* 730 * PORTnCR helper macro for SH-Mobile/R-Mobile 731 */ 732 #define PORTCR(nr, reg) \ 733 { \ 734 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ 735 GROUP(2, 2, 1, 3), \ 736 GROUP( \ 737 /* PULMD[1:0], handled by .set_bias() */ \ 738 0, 0, 0, 0, \ 739 /* IE and OE */ \ 740 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ 741 /* SEC, not supported */ \ 742 0, 0, \ 743 /* PTMD[2:0] */ \ 744 PORT##nr##_FN0, PORT##nr##_FN1, \ 745 PORT##nr##_FN2, PORT##nr##_FN3, \ 746 PORT##nr##_FN4, PORT##nr##_FN5, \ 747 PORT##nr##_FN6, PORT##nr##_FN7 \ 748 )) \ 749 } 750 751 /* 752 * GPIO number helper macro for R-Car 753 */ 754 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) 755 756 #endif /* __SH_PFC_H */ 757
