1 /*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
27
28 #include <drm/drm_util.h>
29
30 enum link_m_n_set;
31 struct dpll;
32 struct drm_connector;
33 struct drm_device;
34 struct drm_display_mode;
35 struct drm_encoder;
36 struct drm_file;
37 struct drm_format_info;
38 struct drm_framebuffer;
39 struct drm_i915_error_state_buf;
40 struct drm_i915_gem_object;
41 struct drm_i915_private;
42 struct drm_mode_fb_cmd2;
43 struct drm_modeset_acquire_ctx;
44 struct drm_plane;
45 struct drm_plane_state;
46 struct i915_ggtt_view;
47 struct intel_atomic_state;
48 struct intel_crtc;
49 struct intel_crtc_state;
50 struct intel_crtc_state;
51 struct intel_digital_port;
52 struct intel_dp;
53 struct intel_encoder;
54 struct intel_load_detect_pipe;
55 struct intel_plane;
56 struct intel_plane_state;
57 struct intel_remapped_info;
58 struct intel_rotation_info;
59
60 enum i915_gpio {
61 GPIOA,
62 GPIOB,
63 GPIOC,
64 GPIOD,
65 GPIOE,
66 GPIOF,
67 GPIOG,
68 GPIOH,
69 __GPIOI_UNUSED,
70 GPIOJ,
71 GPIOK,
72 GPIOL,
73 GPIOM,
74 GPION,
75 GPIOO,
76 };
77
78 /*
79 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
80 * rest have consecutive values and match the enum values of transcoders
81 * with a 1:1 transcoder -> pipe mapping.
82 */
83 enum pipe {
84 INVALID_PIPE = -1,
85
86 PIPE_A = 0,
87 PIPE_B,
88 PIPE_C,
89 PIPE_D,
90 _PIPE_EDP,
91
92 I915_MAX_PIPES = _PIPE_EDP
93 };
94
95 #define pipe_name(p) ((p) + 'A')
96
97 enum transcoder {
98 INVALID_TRANSCODER = -1,
99 /*
100 * The following transcoders have a 1:1 transcoder -> pipe mapping,
101 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
102 * rest have consecutive values and match the enum values of the pipes
103 * they map to.
104 */
105 TRANSCODER_A = PIPE_A,
106 TRANSCODER_B = PIPE_B,
107 TRANSCODER_C = PIPE_C,
108 TRANSCODER_D = PIPE_D,
109
110 /*
111 * The following transcoders can map to any pipe, their enum value
112 * doesn't need to stay fixed.
113 */
114 TRANSCODER_EDP,
115 TRANSCODER_DSI_0,
116 TRANSCODER_DSI_1,
117 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
118 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
119
120 I915_MAX_TRANSCODERS
121 };
122
transcoder_name(enum transcoder transcoder)123 static inline const char *transcoder_name(enum transcoder transcoder)
124 {
125 switch (transcoder) {
126 case TRANSCODER_A:
127 return "A";
128 case TRANSCODER_B:
129 return "B";
130 case TRANSCODER_C:
131 return "C";
132 case TRANSCODER_D:
133 return "D";
134 case TRANSCODER_EDP:
135 return "EDP";
136 case TRANSCODER_DSI_A:
137 return "DSI A";
138 case TRANSCODER_DSI_C:
139 return "DSI C";
140 default:
141 return "<invalid>";
142 }
143 }
144
transcoder_is_dsi(enum transcoder transcoder)145 static inline bool transcoder_is_dsi(enum transcoder transcoder)
146 {
147 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
148 }
149
150 /*
151 * Global legacy plane identifier. Valid only for primary/sprite
152 * planes on pre-g4x, and only for primary planes on g4x-bdw.
153 */
154 enum i9xx_plane_id {
155 PLANE_A,
156 PLANE_B,
157 PLANE_C,
158 };
159
160 #define plane_name(p) ((p) + 'A')
161 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
162
163 /*
164 * Per-pipe plane identifier.
165 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
166 * number of planes per CRTC. Not all platforms really have this many planes,
167 * which means some arrays of size I915_MAX_PLANES may have unused entries
168 * between the topmost sprite plane and the cursor plane.
169 *
170 * This is expected to be passed to various register macros
171 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
172 */
173 enum plane_id {
174 PLANE_PRIMARY,
175 PLANE_SPRITE0,
176 PLANE_SPRITE1,
177 PLANE_SPRITE2,
178 PLANE_SPRITE3,
179 PLANE_SPRITE4,
180 PLANE_SPRITE5,
181 PLANE_CURSOR,
182
183 I915_MAX_PLANES,
184 };
185
186 #define for_each_plane_id_on_crtc(__crtc, __p) \
187 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
188 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
189
190 #define for_each_dbuf_slice_in_mask(__slice, __mask) \
191 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
192 for_each_if((BIT(__slice)) & (__mask))
193
194 #define for_each_dbuf_slice(__slice) \
195 for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1)
196
197 enum port {
198 PORT_NONE = -1,
199
200 PORT_A = 0,
201 PORT_B,
202 PORT_C,
203 PORT_D,
204 PORT_E,
205 PORT_F,
206 PORT_G,
207 PORT_H,
208 PORT_I,
209
210 I915_MAX_PORTS
211 };
212
213 #define port_name(p) ((p) + 'A')
214
215 /*
216 * Ports identifier referenced from other drivers.
217 * Expected to remain stable over time
218 */
port_identifier(enum port port)219 static inline const char *port_identifier(enum port port)
220 {
221 switch (port) {
222 case PORT_A:
223 return "Port A";
224 case PORT_B:
225 return "Port B";
226 case PORT_C:
227 return "Port C";
228 case PORT_D:
229 return "Port D";
230 case PORT_E:
231 return "Port E";
232 case PORT_F:
233 return "Port F";
234 case PORT_G:
235 return "Port G";
236 case PORT_H:
237 return "Port H";
238 case PORT_I:
239 return "Port I";
240 default:
241 return "<invalid>";
242 }
243 }
244
245 enum tc_port {
246 PORT_TC_NONE = -1,
247
248 PORT_TC1 = 0,
249 PORT_TC2,
250 PORT_TC3,
251 PORT_TC4,
252 PORT_TC5,
253 PORT_TC6,
254
255 I915_MAX_TC_PORTS
256 };
257
258 enum tc_port_mode {
259 TC_PORT_TBT_ALT,
260 TC_PORT_DP_ALT,
261 TC_PORT_LEGACY,
262 };
263
264 enum dpio_channel {
265 DPIO_CH0,
266 DPIO_CH1
267 };
268
269 enum dpio_phy {
270 DPIO_PHY0,
271 DPIO_PHY1,
272 DPIO_PHY2,
273 };
274
275 enum aux_ch {
276 AUX_CH_A,
277 AUX_CH_B,
278 AUX_CH_C,
279 AUX_CH_D,
280 AUX_CH_E, /* ICL+ */
281 AUX_CH_F,
282 AUX_CH_G,
283 AUX_CH_H,
284 AUX_CH_I,
285 };
286
287 #define aux_ch_name(a) ((a) + 'A')
288
289 /* Used by dp and fdi links */
290 struct intel_link_m_n {
291 u32 tu;
292 u32 gmch_m;
293 u32 gmch_n;
294 u32 link_m;
295 u32 link_n;
296 };
297
298 enum phy {
299 PHY_NONE = -1,
300
301 PHY_A = 0,
302 PHY_B,
303 PHY_C,
304 PHY_D,
305 PHY_E,
306 PHY_F,
307 PHY_G,
308 PHY_H,
309 PHY_I,
310
311 I915_MAX_PHYS
312 };
313
314 #define phy_name(a) ((a) + 'A')
315
316 enum phy_fia {
317 FIA1,
318 FIA2,
319 FIA3,
320 };
321
322 #define for_each_pipe(__dev_priv, __p) \
323 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
324 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
325
326 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
327 for_each_pipe(__dev_priv, __p) \
328 for_each_if((__mask) & BIT(__p))
329
330 #define for_each_cpu_transcoder(__dev_priv, __t) \
331 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
332 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
333
334 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
335 for_each_cpu_transcoder(__dev_priv, __t) \
336 for_each_if ((__mask) & BIT(__t))
337
338 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
339 for ((__p) = 0; \
340 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
341 (__p)++)
342
343 #define for_each_sprite(__dev_priv, __p, __s) \
344 for ((__s) = 0; \
345 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
346 (__s)++)
347
348 #define for_each_port(__port) \
349 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
350
351 #define for_each_port_masked(__port, __ports_mask) \
352 for_each_port(__port) \
353 for_each_if((__ports_mask) & BIT(__port))
354
355 #define for_each_phy_masked(__phy, __phys_mask) \
356 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
357 for_each_if((__phys_mask) & BIT(__phy))
358
359 #define for_each_crtc(dev, crtc) \
360 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
361
362 #define for_each_intel_plane(dev, intel_plane) \
363 list_for_each_entry(intel_plane, \
364 &(dev)->mode_config.plane_list, \
365 base.head)
366
367 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
368 list_for_each_entry(intel_plane, \
369 &(dev)->mode_config.plane_list, \
370 base.head) \
371 for_each_if((plane_mask) & \
372 drm_plane_mask(&intel_plane->base))
373
374 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
375 list_for_each_entry(intel_plane, \
376 &(dev)->mode_config.plane_list, \
377 base.head) \
378 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
379
380 #define for_each_intel_crtc(dev, intel_crtc) \
381 list_for_each_entry(intel_crtc, \
382 &(dev)->mode_config.crtc_list, \
383 base.head)
384
385 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
386 list_for_each_entry(intel_crtc, \
387 &(dev)->mode_config.crtc_list, \
388 base.head) \
389 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
390
391 #define for_each_intel_encoder(dev, intel_encoder) \
392 list_for_each_entry(intel_encoder, \
393 &(dev)->mode_config.encoder_list, \
394 base.head)
395
396 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
397 list_for_each_entry(intel_encoder, \
398 &(dev)->mode_config.encoder_list, \
399 base.head) \
400 for_each_if((encoder_mask) & \
401 drm_encoder_mask(&intel_encoder->base))
402
403 #define for_each_intel_dp(dev, intel_encoder) \
404 for_each_intel_encoder(dev, intel_encoder) \
405 for_each_if(intel_encoder_is_dp(intel_encoder))
406
407 #define for_each_intel_connector_iter(intel_connector, iter) \
408 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
409
410 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
411 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
412 for_each_if((intel_encoder)->base.crtc == (__crtc))
413
414 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
415 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
416 for_each_if((intel_connector)->base.encoder == (__encoder))
417
418 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
419 for ((__i) = 0; \
420 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
421 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
422 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
423 (__i)++) \
424 for_each_if(plane)
425
426 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
427 for ((__i) = 0; \
428 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
429 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
430 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
431 (__i)++) \
432 for_each_if(plane)
433
434 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
435 for ((__i) = 0; \
436 (__i) < (__state)->base.dev->mode_config.num_crtc && \
437 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
438 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
439 (__i)++) \
440 for_each_if(crtc)
441
442 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
443 for ((__i) = 0; \
444 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
445 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
446 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
447 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
448 (__i)++) \
449 for_each_if(plane)
450
451 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
452 for ((__i) = 0; \
453 (__i) < (__state)->base.dev->mode_config.num_crtc && \
454 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
455 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
456 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
457 (__i)++) \
458 for_each_if(crtc)
459
460 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
461 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
462 (__i) >= 0 && \
463 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
464 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
465 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
466 (__i)--) \
467 for_each_if(crtc)
468
469 #define intel_atomic_crtc_state_for_each_plane_state( \
470 plane, plane_state, \
471 crtc_state) \
472 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
473 ((crtc_state)->uapi.plane_mask)) \
474 for_each_if ((plane_state = \
475 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
476
477 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
478 for ((__i) = 0; \
479 (__i) < (__state)->base.num_connector; \
480 (__i)++) \
481 for_each_if ((__state)->base.connectors[__i].ptr && \
482 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
483 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
484
485 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
486 u8 active_pipes);
487 void intel_link_compute_m_n(u16 bpp, int nlanes,
488 int pixel_clock, int link_clock,
489 struct intel_link_m_n *m_n,
490 bool constant_n, bool fec_enable);
491 bool is_ccs_modifier(u64 modifier);
492 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane);
493 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
494 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
495 u32 pixel_format, u64 modifier);
496 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
497 enum drm_mode_status
498 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
499 const struct drm_display_mode *mode);
500 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
501 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
502
503 void intel_plane_destroy(struct drm_plane *plane);
504 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state);
505 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
506 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
507 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
508 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
509 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
510 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
511 const char *name, u32 reg, int ref_freq);
512 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
513 const char *name, u32 reg);
514 void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
515 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
516 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
517 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
518 unsigned int intel_fb_xy_to_linear(int x, int y,
519 const struct intel_plane_state *state,
520 int plane);
521 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
522 int color_plane, unsigned int height);
523 void intel_add_fb_offsets(int *x, int *y,
524 const struct intel_plane_state *state, int plane);
525 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
526 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
527 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
528 int intel_display_suspend(struct drm_device *dev);
529 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
530 void intel_encoder_destroy(struct drm_encoder *encoder);
531 struct drm_display_mode *
532 intel_encoder_current_mode(struct intel_encoder *encoder);
533 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
534 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
535 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
536 enum port port);
537 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
538 struct drm_file *file_priv);
539 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
540 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
541 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
542
543 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
544 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
545 struct intel_digital_port *dig_port,
546 unsigned int expected_mask);
547 int intel_get_load_detect_pipe(struct drm_connector *connector,
548 struct intel_load_detect_pipe *old,
549 struct drm_modeset_acquire_ctx *ctx);
550 void intel_release_load_detect_pipe(struct drm_connector *connector,
551 struct intel_load_detect_pipe *old,
552 struct drm_modeset_acquire_ctx *ctx);
553 struct i915_vma *
554 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
555 const struct i915_ggtt_view *view,
556 bool uses_fence,
557 unsigned long *out_flags);
558 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
559 struct drm_framebuffer *
560 intel_framebuffer_create(struct drm_i915_gem_object *obj,
561 struct drm_mode_fb_cmd2 *mode_cmd);
562 int intel_prepare_plane_fb(struct drm_plane *plane,
563 struct drm_plane_state *new_state);
564 void intel_cleanup_plane_fb(struct drm_plane *plane,
565 struct drm_plane_state *old_state);
566
567 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
568 enum pipe pipe);
569
570 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
571 const struct dpll *dpll);
572 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
573 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
574 bool intel_fuzzy_clock_check(int clock1, int clock2);
575
576 void intel_prepare_reset(struct drm_i915_private *dev_priv);
577 void intel_finish_reset(struct drm_i915_private *dev_priv);
578 void intel_dp_get_m_n(struct intel_crtc *crtc,
579 struct intel_crtc_state *pipe_config);
580 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
581 enum link_m_n_set m_n);
582 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
583 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
584 struct dpll *best_clock);
585 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
586
587 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
588 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
589 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
590 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
591 enum intel_display_power_domain
592 intel_aux_power_domain(struct intel_digital_port *dig_port);
593 enum intel_display_power_domain
594 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
595 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
596 struct intel_crtc_state *pipe_config);
597 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
598 struct intel_crtc_state *crtc_state);
599
600 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
601 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
602 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
603 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
604 const struct intel_plane_state *plane_state);
605 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
606 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
607 const struct intel_plane_state *plane_state);
608 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
609 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
610 int plane);
611 int skl_check_plane_surface(struct intel_plane_state *plane_state);
612 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
613 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
614 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
615 u32 pixel_format, u64 modifier,
616 unsigned int rotation);
617 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
618 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
619
620 struct intel_display_error_state *
621 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
622 void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
623 struct intel_display_error_state *error);
624
625 bool
626 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
627 uint64_t modifier);
628
629 /* modesetting */
630 void intel_modeset_init_hw(struct drm_i915_private *i915);
631 int intel_modeset_init_noirq(struct drm_i915_private *i915);
632 int intel_modeset_init_nogem(struct drm_i915_private *i915);
633 int intel_modeset_init(struct drm_i915_private *i915);
634 void intel_modeset_driver_remove(struct drm_i915_private *i915);
635 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
636 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
637 void intel_display_resume(struct drm_device *dev);
638 void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
639
640 /* modesetting asserts */
641 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
642 enum pipe pipe);
643 void assert_pll(struct drm_i915_private *dev_priv,
644 enum pipe pipe, bool state);
645 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
646 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
647 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
648 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
649 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
650 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
651 enum pipe pipe, bool state);
652 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
653 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
654 void assert_pipe(struct drm_i915_private *dev_priv,
655 enum transcoder cpu_transcoder, bool state);
656 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
657 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
658
659 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
660 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
661 * which may not necessarily be a user visible problem. This will either
662 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
663 * enable distros and users to tailor their preferred amount of i915 abrt
664 * spam.
665 */
666 #define I915_STATE_WARN(condition, format...) ({ \
667 int __ret_warn_on = !!(condition); \
668 if (unlikely(__ret_warn_on)) \
669 if (!WARN(i915_modparams.verbose_state_checks, format)) \
670 DRM_ERROR(format); \
671 unlikely(__ret_warn_on); \
672 })
673
674 #define I915_STATE_WARN_ON(x) \
675 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
676
677 #endif
678
